KR20130121042A - Semiconductor reflow processing for feature fill - Google Patents

Abstract

A method for filling at least one part of a feature on a material includes: a step for obtaining the material including the feature, a step for depositing a first conformal conductive layer on the feature, and a step for thermally processing the material to reflow the first conformal conductive layer on the feature. [Reference numerals] (106) Annealing;(AA) Barrier and seed deposition;(BB) ECD seed deposition;(CC) Replow for partial or total filling;(DD) Gap filling or capping

Description

Semiconductor Reflow Processing for Feature Fill {SEMICONDUCTOR REFLOW PROCESSING FOR FEATURE FILL}

The present invention relates to a conductive material, such as copper (Cu), cobalt (Co), nickel, in features of microelectronic workpieces (especially in trenches and vias, in damascene applications). Methods for electrochemically depositing metals such as (Ni), gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminum (Al), and alloys thereof.

An integrated circuit is an interconnected ensemble of devices formed in and in a dielectric material overlying a surface of the semiconductor material. Devices that can be formed in a semiconductor include MOS transistors, bipolar transistors, diodes, and diffused resistors. Devices that can be formed in the dielectric include thin film resistors and capacitors. The devices are interconnected by conductor paths formed in the dielectric. Typically, two or three or more levels of conductor paths are used as interconnects, with successive levels separated by a dielectric layer. In current technology, copper and silicon oxide are generally used as conductors and dielectrics, respectively.

Depositions in copper interconnects typically include a dielectric layer, barrier layer, seed layer, copper fill, and copper cap. Since copper tends to diffuse into the dielectric material, barrier layers are used to isolate the copper precipitate from the dielectric material. However, it should be understood that for metal interconnects other than copper, barrier layers may not be required. Barrier layers typically consist of refractory metals or refractory compounds, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and the like. Other suitable barrier layer materials may include manganese (Mn) and manganese nitride (MnN). The barrier layer is typically formed using a deposition technique called physical vapor deposition (PVD), but can also be formed by using other deposition techniques such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The seed layer can be deposited on the barrier layer. However, as well as separate seed layers, such as direct on barrier (DOB) deposition, for example titanium ruthenium (TiRu), tantalum ruthenium (TaRu), tungsten ruthenium (WRu), and It is to be understood that barrier layers made of alloys or co-deposited metals on which interconnect metals can be deposited thereon without the need for other barrier layers to be used are also within the scope of the present invention.

In one non-limiting example, the seed layer can be a copper seed layer. As in other non-limiting examples, the seed layer may be a copper alloy seed layer, such as copper manganese, copper cobalt, or copper nickel alloys. In the case of depositing copper on the feature, there are several exemplary options for the seed layer. First, the seed layer can be a PVD copper seed layer. See, for example, FIG. 3 for description of a process involving PVD copper seed deposition. The seed layer can also be formed by using other deposition techniques such as CVD or ALD.

Second, the seed layer can be a laminated film, such as a liner layer and a PVD seed layer. The liner layer is a material used between the barrier and the PVD seed to alleviate discontinuous seed problems and to improve the adhesion of the PVD seed. The liners are typically precious metals such as ruthenium (Ru), platinum (Pt), palladium (Pd), and osmium (Os), but the list may also include cobalt (Co) and nickel (Ni). Currently, CVD Ru and CVD Co are common liners; However, liner layers may also be formed by using other deposition techniques such as ALD or PVD.

Third, the seed layer may be a secondary seed layer. The secondary seed layer is generally formed from precious metals such as Ru, Pt, Pd, and Os, but the list may also include Co and Ni, and most commonly CVD Ru and CVD Co, with the liner layer. Similar (such as seed and liner layers, secondary seed layers may also be formed by using other deposition techniques such as ALD or PVD). The difference is that the secondary seed layers function as seed layers, while the liner layer is an intermediate layer between the barrier layer and the PVD seed. For example, see FIGS. 5 and 6 for description of processes including ECD seed deposition in FIG. 5 and flash deposition in FIG. 6, respectively, as described below, followed by secondary seed depositions. See (“flash” deposition is primarily on the field and under the feature without significant deposition on the sidewalls of the feature).

After the seed layer is deposited according to one of the examples described above, the feature may include a seed layer enhancement (SLE) layer, which has a thickness of the deposited metal, eg, about 2 nm. It is a thin layer of copper. SLE layers are also known as electrochemically deposited seeds (or ECD seeds). See, for example, FIG. 4 for description of a process involving PVD seed deposition and ECD seed deposition. See, for example, FIG. 5 for description of a process involving secondary seed deposition and ECD seed deposition. As shown in FIGS. 4 and 5, the ECD seed may be a conformally deposited layer.

ECD copper seeds are typically deposited using basic chemistry that includes highly diluted copper ethylenediamine (EDA) complexes. ECD copper seed may also be deposited using other copper complexes such as citrate, tartrate, urea, and the like, and have a pH range of about 2 to about 11, about 3 to about 10, or And may be deposited in a pH range of about 4 to about 10.

After the seed layer is deposited according to one of the examples described above (which may also include an optional ECD seed), conventional ECD fills and caps may be performed on the feature using, for example, acidic deposition chemistry. Can be. Conventional ECD copper acid chemistries include, for example, copper sulfide, sulfuric acid, methane sulfonic acid, hydrochloric acid, and organic additives (such as accelerators, inhibitors, and levelers). It may include. Electrochemical deposition of copper has been known to be the most cost effective way to deposit copper metallization layers. In addition to being economically viable, ECD deposition techniques provide a substantially bottom up (eg, non-conformal) metal fill that is mechanically and electrically suitable for interconnect structures.

In particular, conventional ECD fill in small features can result in lower quality interconnects. For example, conventional ECD copper fill can produce voids, particularly in features having a size of less than 30 nm. As an example of the type of voids formed using conventional ECD deposition, the openings of the feature can be pinched off. Other types of voids can also result from using a conventional ECD copper fill process in small features. Other inherent characteristics of the deposition formed using conventional ECD copper fill and these voids can increase the resistance of the interconnect, thereby slowing down the electrical performance of the device and degrading the reliability of the copper interconnect. Let's do it.

Thus, there is a need for an improved, substantially void-free metal fill process for features. Such substantially void-free metal fills may be useful in small features, for example, features having an aperture size of less than 30 nm.

This summary is provided to introduce a selection of concepts in a simplified form that is further described below in the Detailed Description. This Summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

According to one embodiment of the invention, a method for at least partially filling a feature on a workpiece is provided. The method generally thermally processes the material to obtain a material comprising a feature, deposit a first conformal conductive layer on the feature, and reflow the first conformal conductive layer on the feature. It includes a step.

According to another embodiment of the present invention, a method is provided for at least partially filling a feature on a workpiece. The method generally comprises obtaining a material comprising a feature, depositing a barrier layer on the feature, and depositing a first conductive layer on the feature after the barrier layer, wherein the first conductive layer is seeded. It is a layer. The method includes depositing a second conductive layer on the feature after the first conductive layer, wherein the second conductive layer is a formation following conductive layer, and the material to reflow the second conductive layer in the feature. Further comprising annealing.

According to another embodiment of the present invention, a work piece is provided. The material generally includes at least one feature having a size of less than 30 nm, and a substantially void-free conductive layer in the feature.

Many of the above-described aspects and accompanying advantages of the present invention will be more readily understood with reference to the following detailed description, taken in conjunction with the accompanying drawings:
1 is a schematic flow diagram showing process steps and exemplary feature development of an exemplary embodiment of the present invention;
2 is a comparison diagram of exemplary process steps that may be used with prior art processes and conventional processes in accordance with embodiments of the present invention;
3 is a schematic process diagram showing exemplary feature development and process steps using a prior art main damascene process including barrier deposition, seed deposition, and conventional ECD fill and cap deposition;
4 is a schematic showing exemplary feature development and process steps using a prior art SLE (also known as ECD seed) process including barrier deposition, seed deposition, ECD seed deposition, and conventional ECD fill and cap deposition. A process diagram;
FIG. 5 is a schematic process diagram showing exemplary feature development and process steps using a prior art ECD seed process including barrier deposition, secondary seed deposition, ECD seed deposition, and conventional ECD fill and cap deposition; FIG.
6 illustrates process steps and exemplary feature development using prior art deposition for a secondary seed process having a flash layer, including barrier deposition, secondary seed deposition, flash deposition, and conventional ECD fill and cap deposition. A schematic process diagram depicting;
7 is a schematic process diagram illustrating process steps and exemplary feature development of a number of exemplary embodiments of the present invention;
8 is a diagram of exemplary process steps for deposition on damascene features having feature diameters of about 30 nm in accordance with embodiments of the present invention for various exemplary wafers;
FIG. 9 is a graph of 120 micron long line resistance resistance value results obtained from the exemplary wafers described in FIG. 8;
FIG. 10 is a graph of 1 meter long line resistance resistance results obtained from the example wafers described in FIG. 8;
FIG. 11 is a graph of 1 meter long line resistance resistive-capacitive delay results obtained from the example wafers described in FIG. 8;
12 includes a transmission electron microscopy (TEM) photograph of a substantially void-free gap fill for a damascene feature with a feature diameter of about 30 nm in accordance with embodiments of the present invention.

Embodiments of the present invention relate to a material, such as processing assemblies for processing semiconductor wafers, devices or materials, and methods of processing the same. The term material, wafer, or semiconductor wafer refers to semiconductor wafers and other substrates or wafers, grass, masks, and optical or memory media, MEMS substrates, or micro-electronic, micro-mechanical, or micro electro-mechanical devices. By any flat media or article comprising any other material having.

The processes described herein will be used for metal or metal alloy deposition in the features of the materials, the features including trenches and vias. In one embodiment of the invention, the process can be used on small features, for example features having a feature diameter of less than 30 nm. However, it should be understood that the processes described herein are applicable to any feature size. The dimension sizes discussed in this application are feature dimensions after etching in the upper opening of the feature. The processes described herein can be applied to various forms of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, and alloy deposition, eg, damascene applications. In embodiments of the invention, the damascene features are less than 30 nm, less than about 5 to 30 nm, less than about 10 to 30 nm, about 15 to about 20 nm, less than about 20 to 30 nm, less than 20 nm, 10 nm. Less than and about 5 to about 10 nm in size.

The descriptive terms "micro-feature material" and "material" as used herein include all structures and layers that have been previously deposited and formed at a given point in processing, and are merely such as shown in FIG. It should be understood that it is not limited to structures and layers.

It should be understood that the processes described herein may also be varied for metal or metal alloy deposition in high aspect ratio features, eg, vias in through silicon via (TSV) features.

Although generally described as metal deposition in the present application, it should be understood that the term "metal" also considers metal alloys. Such metals and metal alloys may be used to form the seed layer or to completely or partially fill the feature. Exemplary copper alloys may include, but are not limited to, copper manganese and copper aluminum. As a non-limiting example, the alloy composition ratio may range from about 0.5% to about 6% secondary alloy metal as compared to the primary alloy metal (eg, Cu, Co, Ni, Ag, Au, etc.).

As described above, conventional fabrication of metal interconnects may include suitable deposition of a barrier layer on a dielectric material to prevent diffusion of metal into the dielectric material. Suitable barrier layers may include, for example, Ta, Ti, TiN, TaN, Mn, or MnN. Suitable barrier deposition methods can include PVD, ALD, and CVD; However, PVD is the most common process for barrier layer deposition. Barrier layers are typically used to separate copper or copper alloys from dielectric materials; However, it should be understood that in the case of other metal interconnects, diffusion may not be a problem and a barrier layer may not be necessary.

Barrier layer deposition may be followed by optional seed layer deposition. In the case of depositing metal on the feature, there are several options for the seed layer. As described above, the seed layer may be (1) a seed layer (a non-limiting example, a PVD copper seed layer). The seed layer can be a metal layer such as copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, ruthenium, and alloys thereof. The seed layer may also be a (2) liner layer and a laminated film of seed layer (non-limiting examples, such as CVD Ru liner layer and PVD copper seed layer) or (3) secondary seed layer (non-limiting example, CVD Or ALD Ru secondary seed layer). However, it should be understood that other methods of depositing these exemplary seed layers should be considered by the present invention.

As described above, the liner layer is a material used between the barrier layer and the seed layer to mitigate discontinuous seed problems and to improve the adhesion of the seed layer. The liners are typically precious metals such as Ru, Pt, Pd and Os, but the list may also include Co and Ni. Currently, CVD Ru and CVD Co are common liners; However, liner layers can also be formed by using other deposition techniques such as PVD or ALD. The thickness of the liner layer may range from about 5 kPa to about 50 kPa for damascene applications.

In addition, the secondary seed layer, described above, is typically formed from precious metals such as Ru, Pt, Pd, and Os, but the list may also include Co and Ni and most commonly CVD Ru and CVD Co. In, similar to the liner layer. The difference is that the secondary seed layer functions as a seed layer, while the liner layer is an intermediate layer between the barrier layer and the seed layer. Secondary seed layers can also be formed by using other deposition techniques such as PVD or ALD.

The liner or secondary seed precipitate removes any surface oxides, densifies the secondary seed or liner layer, and improves the surface properties of the precipitate to improve the forming gaseous environment (eg, 3-5% hydrogen or helium in nitrogen). In 3-5% hydrogen) at a temperature of about 100 ° C to about 500 ° C. The liner layer or secondary seed precipitate may further be passivated by soaking in gaseous nitrogen (N 2 gas) or other passivation environments to prevent surface oxidation. Passivation of the liner or secondary seed is described in US Pat. No. 8357599, registered January 22, 2013.

After the seed layer is deposited (PVD copper seed-PVD copper seed includes a CVD Ru liner or CVD Ru secondary seed), or one of non-limiting examples of other deposited metals or metal alloys, layer combinations, or deposition techniques. The feature may form a conformal metal layer after the seed layer. However, it should also be understood that the conformal metal layer can be deposited directly on the barrier layer, ie without the seed layer.

In one embodiment of the invention, the conformal layer is deposited using an ECD seed process, and then using a process referred to as ECD seed "plus" deposition (or ECD seed "plus") comprising a thermal treatment step. can be changed. In other embodiments of the invention, the conformal layer may be deposited using CVD, ALD or other deposition techniques, followed by a thermal treatment step. According to embodiments of the present invention, the conformal layer is "flowable" or mobile when thermally treated or annealed.

In this embodiment, the ECD seed “plus” is generally referred to as a thermal treatment step, such as an ECD metal seed deposition plus annealing step. In one embodiment of the invention, the thermal treatment step may result in some or all of the reflow of seed deposition. Increasing the temperature in the ECD seed layer helps the mobility of the atoms in the layer and improves their ability to fill the structure.

In contrast to conventional ECD metal fills (using acidic chemical properties), ECD seed “plus” deposition is similar to ECD seed deposition (using basic chemical properties), but adds a thermal treatment step. In addition, instead of just depositing a seed layer, an ECD seed “plus” can be performed to partially or completely fill the features. By the ECD seed “plus” process, substantially void-free filling of small features can be achieved, as described in more detail below (see image of substantially void-free filling in the small features of FIG. 12). ).

The chemical properties used in the ECD chamber for ECD seed “plus” deposition are based on the basic chemical properties, eg, about 8 to about 11, in one embodiment of the invention, about 8 to about 10, and one embodiment of the present disclosure. In an example, Cu (ethylenediamine) 2 may be included at a pH in the range of about 9.3. However, it should be understood that acidic chemical properties with suitable organic additives may also be used to achieve conformal ECD seed deposition.

After ECD seed deposition, the workpiece may then be rotated, cleaned, and dried (SRD) or other cleaning processes. The ECD seed is then heated to a temperature that is warm enough for the seed to reflow but not too hot so that the material or members on the material are damaged or degraded. For example, the temperature may range from about 100 ° C. to about 500 ° C. for seed reflow in the features. Suitable thermal treatment or annealing temperatures range from about 100 ° C. to about 500 ° C., and are capable of maintaining temperatures that lasted within a temperature range of about 200 ° C. to about 400 ° C., and at least about 250 ° C. to about 350 ° C. Can be achieved.

The thermal treatment or annealing process can be carried out using a forming or inert gas, pure hydrogen, or a reducing gas such as ammonia (NH 3). During reflow, as the shape of the deposition changes, as shown in FIG. 7, metal deposits may collect at the bottom of the feature. In addition to reflow during the thermal treatment process, metal precipitates can also grow larger crystals and reduce film resistivity. Inert gas can be used to cool the material after heating.

After the ECD seed “plus” deposition and thermal treatment process is completed to partially or completely fill the feature, conventional acidic chemical properties can be used to complete the deposition process for gap fill and cap deposition. Acidic chemical metal deposition steps are generally used to fill large structures and to maintain the proper film thickness needed for subsequent polishing steps, since it is generally a faster process than ECD seeds and saves time and reduces processing costs. do.

As shown in FIGS. 1 and 7, the ECD seed deposition and reflow steps may be repeated to ensure full filling of the feature with the ECD seed. In that regard, the processes described herein can include one or more ECD seed deposition, cleaning (such as SRD), and thermal processing step cycles.

Referring to FIG. 1, the reflow process 100 and exemplary features created by the reflow process are shown. Material 112 may be a dielectric material on a crystalline silicon material that includes at least one feature 122 in an exemplary embodiment. In an exemplary step 102, the feature 122 is lined with the barrier layer 114 and the seed layer 115. In exemplary step 104, feature 122 of material 112 received a layer of ECD seed material 116 on seed layer 115. In the exemplary annealing step 106, the material is annealed to a suitable temperature to cause the exemplary reflow step 108 to promote partial or full filling. During the annealing step, the ECD seed material 116 flows into the feature 122 to form the fill 118, with at least a detrimental effect, if any, on the workpiece 112 or the features contained therein. . In an exemplary embodiment, the ECD seed deposition step 104, annealing step 106, and reflow step 108 may be repeated to obtain the desired properties of the fill 118. The number of repeating steps may depend on the structure. Once the fill 118 reaches the desired dimensions, the exemplary cap step 110 can be used to terminate the process in which additional material 120 is deposited on the feature, in preparation for further material 112 processing.

Referring to FIG. 2, process flow examples are provided wherein embodiments of the present invention can be used in conjunction with and in conjunction with other material surface deposition processes. The previously developed process will be described first. First, the TSV process involves the deposition of a barrier layer, seed layer, and conventional ECD fill. Second, the ECD seed (also known as SLE) process includes the deposition of a barrier layer, seed layer, ECD seed layer, and conventional ECD fill. Third, an ECD seed (SLE) process with a liner includes deposition of a barrier layer, liner layer, seed layer, ECD seed layer, and conventional ECD fill. Fourth, an ECD seed (SLE) process with a secondary seed includes deposition of a barrier layer, a secondary seed layer, an ECD seed layer, and a conventional ECD fill. Fifth, an ECD seed (SLE) process with secondary seed and flash includes deposition of a barrier layer, secondary seed layer, flash layer, ECD seed layer, and conventional ECD fill. Sixth, an ECD seed (DOB) process includes the deposition of a barrier layer, an ECD seed layer, and a conventional ECD fill. This is a DOB process because there is no deposition of a secondary seed, liner, or seed layer; More precisely, the ECD seed layer is deposited directly on the plateable barrier layer.

Still referring to FIG. 2, processes in accordance with embodiments of the present invention will now be described. Seventh, an ECD seed plus (DOB) process includes the deposition of a barrier layer, an ECD seed “plus” precipitate, and a conventional ECD fill and / or cap. As in the sixth example above, this is also a DOB process because there is no deposition of a secondary seed, liner, or seed layer; More precisely, the ECD seed layer is deposited directly on the plateable barrier layer. Eighth, the ECD seed plus process includes the deposition of a barrier layer, a secondary seed layer, an ECD seed “plus” precipitate, and a conventional ECD fill and / or cap. Ninth, an ECD seed plus process without ECD includes the deposition of a barrier layer, a secondary seed layer, and an ECD seed “plus” precipitate. The tenth, secondary seedless ECD seed plus process includes the deposition of a barrier layer, seed layer, ECD seed “plus” precipitate, and conventional ECD fill and / or cap. Eleventh, an ECD seed plus process with liner and seed includes deposition of a barrier layer, liner layer, seed layer, ECD seed “plus” precipitate, and conventional ECD fill and / or cap.

Referring to FIG. 7, another exemplary process in accordance with embodiments of the present invention is provided. In the first step, the material having the barrier layer and the secondary seed layer is thermally treated or annealed before the ECD seed step to remove any surface oxides, densify the precipitate, and improve the surface properties of the precipitate. Although the seed layer shown in FIG. 7 is a secondary seed layer, it should be understood that it may also be a seed layer or a lamination film of a liner layer and a seed layer. Suitable thermal treatment or annealing conditions may possibly include temperatures of about 200 ° C. to about 400 ° C. for about one (1) to about ten (10) minutes in the forming gas or pure hydrogen. As mentioned above, the material may alternatively be thermally treated in an inert gas such as N 2, argon (Ar) or helium (He). Reducing gases such as ammonia (NH 3) may also be used.

In the second step, the material is transferred to a deposition chamber for conformal deposition of the ECD seed layer. The thickness of the deposited film is changed depending on the feature dimensions of the metal precipitate and the desired properties.

In a third step, the workpiece is rotated to clean the workpiece, washed with deionized (DI) water and dried.

In a fourth step, the workpiece is thermally treated or annealed to a temperature in the range of 200 ° C. to 400 ° C. to reflow the metal into the feature.

In a fifth step, the workpiece may undergo sequential reprocessing of steps 2, 3 and 4 until the desired fill profile of the feature on the workpiece is obtained.

In a sixth step, the material is subjected to conventional ECD acidic chemical vapor deposition to achieve the desired thickness. The material is then ready for subsequent processing, which may include additional thermal processing, chemical mechanical polishing, and other processes.

Alternative embodiments of the process may include variations of the steps already described herein, and these steps, combinations and substitutions may additionally be incorporated into the following additional steps. Conformal “seed” deposition may be performed with or without organic additives such as inhibitors, promoters, and / or levelers, for example, from about 4 to about 10, from about 3 to about 10, Or in the pH range of about 2 to about 11 is contemplated herein. Reflow may be performed using a plurality of deposition, cleaning (eg, SRD), and thermal treatment or annealing steps, or may be performed in a single step followed by thermal treatment or annealing at a suitable temperature.

ECD seed “plus” deposition is important for the development of small features, as the thermal treatment or annealing and reflow steps provide substantially void-free seed deposition. As described in more detail below, void formation in the features increases the resistance value (slows the electrical performance of the device) and degrades the reliability of the interconnect.

Other advantages are realized by using the processes described herein. In that regard, a single tool made by Applied Materials Inc., such as Raider ^® electrochemical deposition, cleaning (eg SRD), and thermal treatment or annealing tools, may Steps), a cleaning step (or steps if repeated), a thermal treatment step (or steps if repeated), and a final ECD step. In addition, the results show substantially void-free gap fill for small features using the processes described herein, resulting in lower resistance values and resistive-capacitive (RC) delay values. In addition, the processes described herein provide the ability to fill small features of less than approximately 30 nm, while the fill cannot be achieved using conventional processes. ECD seed “plus” technology is also advantageous in features larger than 30 nm.

As mentioned above, one or more layers of the ECD seed may be applied and then exposed to elevated temperatures to fill deeper or higher aspect ratio features. Referring to FIG. 8, two exemplary ECDs as compared to two conventional ECD seed processes (no annealing step) [wafer 1 and wafer 7] for deposition on damascene features having feature diameters of about 30 nm. A seed plus process (including annealing steps) is provided (wafer 4 and wafer 5). 9-11, the results show an incremental deposition of the ECD seed in the damascene features, and by some or all deposition steps following the annealing step, a single step of the ECD seed (ie, without an annealing step). ) Results in reduced resistance value and resistive-capacitive (RC) delay values.

All of the wafers 1, 4, 5, and 7 included the following initial process conditions: a barrier layer of 10 μs ALD TaN was deposited, followed by a seed layer (secondary seed) of 30 μs CVD Ru, followed by The materials were annealed at 300 ° C. with 10 minutes of nitrogen passivation.

Wafers 1 and 7 were then plated at 2.1 amp-min and 0.5 amp-min, respectively, in a single step of ECD copper seed and then finished with fill and cap using conventional acidic ECD copper deposition processes. The resulting materials produced thick ECD copper seeds (wafer 1) and thin ECD copper seeds (wafer 7).

Wafers 4 and 5 met ECD seed “plus” conditions. Wafer 4 included three ECD copper seed steps each after the first two steps at 0.7 amp-min followed by 300 ° C. annealing and no annealing after the third step, followed by filling using a conventional acidic ECD copper deposition process. And finished with a cap. A microscope image associated with wafer 4 having a feature size of approximately 30 nm is provided in FIG. 12. There is no annealing after the third step, but it should be understood that the last annealing step is also within the scope of the present invention.

Wafer 5 included four ECD copper seed steps with 300 ° C. annealing after the first three steps at 0.5 amp-min and no annealing after the fourth step, followed by filling and using a conventional acidic ECD copper deposition process. Finished with a cap. Similar to wafer 4, it should be understood that the final annealing step is also within the scope of the present invention.

Referring now to FIGS. 9-11, resistance values and RC delay data by comparison for wafers 1, 4, 5, and 7 are provided. As can be seen in FIGS. 9-11, materials formed using ECD seed “plus” according to the methods described herein (wafers 4 and 5) are formed using previously developed techniques. Resistance and resistive / capacitive (RC) delay are significantly reduced compared to the (swafers 1 and 7).

9 and 10, materials formed according to embodiments of the present invention use ECD seeds, but 0 to about 40%, greater than 0 and up to 30%, compared to materials formed without ECD seed plus annealing cycles. A reduction in resistance is achieved in the range of greater than zero and up to 20%, from about 10% to about 20%, and from about 10% to about 15%.

Referring to FIG. 11, materials formed in accordance with embodiments of the present invention achieve an RC delay value reduction compared to materials formed using ECD seeds but without ECD seed plus annealing cycles. Smaller RC delays can result in less or no damage to the low K intermetallic dielectric in the feature.

While illustrative embodiments have been shown and described, it will be understood that various changes may be made therein without departing from the spirit and scope of the invention.

Embodiments of the present invention for which exclusive ownership and privileges are claimed are defined as follows:

Claims (20)

A method for at least partially filling a feature on a workpiece, the method comprising:
(a) obtaining a material comprising the feature;
(b) depositing a first conformal conductive layer in the feature; And
(c) thermally treating the material to reflow the first conformal conductive layer in the feature;
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Thermally processing the material reduces voids in the feature fill,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Further comprising depositing a barrier layer in the feature before the first conformal conductive layer is deposited;
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Further comprising depositing a conductive seed layer on the feature before the first conformal conductive layer is deposited;
A method for at least partially filling a feature on a workpiece. 5. The method of claim 4,
The metal for the seed layer is selected from the group consisting of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, ruthenium, and alloys thereof,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
The metal for the first conformal conductive layer is selected from the group consisting of copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, and alloys thereof,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Wherein the first conformal conductive layer is deposited electrochemically, by chemical vapor deposition, or by atomic layer deposition,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Depositing a second conformal conductive layer after the first conformal conductive layer and thermally treating the material to reflow the second conformal conductive layer;
A method for at least partially filling a feature on a workpiece. The method of claim 8,
Depositing a third conformal conductive layer after the second conformal conductive layer and thermally treating the material to reflow the third conformal conductive layer,
A method for at least partially filling a feature on a workpiece. 5. The method of claim 4,
The seed layer is selected from the group consisting of a seed, a secondary seed, and a stack film of seed and liner,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Wherein the reflowed first conformal conductive layer partially or completely fills the feature,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
The first conformal conductive layer comprises at least one copper complex selected from the group consisting of copper ethylenediamine, citrate, tartrate, and urea deposited using chemistry,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Further comprising depositing a cap layer on the reflowed first conformal conductive layer;
A method for at least partially filling a feature on a workpiece. The method of claim 13,
The cap layer is deposited with an acidic chemical nature,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
The thermal treatment temperature is selected from the group consisting of about 100 ° C. to about 500 ° C., about 200 ° C. to about 400 ° C., and about 250 ° C. to about 350 ° C.,
A method for at least partially filling a feature on a workpiece. The method of claim 1,
Feature diameters are less than 30 nm, less than about 5 to 30 nm, less than about 10 to 30 nm, about 15 to about 20 nm, less than about 20 to 30 nm, less than 20 nm, less than 10 nm, and about 5 to about 10 nm. Selected from the group consisting of:
A method for at least partially filling a feature on a workpiece. The method of claim 1,
The thermally treated material is greater than 0 and up to about 40%, greater than 0 and up to 30%, greater than 0 and up to 20%, from about 10% to about 0, compared to a material formed without thermally treating the material. Having a resistance value decrease selected from the group consisting of 20% and about 10% to about 15%,
A method for at least partially filling a feature on a workpiece. The method of claim 3, wherein
Wherein the first conformal conductive layer is deposited directly on the barrier layer
A method for at least partially filling a feature on a workpiece. A method for at least partially filling a feature on a workpiece,
(a) obtaining a material comprising the feature;
(b) depositing a barrier layer on the feature;
(c) depositing a first conductive layer in the feature after the barrier layer, wherein the first conductive layer is a seed layer;
(d) depositing a second conductive layer in the feature after the first conductive layer, the second conductive layer being a formation following conductive layer; And
(e) annealing the material to reflow the second conductive layer in the feature,
A method for at least partially filling a feature on a workpiece. As the material,
(a) at least one feature having a size of less than 30 nm; And
(b) a substantially void-free conductive layer disposed on the feature,
Material.

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