CN101651117A - Metal copper filling method used in Damascus interconnecting process - Google Patents
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- CN101651117A CN101651117A CN200810118423A CN200810118423A CN101651117A CN 101651117 A CN101651117 A CN 101651117A CN 200810118423 A CN200810118423 A CN 200810118423A CN 200810118423 A CN200810118423 A CN 200810118423A CN 101651117 A CN101651117 A CN 101651117A
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Abstract
The invention discloses a metal copper filling method used in the Damascus interconnecting process and belongs to the field of integrated circuit manufacturing. The method comprises the following steps that: firstly, pores needing to be filled is subjected to a copper electroplating step and a copper re-spluttering step for n times; secondly, the degassing step is carried out after each copper electroplating step and each copper re-spluttering step; and finally, the last copper electroplating step is carried out, and n is equal to Int[(R-2)/2], wherein Int is defined as an integer obtained byrounding up any real number and most close to the real number. In the metal copper filling method, the copper re-spluttering step can remove the metal copper which is piled on the top parts of the pores to be filled after the last copper electroplating step by bombardment, so that the cause forming the pore space is eliminated. In particular to the pores of which the technical node is below 45nm,the actual width of the contact hole is less than 70nm, and the depth-to-width ratio is over 2:1, the none-pore space filling of the pores is ensured.
Description
Technical field
The present invention relates to a kind of Damascus interconnection process, particularly relate to metal copper filling method in the interconnection process of a kind of Damascus.
Background technology
Along with the CMOS transistor size constantly narrows down to sub-micron grade, as the prediction of Moore's Law, the number of transistors in high efficiency, high density integrated circuit rises to several ten million.The integrated needs of the signal of the active element that these quantity are huge are the high desnity metal line more than eight layers nearly, yet resistance that these metal interconnecting wires bring and parasitic capacitance have become the principal element of this high efficient integrated circuit speed of restriction.Based on the promotion of this factor, semi-conductor industry becomes the metallic copper interconnection line from original metallic aluminium interconnection line technological development, low simultaneously dielectric media material substitution silicon dioxide become the dielectric of metal interlevel.Metallic copper has reduced the resistance of metal connecting line interlayer, has strengthened circuit stability simultaneously; Low dielectric media material has then reduced the parasitic capacitance between the metal connecting line layer.
Because the etching to copper is very difficult, so the two embedded technologies of copper-connection employing, dual damascene process (Dual Damascene) claimed again.The typical process flow of existing Damascus technics is: (1) at first deposits the thin silicon nitride (Si3N4) of one deck as diffusion impervious layer and etch stop layer; (2) then deposit certain thickness low dielectric media material in the above; (3) make micro through hole (Via) then by lithography; (4) through hole is carried out partial etching; (5) make groove (Trench) afterwards again by lithography, the preparation flow of through hole, groove and order difference according to the different of technological process and to some extent wherein, but finally all are the results that reached for the 6th step; (6) continue to etch complete through hole and groove; (7) follow sputtering sedimentation (PVD) diffusion impervious layer (TaN/Ta Barrier Layer) and copper seed layer (Seed layer).The effect of diffusion impervious layer is the adhesion that prevention copper diffuses into dielectric material and amplified medium material and copper, the conductive layer when inculating crystal layer is the conduct plating; (8) be the electroplating technology of copper interconnecting line afterwards; (9) be annealing and chemico-mechanical polishing (CMP, Chemical Mechanical Polishing) at last, copper coating is carried out planarization and cleaning.So just formed metal interconnecting wires.Wherein the fill process of copper metal is to be finished jointly by preparation and (8) copper plating filling of above-mentioned (7) copper barrier layer/inculating crystal layer.
In the step of typical process flow (7) the sputtering sedimentation diffusion impervious layer of above-mentioned existing Damascus technics and copper seed layer, concrete technological process is as follows: (i) degas: the mode by heating is removed volatile gaseous impurity residual in preceding road technology and the propagation in atmosphere process, to guarantee the electric property of copper metal layer; (ii) prerinse: by the method for plasma etching remove residual in preceding road technology and the propagation in atmosphere process can not volatile impurity and the oxide of copper, to guarantee the electric property of copper metal layer; (iii) tantalum nitride (TaN) barrier layer physical vapor/sputtering sedimentation; (iv) tantalum (Ta) barrier layer physical vapor/sputtering sedimentation; (v) heavily sputter of tantalum/resedimentation technology, adjusting, the hole filling step of cvd nitride tantalum/tantalum duplicature covers the continuity that distributes and guarantee tantalum metal layer; (vi) copper seed layer deposits, for follow-up copper electroplating technology provides conductive layer.
Physical vapour deposition (PVD) and sputter-deposition technology are class thin film fabrication technology of the most widely using in the semi-conductor industry, and general reference adopts physical method to prepare the thin film preparation process of film; And in the integrated circuit manufacturing, refer in particular to magnetron sputtering technique more, be mainly used in the deposition of metallic films such as aluminium, aluminum bronze, to constitute Metal Contact, metal interconnecting wires etc.Figure 2 shows that the basic schematic diagram of metal sputtering process, consist predominantly of following key step: (1) produces positive argon ion in high vacuum cavity plasma, and quickens to the target with negative potential; (2) argon ion obtains momentum at the accelerator intermediate ion, and the bombardment target; (3) argon ion clashes into metallic atom by physical process from target; (4) clashed into the atomic migration that and arrived silicon chip surface; (5) condensed and the formation film at silicon chip surface by the atom of sputter, film has and the essentially identical component of target material; (6) additional materials is taken away by vacuum pump.
Along with the continuous development and the characteristic size of microelectric technique are constantly dwindled, because the deposition direction of the uncontrollable sputtering particle of conventional sputter technology, sputter enters through hole with high-aspect-ratio and the ability of narrow channel is restricted, can't finish (as shown in Figure 1) to the hole depth-to-width ratio smoothly greater than hole filling in 1: 1 o'clock, its main problem at first is the lack of fill at hole filling bottom corners place; In addition, the top-hung that exists of top corner place is hung (Overhang) phenomenon and has been sealed the hole top and make filling to proceed.
In order to address this problem, plasma physics vapour deposition/plasma sputtering technology is arisen at the historic moment, it makes the metallic atom plasma that sputters by different modes, control the direction of motion and the energy of metal ion again by variety of way, thereby effectively improve step covering power high aspect ratio vias and narrow channel.But because the ionization level of metallic atom can not reach 100%, so the phenomenon of top suspension (Overhang) and bottom corners lack of fill still exists.
Summary of the invention
In order to solve copper filling hole problem in the copper dual damascene process, the invention provides the metal copper filling method in the interconnection process of a kind of Damascus.This method realizes that by improving copper electro-plating method, the heavy sputter step of increase copper in the existing metal filled method copper hole does not have hole and fills.Described technical scheme is as follows:
Metal copper filling method in the interconnection process of a kind of Damascus of the present invention, described method comprises the following steps:
Steps A: the hole that desire is filled carries out n copper plating step and copper weight sputter step successively;
Step B: carry out once final copper and electroplate;
Described n=Int[(R-2)/2]; Wherein R is the desire hole of filling dark/wide ratio; Described Int function is defined as: any real number is rounded up is immediate integer.
Metal copper filling method in the interconnection process of a kind of Damascus of the present invention each time in the copper plating step, is target with 2 times to pore width to the metal filled degree of depth of copper of desiring filling pore in described steps A.
In the metal copper filling method, the final copper of described step B is electroplated the filling of finishing the hole residue degree of depth that desire is filled in the interconnection process of a kind of Damascus of the present invention.
In the metal copper filling method, in described steps A, between the heavy sputter step of each copper plating step and copper, the step of degassing is set in the interconnection process of a kind of Damascus of the present invention.
In the metal copper filling method, the copper metal that the heavy sputter step of the copper of described steps A is specially having deposited bombards in the interconnection process of a kind of Damascus of the present invention, will desire the thicker copper metal-stripping that filling pore top corner place has deposited.
In the metal copper filling method, the heavy sputter step of the copper in the described steps A is finished in the copper seed layer physical vapor deposition chamber in the interconnection process of a kind of Damascus of the present invention; The bias voltage that is applied on the silicon chip in the heavy sputter step of described copper is 350W to 750W.
In the interconnection process of a kind of Damascus of the present invention in the metal copper filling method, the described step of degassing is specially by adding the residual volatilizable gaseous impurity of the preceding road of heat abstraction technology, realize having filled the crystallization again of copper metal simultaneously, adjust crystal structure, obtain low metallic resistance.
In the metal copper filling method, the described step of degassing is finished at the chamber that degass in the interconnection process of a kind of Damascus of the present invention; The heating-up temperature of degassing is 150 to 350 degrees centigrade.
The beneficial effect of technical scheme provided by the invention is:
1, the heavy sputter step of copper that increases of metal copper filling method of the present invention will go up and be deposited in the copper metal of desiring filling pore top corner place after the plating step and peel off, guarantee that metal can successfully be packed into the hole inside that desire is filled in follow-up electroplating process, eliminated the origin cause of formation that hole forms.Particularly, can guarantee that the no hole of hole is filled at the following technology node of 45 nanometers, contact hole developed width＜70 nanometers, hole depth-to-width ratio hole greater than 2: 1.
2, between the heavy sputter step of inferior copper plating step and copper, the step of degassing is set in this method, can heat-treats, when removing impurity, improve the metal electric property plated metal.
3, this method can utilize existing manufacturing equipment to finish, and need not the equipment that increases, more renews or raises the cost, and avoids manufacturer to improve and additionally pay the fund updating apparatus for obtaining processability.
Description of drawings
Fig. 1 is the flow chart of the metal copper filling method in the interconnection process of the described Damascus of the embodiment of the invention;
Fig. 2 is that the schematic diagram that phenomenon is hung in top-hung appears in the hole top corner place that the metal filled technology of existing copper causes;
Fig. 3 is the sputter principle schematic;
Fig. 4 is heavy sputter schematic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
The typical process flow of existing Damascus technics:
(1) at first deposits the thin silicon nitride (Si3N4) of one deck as diffusion impervious layer and etch stop layer;
(2) then deposit certain thickness low dielectric media material in the above;
(3) make micro through hole (Via) then by lithography;
(4) through hole is carried out partial etching;
(5) make groove (Trench) afterwards again by lithography, the preparation flow of through hole, groove and order difference according to the different of technological process and to some extent wherein, but finally all are the results that reached for the 6th step;
(6) continue to etch complete through hole and groove;
(7) follow sputtering sedimentation (PVD) diffusion impervious layer (TaN/Ta Barrier Layer) and copper seed layer (Seedlayer).The effect of diffusion impervious layer is the adhesion that prevention copper diffuses into dielectric material and amplified medium material and copper, the conductive layer when inculating crystal layer is the conduct plating;
(8) be the electroplating technology of copper interconnecting line afterwards, i.e. it is metal filled that copper is carried out in utilization plating;
(9) be annealing and chemico-mechanical polishing (CMP, Chemical Mechanical Polishing) at last, copper coating is carried out planarization and cleaning.
It is metal filled only to carry out a copper in the above-mentioned existing copper dual damascene interconnection process, can finish preferably hole dark/hole under wide (A/R) smaller situation fills.But when hole dark/wide than (A/R) greater than 2 the time, carry out the metal filled copper hole that will occur of copper by existing method and produce hole near top area, can't reach the metal filled requirement of copper.
Metal copper filling method in the interconnection process of Damascus of the present invention at the following technology node of 45 nanometers, contact hole developed width＜70 nanometers, hole dark/wide situation than (A/R)＞2: 1, by increasing the heavy sputter step of copper, guarantee the no hole filling effect of copper metal.
In the interconnection process of Damascus, finish above-mentioned flow process after (7) step according to existing process method, beginning is carried out metal filled according to method of the present invention.
The width of desiring filling contact hole in the present embodiment is 56 nanometers, hole is dark/wide be 4: 1 than (A/R).
At first, according to hole dark/wide than calculating the heavily coefficient n that heavily electroplates of sputter and copper of copper.
The copper heavily computational methods of the coefficient n that heavily electroplates of sputter and copper is: n=Int[(R-2)/2].Wherein R is hole dark/wide ratio; The Int function is defined as: any real number is upwards collected evidence is immediate integer.The present embodiment mesopore is dark/wide be 4 than R, according to n=Int[(R-2)/2] can determine copper heavily the coefficient n that electroplates of sputter and copper be 1.That is to say, in the present embodiment steps A, will carry out a copper and electroplate and a heavily sputter of copper.If calculate n, then carry out successively (the heavily sputter of copper plating → copper) → (the heavily sputter of copper plating → copper) greater than 1 ... until finishing n time.
After determining that coefficient n is 1, next to carry out a copper plating step (step 100), by to electroplating the control of condition, finish about 2 times of metal filled degree of depth of the copper to pore width to desiring filling pore, promptly finish the plating degree of depth of about 112 nanometers in the present embodiment by the copper plating first time.In the production process of reality, because concrete filling process can be subjected to factor affecting such as quality of materials, operational environment, equipment running status, so it is filled, and the result can there is some difference.
Through a copper plating step, the copper metal can be distributed in the machine hole outside, inside of hole, and the too much phenomenon of copper metal accumulation that can exist at hole top corner place this moment is filled if continue, the copper metal may block the filling pore upper opening, hole will occur in the hole like this.
For solving the problem of electroplating, should carry out the heavy sputter step of copper, but, after the copper plating step, the step (step 110) of degassing can be set in order to guarantee the copper heavily quality and the effect of sputter at filling pore top corner metal accumulation.Degas is by adding the residual volatilizable gaseous impurity of the preceding road of heat abstraction technology, realize having filled the crystallization again of copper metal simultaneously, adjust crystal structure, obtaining low metallic resistance.The technology of degassing is carried out in the chamber of degassing, the technology of degassing heating-up temperature is 250 degrees centigrade, it is the inflation/operation of bleeding (argon flow amount is 35sccm) of one-period that the feeding argon gas carries out with 10 seconds, with the volatilizable gaseous impurity of quick removal silicon chip surface and strengthen heat conduction under the vacuum condition, the process time is 40s.
Through degassing after the step next step, carry out a heavily sputter (step 120) of copper.
Heavy sputtering technology be by in sputter procedure or sputter finish after by metal ion or argon ion energy and the direction of motion are controlled, the film that has deposited is bombarded, the thicker copper metal film that filling pore top corner place has been deposited bombards again to be peeled off, adjust and deposited hole filled with film step covering state, alleviate the problem that the top hangs thereby play.Heavy sputtering technology is accompanied by the resedimentation of film usually to guarantee the continuity of deposit film.
Copper heavily sputter by the copper metal of electroplating deposition is bombarded heavily sputter, the top of having alleviated aggravation after preceding road copper is electroplated hangs phenomenon, make because electroplating activity is soon reopened by the aperture of metal shutoff and enlarges, the continuation that helps next step copper metal is filled.Copper heavily sputters in the copper seed layer physical vapor deposition chamber and carries out; The DC power supply power of the heavy sputtering technology of copper is 36kW; The initial ignition argon flow amount is 130sccm, and the argon flow amount during process for stabilizing is 20sccm; The copper heavily used technology silicon chip bias voltage of sputter is 350W to 750W, and present embodiment is selected pressurization 600W.
Through the heavy sputter step of above-mentioned copper, can effectively remove the too much phenomenon of hole top corner place copper metal accumulation, copper electroplated metal layer is evenly distributed.
At last, carry out final copper and electroplate (step 130), filling on the hole basis of certain depth, finish remaining copper metal hole and fill.Like this, the hole of desire filling is just metal filled full by copper.
After utilizing metal copper filling method of the present invention, still needing to use existing method is annealing and chemico-mechanical polishing at last, and copper coating is carried out planarization and cleaning.
So far, whole technological processes of copper dual damascene interconnection process have just been finished.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, metal copper filling method in the interconnection process of a kind of Damascus is characterized in that described method comprises the following steps:
Steps A: the hole that desire is filled carries out n copper plating step and copper weight sputter step successively;
Step B: carry out once final copper and electroplate;
Described n=Int[(R-2)/2]; Wherein R is the desire hole of filling dark/wide ratio; Described Int function is defined as: any real number is rounded up is immediate integer.
2, metal copper filling method in the interconnection process of a kind of Damascus according to claim 1 is characterized in that, each time in the copper plating step, is target with 2 times to pore width to the metal filled degree of depth of copper of desiring filling pore in described steps A.
3, metal copper filling method in the interconnection process of a kind of Damascus according to claim 1 is characterized in that, the final copper of described step B is electroplated the filling of finishing the hole residue degree of depth that desire is filled.
4, metal copper filling method in the interconnection process of a kind of Damascus according to claim 1 is characterized in that, between the heavy sputter step of each copper plating step and copper, the step of degassing is set in described steps A.
5, metal copper filling method in the interconnection process of a kind of Damascus according to claim 1, it is characterized in that, the copper metal that the heavy sputter step of the copper of described steps A is specially having deposited bombards, and will desire the thicker copper metal-stripping that filling pore top corner place has deposited.
6, metal copper filling method in the interconnection process of a kind of Damascus according to claim 1 is characterized in that, the heavy sputter step of the copper in the described steps A is finished in the copper seed layer physical vapor deposition chamber; The bias voltage that is applied on the silicon chip in the heavy sputter step of described copper is 350W to 750W.
7, metal copper filling method in the interconnection process of a kind of Damascus according to claim 4, it is characterized in that, the described step of degassing is specially by adding the residual volatilizable gaseous impurity of the preceding road of heat abstraction technology, realize having filled the crystallization again of copper metal simultaneously, adjust crystal structure, obtain low metallic resistance.
8, metal copper filling method in the interconnection process of a kind of Damascus according to claim 7 is characterized in that the described step of degassing is finished at the chamber that degass; The heating-up temperature of degassing is 150 to 350 degrees centigrade.
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| CN102290370A (en) * | 2010-06-21 | 2011-12-21 | 无锡华润上华半导体有限公司 | Manufacturing method of conductive plug |
| CN103426815A (en) * | 2012-04-26 | 2013-12-04 | 应用材料公司 | Semiconductor reflow processing for feature fill |
| CN103426816A (en) * | 2012-04-26 | 2013-12-04 | 应用材料公司 | Semiconductor reflow processing for high aspect ratio fill |
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| CN101211818B (en) * | 2006-12-26 | 2010-04-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated circuit interlinkage structure interstitial copper-plating method and structure |
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| CN102290370A (en) * | 2010-06-21 | 2011-12-21 | 无锡华润上华半导体有限公司 | Manufacturing method of conductive plug |
| CN103426815A (en) * | 2012-04-26 | 2013-12-04 | 应用材料公司 | Semiconductor reflow processing for feature fill |
| CN103426816A (en) * | 2012-04-26 | 2013-12-04 | 应用材料公司 | Semiconductor reflow processing for high aspect ratio fill |
| US10665503B2 (en) | 2012-04-26 | 2020-05-26 | Applied Materials, Inc. | Semiconductor reflow processing for feature fill |
| CN103854990A (en) * | 2012-11-30 | 2014-06-11 | 格罗方德半导体公司 | Methods for fabricating integrated circuits having low resistance metal gate structures |
| CN103854990B (en) * | 2012-11-30 | 2017-01-18 | 格罗方德半导体公司 | Methods for fabricating integrated circuits having low resistance metal gate structures |
| CN104269405B (en) * | 2014-09-16 | 2017-08-11 | 华中科技大学 | A kind of three-dimensional semiconductor memory device filled based on deep hole and preparation method thereof |
| CN109087886A (en) * | 2018-11-05 | 2018-12-25 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN109087886B (en) * | 2018-11-05 | 2019-10-25 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN114216869A (en) * | 2021-10-19 | 2022-03-22 | 华灿光电（浙江）有限公司 | Wafer doping detection system and detection method |
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Address after: No. 8, Wenchang Avenue, Beijing economic and Technological Development Zone, 100176 Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016 M5 building, No. 1 Jiuxianqiao East Road, Chaoyang District, Beijing Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |