CN103426814B - Metal filling method - Google Patents
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- CN103426814B CN103426814B CN201210165002.7A CN201210165002A CN103426814B CN 103426814 B CN103426814 B CN 103426814B CN 201210165002 A CN201210165002 A CN 201210165002A CN 103426814 B CN103426814 B CN 103426814B
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Abstract
The invention provides a metal filling method. The metal filling method comprises the steps that a substrate is provided; an interlayer dielectric layer and a first groove which is located in the interlayer dielectric layer are formed on the substrate; a barrier layer and a seed crystal layer covering the barrier layer are sequentially deposited on the bottom and the side wall of the first groove, so as to form a second groove; and a metal material is deposited in the second groove through an ionic liquid electric deposition technology until the second groove is filled, so as to form a metal layer. According to the metal filling method provided by the invention, the metal material is filled in the trench through the ionic liquid electric deposition technology to form the metal layer; the formed metal layer has good compactness and can effectively prevent the diffusion of metal atoms in the metal layer; the performance of a semiconductor device which comprises the formed metal layer is improved; and the technology cost is reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of method of filling metal.
Background technology
Along with the development of semiconductor technology, integrated circuit develops into millions of devices from the minority interconnect devices manufactured on a single chip.The performance that current integrated circuit provides and complexity are considerably beyond the imagination originally.In order to improve complexity and the current densities (that is, can be installed to the quantity of the device on given chip area) of integrated circuit, in integrated circuit, the live width of minimum device becomes more and more less.
The current densities of continuous increase not only increases complexity and the performance of integrated circuit, and, also for client provides the parts of more low cost.Integrated circuit or chip manufacturing apparatus usually may spend hundreds and thousands of ten thousand, even tens dollars.Every suit manufacturing equipment has certain wafer throughput, and every wafer will have the integrated circuit of some.Therefore, by manufacturing more and more less individual integrated circuit (IC)-components, more device can be manufactured on each wafer, the output of manufacturing equipment can be increased like this.Make device less always very challenging property, because each technique for IC manufacturing all exists restriction.That is, a kind of given technique can only be worked into a certain specific feature sizes usually, so, need to make further change to technique or device layout.
Such as, along with constantly reducing of device feature size in integrated circuit (IC) chip, the current density in metal connecting line constantly increases, and the response time constantly shortens, and traditional aluminum metal interconnection line reaches technological limits.After process is less than 130nm, traditional aluminum interconnecting technology gradually replace by copper interconnecting line technology.With aluminum metallic matrix ratio, make with process for copper the RC that metal interconnecting wires can reduce interconnection line and postpone, improve the integrity problem that electromigration etc. causes.But, the characteristic of the very fast and etching difficulty of the diffusion velocity due to copper, existing technique forms copper interconnecting line by physical vapor deposition technique, but the copper interconnecting line compactness formed by above-mentioned technique is poor, copper ion easily moves, and causes the electric property of formed copper interconnecting line poor.
In addition, along with the reduction of device feature size in integrated circuit, needing the technique to forming device to do further adjustment, causing the raising of device manufacturing cost.To manufacture the MOS device in semiconductor device, in the process forming metal gates in MOS device, need first by chemical vapor deposition method or grid material deposited by physical vapour deposition (PVD), then by etching technics, described grid material is etched, form metal gates.Due to the reduction of MOS device characteristic size, the characteristic size also corresponding reduction of grid, cause the technique forming metal gates more complicated, cost is higher.
Therefore, provide a kind of method of filling metal, with improve comprise is formationed metal interconnecting wires or metal gates semiconductor device performance while reduction process costs, become one of current problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of method of filling metal, improves the performance comprising metal interconnecting wires or metal gate semiconductor device, reduces process costs.
For solving the problem, the invention provides a kind of method of filling metal, comprising: substrate is provided, described substrate is formed with interlayer dielectric layer and is positioned at the first groove of described interlayer dielectric layer; At the bottom of described first groove and sidewall deposited barrier layer and the inculating crystal layer covering described barrier layer successively, form the second groove; By ionic liquid electrodeposition technique deposit metallic material in described second groove, to filling up the second groove, form metal level.
Optionally, described ionic liquid electrodeposition technique intermediate ion liquid electric deposit fluid comprises organic cation, organic anion and inorganic ions.
Optionally, the material of described inculating crystal layer is copper.
Optionally, the technique that copper seed layer is formed metal level comprises: by acetic acid 1-ethyl-3-methylimidazole, Schweinfurt green and the copper chloride mixed in molar ratio by 77 ~ 93:5 ~ 15:2 ~ 8, be mixed with the first ionic liquid electrodeposition liquid; The substrate including the second groove is immersed in the first ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer of the second groove, form metal level.
Optionally, current density when carrying out electro-deposition is at 0.1 ~ 10A/cm
2in scope.
Optionally, in described first ionic liquid electrodeposition liquid, acetate ion compares within the scope of 0.5 ~ 2:1 with the ion number of 1-ethyl-3-methylimidazole ion.
Optionally, the temperature of described first ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
Optionally, the material of described inculating crystal layer is aluminium.
Optionally, the technique that aluminium inculating crystal layer is formed metal level comprises: by bromination N-butyl-pyridinium, alkyl aluminum by the mixed in molar ratio of 85 ~ 95:5 ~ 15, be mixed with the second ionic liquid electrodeposition liquid; The substrate including the second groove is immersed in the second ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer of the second groove, form metal level.
Optionally, current density when carrying out electro-deposition is at 0.1 ~ 10A/cm
2in scope.
Optionally, in described second ionic liquid electrodeposition liquid, bromide ion compares within the scope of 0.5 ~ 2:1 with the ion number of N-butyl-pyridinium ion.
Optionally, the temperature of described second ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
Optionally, the technique that aluminium inculating crystal layer is formed metal level comprises: by chlorination 1-ethyl-3-methylimidazole, alkyl aluminum by the mixed in molar ratio of 85 ~ 95:5 ~ 15, be mixed with the 3rd ionic liquid electrodeposition liquid; The substrate including the second groove is immersed in the 3rd ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer of the second groove, form metal level.
Optionally, current density when carrying out electro-deposition is at 0.1 ~ 10A/cm
2in scope.
Optionally, in described 3rd ionic liquid electrodeposition liquid, chloride ion compares within the scope of 0.5 ~ 2:1 with the ion number of 1-ethyl-3-methylimidazole ion.
Optionally, the temperature of described 3rd ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
Optionally, the material on described barrier layer is tantalum nitride.
Compared with prior art, technical solution of the present invention has the following advantages:
Metal material is filled in the trench by ionic liquid electrodeposition technique, ionic liquid electrodeposition technique to form the compactness of metal level higher, and then avoid metallic atom diffusion in metal level, improve the performance of semiconductor device comprising formed metal level, reduce process costs.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet that first embodiment of the invention fills the method for metal;
Fig. 2 ~ Fig. 4 be first embodiment of the invention fill the method for metal form the generalized section in semiconductor device each stage;
Fig. 5 is the schematic flow sheet that second embodiment of the invention fills the method for metal;
Fig. 6 ~ Fig. 9 be second embodiment of the invention fill the method for metal form the generalized section in semiconductor device each stage.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, the compactness that prior art forms metal level is poor, and in metal level, metallic atom easily moves, and causes the electric property of the semiconductor device comprising described metal level poor.In addition, along with in integrated circuit, the characteristic size of device constantly reduces, and the technique forming metal level in device is more complicated, and accordingly, process costs is also higher.
For the problems referred to above, inventor provide a kind of method of filling metal, comprising: substrate is provided, described substrate is formed with interlayer dielectric layer and is positioned at the first groove of described interlayer dielectric layer; At the bottom of described first groove and sidewall deposited barrier layer and the inculating crystal layer covering described barrier layer successively, form the second groove; By ionic liquid electrodeposition technique deposit metallic material in described second groove, to filling up the second groove, form metal level.The method that the present invention fills metal fills metal material in the trench by ionic liquid electrodeposition technique, form metal level, to form the compactness of metal level good, effectively can avoid metallic atom diffusion in metal level, improve the performance of the semiconductor device comprising formed metal level, reduce process costs.
In existing semiconductor technology, metal level be mainly used in MOS device grid and for realizing the metal plug be electrically connected between device, below by the grid and metal plug two specific embodiments of realizing being electrically connected between device forming MOS device, the method that the present invention fills metal is described.
First embodiment
The present embodiment is described the method that the present invention fills metal for the metal plug realizing being electrically connected between device to be formed.With reference to figure 1, fill the schematic flow sheet of the method for metal for first embodiment of the invention, comprising:
Step S21, provides substrate, described substrate is formed with interlayer dielectric layer and is positioned at the first groove of described interlayer dielectric layer;
Step S22, at the bottom of described first groove and sidewall deposited barrier layer and the inculating crystal layer covering described barrier layer successively, forms the second groove;
Step S23, by acetic acid 1-ethyl-3-methylimidazole, Schweinfurt green and the copper chloride mixed in molar ratio by 77 ~ 93:5 ~ 15:2 ~ 8, is mixed with the first ionic liquid electrodeposition liquid;
Step S24, is immersed in the first ionic liquid electrodeposition liquid, carries out electro-deposition by the substrate including the second groove, on the inculating crystal layer of the second groove, form metal level.
With reference to figure 2 ~ Fig. 4, for first embodiment of the invention fill the method for metal form the generalized section in semiconductor device each stage.Be described in conjunction with the method be arranged in reference to figure 1 ~ Fig. 4 embodiment one fills metal.
First, in conjunction with reference to figure 1 and Fig. 2, perform step S21, substrate 200 is provided, described substrate 200 is formed with interlayer dielectric layer 202 and is positioned at the first groove 203 of described interlayer dielectric layer 202.
Concrete, the material of described Semiconductor substrate 200 is can be silicon, germanium silicon or silicon-on-insulator.In practice, described Semiconductor substrate 200 also has device layer (not shown).The such as semiconductor device such as transistor, diode is formed in described device layer.
Because extended meeting after interlayer dielectric layer 202 exists the effect of isolated copper, and copper is deep-level impurity, very high diffusion constant is had in silicon and oxide, donor level or acceptor level can be formed with alms giver or acceptor impurity in forbidden band, therefore, produce leakage current to prevent copper ion from spreading, the preferred dielectric constant (k) of material of described interlayer dielectric layer 202 is less than the advanced low-k materials of silicon dioxide (k=3.9).In concrete enforcement, the material of interlayer dielectric layer 202 can be Silicon Containing Hydrogen Barbiturates (HydrogenSilsesquioxane, HSQ, k=2.8 ~ 3.0), containing Si-CH
3functional group contains methane-siliconic acid salt (Methylsilsesquioxane, MSQ, k=2.5 ~ 2.7), comprehensive Silicon Containing Hydrogen Barbiturates HSQ and hybrid organic siloxane polymer (the Hybrid Organic SiloxanePolymer contained synthesized by methane-siliconic acid salt MSQ, HOSP) film (k=2.5), porous SiOCH film (k=2.3 ~ 2.7), even can adopt the organic macromolecular compounds such as the porousness silicate of ultralow dielectric (k<2.0) (Porous Silicate) and dielectric constant (k) be 1.9 porous SiOCH film.
Then, in conjunction with reference to figure 1 and Fig. 3, perform step S22, at the bottom of described first groove 203 and sidewall deposited barrier layer 209 and the inculating crystal layer 204 covering described barrier layer 209 successively, form the second groove 205.
Concrete, the material on described barrier layer 209 can be tantalum nitride, for improving the adhesiveness between the metal material of follow-up formation and interlayer dielectric layer 202, improve the formation quality of the first groove 203, and stop the metal material of follow-up formation to diffuse into interlayer dielectric layer 202, improve the electric property comprising the semiconductor device of metal material.The formation process on described barrier layer 209 can be physical vapour deposition (PVD), and its concrete formation process, as the known technology of those skilled in the art, does not repeat at this.
The material of described inculating crystal layer 204 can be copper, in order to improve the adhesiveness between follow-up formation metal material and barrier layer 209, described inculating crystal layer 204 is also as the negative electrode in subsequent ion liquid electric depositing operation simultaneously, to form copper metal layer in described second groove 205.The formation process of described inculating crystal layer 204 can be physical vapour deposition (PVD), and its concrete formation process, as the known technology of those skilled in the art, does not repeat at this.
Again then, with reference to figure 1, perform step S23, by acetic acid 1-ethyl-3-methylimidazole [(EMI) (CH
3cOO)], Schweinfurt green [Cu (CH
3cOO)
2] and copper chloride (CuCl
2) by the mixed in molar ratio of 77 ~ 93:5 ~ 15:2 ~ 8, be mixed with the first ionic liquid electrodeposition liquid.
Concrete, acetate ion (CH in described first ionic liquid electrodeposition liquid
3cOO
-) and 1-ethyl-3-methylimidazole ion (EMI
+) ion number than within the scope of 0.5 ~ 2:1.The temperature of described first ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.Described CuCl
2in order to when being formed for realizing the metal plug be electrically connected between device subsequently through the first ionic liquid electrodeposition liquid, improving the migration rate of electronics in the first ionic liquid electrodeposition liquid, improving the efficiency of ionic liquid electrodeposition further.
Finally, in conjunction with reference to figure 1 and Fig. 4, perform step S24, the substrate 200 including the second groove 205 is immersed in the first ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer 204 of the second groove 205, form metal level 206.
Concrete, using inculating crystal layer 204 as negative electrode, copper metal, as anode, carries out electro-deposition, deposit metallic material in the second groove 205.When carrying out electro-deposition, current density is at 0.1 ~ 10A/cm
2in scope.
In a particular embodiment, after step S24, also comprise: the substrate 200 including metal level 206 is taken out from the first ionic liquid electrodeposition liquid, and it is cleaned.It, as the known technology of those skilled in the art, does not repeat at this.
So far, the formation process for realizing the metal plug be electrically connected between device is completed.
In the present embodiment, the copper metal plug compactness formed by the method for ionic liquid electrodeposition process filling metal is good, effectively can prevent copper atom in copper metal plug from migrating to interlayer dielectric layer 202 adjacent with it and move along interlayer dielectric layer 202 surface at copper metal plug surface copper atom, improve the electric property of the semiconductor device comprising formed copper metal plug.
Second embodiment
The present embodiment is described the method that the present invention fills metal with the grid forming MOS device.With reference to figure 5, for second embodiment of the invention fills the method flow schematic diagram of metal, comprising:
Step S31, provides substrate, described substrate is formed with interlayer dielectric layer and is positioned at the first groove of described interlayer dielectric layer;
Step S32, at the bottom of described first groove and sidewall deposited barrier layer and the inculating crystal layer covering described barrier layer successively, forms the second groove;
Step S33, by bromination N-butyl-pyridinium, alkyl aluminum by the mixed in molar ratio of 85 ~ 95:5 ~ 15, is mixed with the second ionic liquid electrodeposition liquid;
Step S34, is immersed in the second ionic liquid electrodeposition liquid, carries out electro-deposition by the substrate including the second groove, on the inculating crystal layer of the second groove, form metal level.
With reference to figure 6 ~ Fig. 9, for second embodiment of the invention fill the method for metal form the generalized section in semiconductor device each stage.Be described in conjunction with the method be arranged in reference to figure 5 ~ Fig. 9 embodiment two fills metal.
First, in conjunction with reference to figure 5 and Fig. 7, perform step S31, substrate 300 is provided, described substrate 300 is formed with interlayer dielectric layer and is positioned at the first groove 307 of described interlayer dielectric layer.
The material of described substrate 300 can be silicon, germanium silicon, silicon-on-insulator etc.Described interlayer dielectric layer comprise the gate dielectric layer 302 of substrate 300 described in cover part and substrate 300 be symmetricly set in described gate dielectric layer 302 both sides and in the vertical direction higher than the side wall 308 on described gate dielectric layer 302 surface, described gate dielectric layer 302 and side wall 308 form described first groove 307 jointly.
With reference to figure 6 ~ Fig. 7, described first groove 307 is formed by following steps: first, and described substrate 300 is formed gate dielectric layer 302 and pseudo-grid 305 successively, and described gate dielectric layer 302 forms pseudo-grid structure jointly with pseudo-grid 305; Then, with pseudo-grid structure for mask, the substrate 300 of pseudo-grid structure both sides is symmetrically formed side wall 308; Finally, remove described pseudo-grid 305, form the first groove 307.
Concrete, the material of described gate dielectric layer 302 can be silica, silicon oxynitride etc.The manufacture method of described gate dielectric layer 302 and side wall 308 is same as the prior art, and as the known technology of those skilled in the art, therefore not to repeat here.
Then, in conjunction with reference to figure 5 and Fig. 8, perform step S32, at the bottom of described first groove 307 and sidewall deposited barrier layer 309 and the inculating crystal layer 304 covering described barrier layer 309 successively, form the second groove 310.
Concrete, the material on described barrier layer 309 can be tantalum nitride, for improving the adhesiveness between the metal material of follow-up formation and sidewall 308, improves the formation quality of the first groove 307, improves the electric property comprising the semiconductor device of MOS device.The formation process on described barrier layer 309 can be physical vapour deposition (PVD), and its concrete formation process, as the known technology of those skilled in the art, does not repeat at this.
The material of described inculating crystal layer 304 can be aluminium, in order to improve the adhesiveness between follow-up formation metal material and barrier layer 309.Meanwhile, described inculating crystal layer 304 also as the negative electrode in subsequent ion liquid electric depositing operation, with in described second groove 310 formed aluminum metal layer.The formation process of described inculating crystal layer 304 can be physical vapour deposition (PVD), and its concrete formation process, as the known technology of those skilled in the art, does not repeat at this.
Again then, with reference to figure 5, perform step S33, by bromination N-butyl-pyridinium, alkyl aluminum [Al (C
2h
6)] by the mixed in molar ratio of 85 ~ 95:5 ~ 15, be mixed with the second ionic liquid electrodeposition liquid.
Concrete, in described second ionic liquid electrodeposition liquid, bromide ion and the ion number of N-butyl-pyridinium ion are than within the scope of 0.5 ~ 2:1.The temperature of described second ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
Finally, in conjunction with reference to figure 5 and Fig. 9, perform step S34, the substrate 300 including the second groove 310 is immersed in the second ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer 304 of the second groove 310, form metal level 306.
Concrete, using inculating crystal layer 304 as negative electrode, aluminum metal, as anode, carries out ionic liquid electrodeposition in the second groove 310.During electro-deposition, current density can at 0.1 ~ 10A/cm
2in scope.
Concrete, after execution step S34, also comprise: the substrate 300 including metal level 306 is taken out from the second ionic liquid electrodeposition liquid, and it is cleaned.It, as the known technology of those skilled in the art, does not repeat at this.
In the present embodiment, also available chlorination 1-ethyl-3-methylimidazole, alkyl aluminum substitute by the 3rd ionic liquid electrodeposition liquid of the mixed in molar ratio of 85 ~ 95:5 ~ 15 described second ionic liquid electrodeposition liquid.In a particular embodiment, chloride ion (Cl in described 3rd ionic liquid electrodeposition liquid
-) and 1-ethyl-3-methylimidazole ion (EMI
+) ion number than within the scope of 0.5 ~ 2:1.The temperature of described 3rd ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
So far, the formation process of metal gates in MOS device is completed.
In the present embodiment, formed the method for metal gates in MOS device by ionic liquid electrodeposition technique, effectively save the process costs forming metal gates.
In above-described embodiment, in groove, metal material is filled by ionic liquid electrodeposition technique, form metal level, to form the compactness of metal level good, metallic atom in metal level can be effectively avoided to move, improve the electric property comprising the semiconductor device of described metal level, reduce process costs.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (11)
1. fill a method for metal, it is characterized in that, comprising:
Substrate is provided, described substrate is formed with interlayer dielectric layer and is positioned at the first groove of described interlayer dielectric layer;
At the bottom of described first groove and sidewall deposited barrier layer and the inculating crystal layer covering described barrier layer successively, form the second groove, the material of described inculating crystal layer is copper or aluminium;
By ionic liquid electrodeposition technique deposit metallic material in described second groove, to filling up the second groove, form metal level;
Wherein, when the material of described inculating crystal layer is copper, the technique that copper seed layer is formed metal level comprises: by acetic acid 1-ethyl-3-methylimidazole, Schweinfurt green and the copper chloride mixed in molar ratio by 77 ~ 93:5 ~ 15:2 ~ 8, be mixed with the first ionic liquid electrodeposition liquid; The substrate including the second groove is immersed in the first ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer of the second groove, form metal level;
When the material of described inculating crystal layer is aluminium, the technique that aluminium inculating crystal layer is formed metal level comprises: by bromination N-butyl-pyridinium, alkyl aluminum by the mixed in molar ratio of 85 ~ 95:5 ~ 15, be mixed with the second ionic liquid electrodeposition liquid; The substrate including the second groove is immersed in the second ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer of the second groove, form metal level; Or the technique forming metal level on aluminium inculating crystal layer comprises: by chlorination 1-ethyl-3-methylimidazole, alkyl aluminum by the mixed in molar ratio of 85 ~ 95:5 ~ 15, be mixed with the 3rd ionic liquid electrodeposition liquid; The substrate including the second groove is immersed in the 3rd ionic liquid electrodeposition liquid, carries out electro-deposition, on the inculating crystal layer of the second groove, form metal level.
2. method of filling metal as claimed in claim 1, it is characterized in that, described ionic liquid electrodeposition technique intermediate ion liquid electric deposit fluid comprises organic cation, organic anion and inorganic ions.
3. as claimed in claim 1 method of filling metal, is characterized in that, when the material of described inculating crystal layer is copper, current density when carrying out electro-deposition is at 0.1 ~ 10A/cm
2in scope.
4. method of filling metal as claimed in claim 1, is characterized in that, in described first ionic liquid electrodeposition liquid, acetate ion and the ion number of 1-ethyl-3-methylimidazole ion are than within the scope of 0.5 ~ 2:1.
5. method of filling metal as claimed in claim 1, it is characterized in that, the temperature of described first ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
6. as claimed in claim 1 method of filling metal, is characterized in that, when the material of described inculating crystal layer is aluminium, current density when carrying out electro-deposition is at 0.1 ~ 10A/cm
2in scope.
7. method of filling metal as claimed in claim 1, is characterized in that, in described second ionic liquid electrodeposition liquid, bromide ion and the ion number of N-butyl-pyridinium ion are than within the scope of 0.5 ~ 2:1.
8. method of filling metal as claimed in claim 1, it is characterized in that, the temperature of described second ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
9. method of filling metal as claimed in claim 1, is characterized in that, in described 3rd ionic liquid electrodeposition liquid, chloride ion and the ion number of 1-ethyl-3-methylimidazole ion are than within the scope of 0.5 ~ 2:1.
10. method of filling metal as claimed in claim 1, it is characterized in that, the temperature of described 3rd ionic liquid electrodeposition liquid is within the scope of 0 ~ 100 DEG C.
The method of the 11. filling metals stated as claim 1, is characterized in that, the material on described barrier layer is tantalum nitride.
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| US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
| US6093647A (en) * | 1998-11-03 | 2000-07-25 | Advanced Micro Devices, Inc. | Method to selectively electroplate conductive material into trenches |
| EP1143506A2 (en) * | 2000-04-04 | 2001-10-10 | Nippon Telegraph and Telephone Corporation | Pattern forming method |
| CN101263247A (en) * | 2005-09-20 | 2008-09-10 | 埃其玛公司 | Electroplating composition for coating a substrate surface with a metal |
| CN101512048A (en) * | 2006-02-21 | 2009-08-19 | 埃其玛公司 | Method and compositions for direct copper plating and filling to form interconnects in the fabrication of semiconductor devices |
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2012
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| US6093647A (en) * | 1998-11-03 | 2000-07-25 | Advanced Micro Devices, Inc. | Method to selectively electroplate conductive material into trenches |
| US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
| EP1143506A2 (en) * | 2000-04-04 | 2001-10-10 | Nippon Telegraph and Telephone Corporation | Pattern forming method |
| CN101263247A (en) * | 2005-09-20 | 2008-09-10 | 埃其玛公司 | Electroplating composition for coating a substrate surface with a metal |
| CN101512048A (en) * | 2006-02-21 | 2009-08-19 | 埃其玛公司 | Method and compositions for direct copper plating and filling to form interconnects in the fabrication of semiconductor devices |
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