CN103425615B - Three-channel data sends adapter - Google Patents
Three-channel data sends adapter Download PDFInfo
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- CN103425615B CN103425615B CN201310326473.6A CN201310326473A CN103425615B CN 103425615 B CN103425615 B CN 103425615B CN 201310326473 A CN201310326473 A CN 201310326473A CN 103425615 B CN103425615 B CN 103425615B
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Abstract
The present invention relates to a kind of Three-channel data and send adapter, including: data processing module A and switching output module B.Wherein, data processing module A includes CPCI computer interface (1), CPCI I/O accelerator (2), data transmission control module (3), the first buffer (4), the second buffer (5), the 3rd buffer (6), interface conversion output module (7), power module (8), crystal oscillator (9) and parameter configuration module (10).This Three-channel data sends adapter and utilizes the buffer of the 16 bit wides parallel data buffer memory to 32, can transmit the data that three tunnels are different, transmission code rate-compatible.
Description
Technical field
The present invention relates to a kind of Three-channel data and send adapter, suitable in system compatible, system rejection to disturbance, ambient temperature etc. are had the system such as the unmanned vehicle observing and controlling of particular/special requirement, vacant lot view data transmission, carry out data interaction with CPCI computer, belong to communication observing and controlling, field of information transmission.
Background technology
At present, domestic for CPCI (CompactPeripheralComponentInterconnect, compact PCI) the mutual data of computer send adapter and often use single-channel data to send adapter, the data that CPCI computer is sent here can be changed into synchronous data flow output by it, have the function of speed switching simultaneously.But a CPCI computer slot can only send a circuit-switched data, and the requirement due to PCB routing, the bit wide selecting data buffer is also restricted, such as, for 32 bit wide data, the 32 bit wide Deta bearers that CPCI computer is sent by the data buffer of two 16 bit wides jointly can be used, if but need transmitting two paths or the parallel data on three tunnels, current existing single-channel data sends adapter not only will not meet the needs of system, also computer operating system can be brought impact.
Summary of the invention
The invention aims to solve existing single-channel data and send the deficiency that adapter exists, it is proposed to a kind of Three-channel data sends adapter, can carry two-way or three-channel parallel data simultaneously, and provide speed handoff functionality.
It is an object of the invention to be achieved through the following technical solutions.
A kind of Three-channel data sends adapter, including: data processing module A and switching output module B.
Its annexation is: the input of data processing module A is connected with the outfan of the CPCI computer in external equipment；The outfan of data processing module A is connected with the input of switching output module B；The outfan of switching output module B is connected with the input of the 2nd CPCI computer in external equipment.
A CPCI computer export data address multiplexed information in external equipment and control signal are to data processing module A；Data processing module A isolates data message and address information from the data address multiplexed information received；Then data message is processed by data processing module A, is converted into n road synchronous difference signal, and the value of n is 2 or 3；Data processing module A is again by address information, control signal and n road synchronous difference signal input to switching output module B；The address information received, control signal and n road synchronous difference signal are carried out forwarding the input of the 2nd CPCI computer exported to external equipment by switching output module B.
Described data processing module A includes CPCI computer interface 1, CPCII/O accelerator 2, data transmission control module the 3, first buffer the 4, second buffer the 5, the 3rd buffer 6, interface conversion output module 7, power module 8, crystal oscillator 9 and parameter configuration module 10；
CPCI computer interface 1 provides incoming level, power module 8 to complete the voltage conversion function of incoming level to power module 8, and sends all parts offer running voltage of adapter to described Three-channel data.
Data address multiplexed information and control signal that a CPCI computer in external equipment is transmitted by CPCI computer interface 1 send into CPCII/O accelerator 2；CPCII/O accelerator 2 is separated into 32 parallel bit data information and 32 bit address information output in the data address multiplexed information that data transmission controls to be transmitted by CPCI computer interface 1 under the control of the control signal of module 3 offer and the clock signal of crystal oscillator 9 offer and controls module 3 to data transmission；The 32 bit data information that CPCII/O accelerator 2 is inputted by data transmission control module 3 are separately input into first buffer the 4, second buffer 5 and the 3rd buffer 6 carries out buffer memory；Data send and the data of first buffer the 4, second buffer 5 and the 3rd buffer 6 buffer memory are read out under the effect controlling the clock signal that module 3 provides at crystal oscillator 9 and carry out parallel-serial conversion formation n road synchrodata；The n road synchrodata that data transmission control module 3 inputs is converted into n road synchronous difference signal and exports to switching output module B by interface conversion output module 7；Crystal oscillator 9 respectively CPCII/O accelerator 2, data send control module 3 and provide clock signal；Parameter configuration module 10 carries out parameter configuration for CPCII/O accelerator 2.
Described data send control module 3 and include cpci bus control module 11, data preprocessing module 12, buffer control module 13, data conversion module 14 and speed generation module 15.Cpci bus controls module 11 and sends 3 tunnel control signals, is respectively sent to CPCII/O accelerator 2, speed generation module 15 and data preprocessing module 12；32 bit address information are sent to speed generation module 15 by CPCII/O accelerator 2, send 32 bit data information to data preprocessing module 12 simultaneously；Data preprocessing module 12 controls under the control of module 11 at cpci bus, 32 bit data information converts first buffer the 4, second buffer 5 and 16 bit wide data that the 3rd buffer 6 carries deliver to buffer and control module 13 to；16 bit wide data control to write the first buffer 4 or the second buffer 5 or the 3rd buffer 6 buffer memory under the operation of module 13 at buffer, and the 16 bit wide data being first stored in buffer are read from the first buffer 4 or the second buffer 5 or the 3rd buffer 6 and inputted to data conversion module 14；Speed generation module 15 is under the effect of the clock signal that cpci bus controls the control signal that sends of module 11 and crystal oscillator 9 provides, and generating rate information is also sent to data conversion module 14；16 bit wide data are changed into n road synchrodata under the rate information effect that speed generation module 15 exports and export to interface conversion output module 7 by data conversion module 14.
The rate information of described speed generation module 15 output is controlled, and 25.6Mbps and following bit rate are optional.
It is-20 DEG C～+55 DEG C that described Three-channel data sends the operating temperature range of adapter.
Beneficial effect
The Three-channel data that the present invention proposes sends adapter and has the following advantages compared with existing single-channel data transmission adapter:
1. the present invention adopts large capacity cache device FIFO (FirstInandFirstOut) for data buffer storage, buffer adopts the FIFO of 16 bit wides, 32 bit parallel data of CPCI are converted into high 16 and are stored in buffer with low 16 bit parallel data, save the wiring space of printed board, simplify design.
2. bit rate is optional, it may be achieved the multiple speed of below 25.6Mbps, changes easy to operate.
3. the data that the present invention can realize three tunnels different are transmitted, and interact with a computer.
4. the present invention adopts IC-components to make, and has the advantages such as rate controlled is flexible, reliability is high, use wider range.
Accompanying drawing explanation
Fig. 1 is the electrical schematic diagram that in the specific embodiment of the invention, Three-channel data sends adapter.
Fig. 2 is the electrical schematic diagram of the data processing module A that Three-channel data sends adapter in the specific embodiment of the invention；
Wherein, 1-CPCI computer interface, 2-CPCII/O accelerator, 3-data send and control module, 4-the first buffer, 5-the second buffer, 6-the 3rd buffer, 7-interface conversion output module, 8-power module, 9-crystal oscillator, 10-parameter configuration module；
Fig. 3 is the electrical schematic diagram of data transmission control module (3) that Three-channel data sends adapter in the specific embodiment of the invention；
Wherein, 11-CPCI bus control module, 12-data preprocessing module, 13-buffer control module, 14-data conversion module, 15-speed generation module.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention will be further described.
Three-channel data in the present embodiment sends adapter, and its electrical schematic diagram is as it is shown in figure 1, include: data processing module A and switching output module B.
Its annexation is: the input of data processing module A is connected with the outfan of the CPCI computer in external equipment；The outfan of data processing module A is connected with the input of switching output module B；The outfan of switching output module B is connected with the input of the 2nd CPCI computer in external equipment.
A CPCI computer export data address multiplexed information in external equipment and control signal are to data processing module A；Data processing module A isolates data message and address information from the data address multiplexed information received；Then data message is processed by data processing module A, is converted into n road synchronous difference signal, and the value of n is 2 or 3；Data processing module A is again by address information, control signal and n road synchronous difference signal input to switching output module B；The address information received, control signal and n road synchronous difference signal are carried out forwarding the input of the 2nd CPCI computer exported to external equipment by switching output module B.
Described data processing module A, its electrical schematic diagram is as in figure 2 it is shown, include: CPCI computer interface 1, CPCII/O accelerator 2, data send and control module the 3, first buffer the 4, second buffer the 5, the 3rd buffer 6, interface conversion output module 7, power module 8, crystal oscillator 9 and parameter configuration module 10；
CPCI computer interface 1 provides incoming level, power module 8 to complete the voltage conversion function of incoming level to power module 8, and sends all parts offer running voltage of adapter to described Three-channel data.Owing to line is too much, Fig. 1 to Fig. 3 does not represent the connecting line that power module 8 sends all parts offer running voltage of adapter to described Three-channel data.
Data address multiplexed information and control signal that a CPCI computer in external equipment is transmitted by CPCI computer interface 1 send into CPCII/O accelerator 2；CPCII/O accelerator 2 is separated into 32 parallel bit data information and 32 bit address information output in the data address multiplexed information that data transmission controls to be transmitted by CPCI computer interface 1 under the control of the control signal of module 3 offer and the clock signal of crystal oscillator 9 offer and controls module 3 to data transmission；The 32 bit data information that CPCII/O accelerator 2 is inputted by data transmission control module 3 are separately input into first buffer the 4, second buffer 5 and the 3rd buffer 6 carries out buffer memory；Data send and the data of first buffer the 4, second buffer 5 and the 3rd buffer 6 buffer memory are read out under the effect controlling the clock signal that module 3 provides at crystal oscillator 9 and carry out parallel-serial conversion formation n road synchrodata；The n road synchrodata that data transmission control module 3 inputs is converted into n road synchronous difference signal and exports to switching output module B by interface conversion output module 7；Crystal oscillator 9 respectively CPCII/O accelerator 2, data send control module 3 and provide clock signal；Parameter configuration module 10 carries out parameter configuration for CPCII/O accelerator 2.
Described data send and control module 3, and its electrical schematic diagram is as it is shown on figure 3, include: cpci bus controls module 11, data preprocessing module 12, buffer control module 13, data conversion module 14 and speed generation module 15.Cpci bus controls module 11 and sends 3 tunnel control signals, is respectively sent to CPCII/O accelerator 2, speed generation module 15 and data preprocessing module 12；32 bit address information are sent to speed generation module 15 by CPCII/O accelerator 2, send 32 bit data information to data preprocessing module 12 simultaneously；Data preprocessing module 12 controls under the control of module 11 at cpci bus, 32 bit data information converts first buffer the 4, second buffer 5 and 16 bit wide data that the 3rd buffer 6 carries deliver to buffer and control module 13 to；16 bit wide data control to write the first buffer 4 or the second buffer 5 or the 3rd buffer 6 buffer memory under the operation of module 13 at buffer, and the 16 bit wide data being first stored in buffer are read from the first buffer 4 or the second buffer 5 or the 3rd buffer 6 and inputted to data conversion module 14；Speed generation module 15 is under the effect of the clock signal that cpci bus controls the control signal that sends of module 11 and crystal oscillator 9 provides, and generating rate information is also sent to data conversion module 14；16 bit wide data are changed into n road synchrodata under the rate information effect that speed generation module 15 exports and export to interface conversion output module 7 by data conversion module 14.
The input voltage V of described power module 8 is 5V, and output voltage is+5V ,+3.3V ,+1.5V.Completing the voltage conversion function of incoming level, it is provided that each component working voltage, in embodiment, input voltage V is 5V, and power module 8 adopts commercially available DC-DC modular converter to make.
The rate information of described speed generation module 15 output is controlled, and 25.6Mbps and following bit rate are optional.
It is-20 DEG C～+55 DEG C that described Three-channel data sends the operating temperature range of adapter.
Specifically used operating procedure is:
1) data processing module A inserts in the slot of CPCI computer, and switching output module B inserts in the pit that CPCI computer is corresponding, connects the netting twine of outwards output, powers up, and installs driver；
2) opening operation environment, carries out speed switching and sends out data, and synchrodata is outwards transmitted through netting twine.
Claims (2)
1. a Three-channel data sends adapter, it is characterised in that: including: data processing module A and switching output module B；
Its annexation is: the input of data processing module A is connected with the outfan of the CPCI computer in external equipment；The outfan of data processing module A is connected with the input of switching output module B；The outfan of switching output module B is connected with the input of the 2nd CPCI computer in external equipment；
A CPCI computer export data address multiplexed information in external equipment and control signal are to data processing module A；Data processing module A isolates data message and address information from the data address multiplexed information received；Then data message is processed by data processing module A, is converted into n road synchronous difference signal, and the value of n is 2 or 3；Data processing module A is again by address information, control signal and n road synchronous difference signal input to switching output module B；The address information received, control signal and n road synchronous difference signal are carried out forwarding the input of the 2nd CPCI computer exported to external equipment by switching output module B；
Described data processing module A includes CPCI computer interface (1), CPCII/O accelerator (2), data transmission control module (3), the first buffer (4), the second buffer (5), the 3rd buffer (6), interface conversion output module (7), power module (8), crystal oscillator (9) and parameter configuration module (10)；
CPCI computer interface (1) provides incoming level to power module (8), and power module (8) completes the voltage conversion function of incoming level, and sends all parts offer running voltage of adapter to described Three-channel data；
Data address multiplexed information and control signal that a CPCI computer in external equipment is transmitted by CPCI computer interface (1) send into CPCII/O accelerator (2)；CPCII/O accelerator (2) sends in data and controls module (3) control signal that provides and CPCI computer interface (1) transmits under the control of clock signal that crystal oscillator (9) provides the data address multiplexed information come be separated into 32 parallel bit data information and 32 bit address information and export to data and send control module (3)；The 32 bit data information that CPCII/O accelerator (2) is inputted by data transmission control module (3) are separately input into the first buffer (4), the second buffer (5) and the 3rd buffer (6) and carry out buffer memory；Data send and the data of the first buffer (4), the second buffer (5) and the 3rd buffer (6) buffer memory are read out under the effect controlling the clock signal that module (3) provides at crystal oscillator (9) and carry out parallel-serial conversion formation n road synchrodata；The n road synchrodata that data transmission control module (3) input is converted into n road synchronous difference signal and exports to switching output module B by interface conversion output module (7)；Crystal oscillator (9) respectively CPCII/O accelerator (2), data send and control module (3) offer clock signal；Parameter configuration module (10) carries out parameter configuration for CPCII/O accelerator (2)；
Described data send control module (3) and include cpci bus control module (11), data preprocessing module (12), buffer control module (13), data conversion module (14) and speed generation module (15)；Cpci bus controls module (11) and sends 3 tunnel control signals, is respectively sent to CPCII/O accelerator (2), speed generation module (15) and data preprocessing module (12)；32 bit address information are sent to speed generation module (15) by CPCII/O accelerator (2), send 32 bit data information to data preprocessing module (12) simultaneously；Data preprocessing module (12) controls under the control of module (11) at cpci bus, 32 bit data information converts to 16 bit wide data that the first buffer (4), the second buffer (5) and the 3rd buffer (6) carry and delivers to buffer control module (13)；16 bit wide data control to write the first buffer (4) or the second buffer (5) or the 3rd buffer (6) buffer memory under the operation of module (13) at buffer, and the 16 bit wide data being first stored in buffer are read from the first buffer (4) or the second buffer (5) or the 3rd buffer (6) and inputted to data conversion module (14)；Speed generation module (15) is under the effect of the clock signal that cpci bus controls module (11) control signal that sends and crystal oscillator (9) provides, and generating rate information is also sent to data conversion module (14)；16 bit wide data are changed into n road synchrodata under the rate information effect that speed generation module (15) exports and export to interface conversion output module (7) by data conversion module (14)；
The rate information that described speed generation module (15) exports is controlled, and 25.6Mbps and following bit rate are optional.
2. a kind of Three-channel data as claimed in claim 1 sends adapter, it is characterised in that: it is-20 DEG C～+55 DEG C that described Three-channel data sends the operating temperature range of adapter.
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| CN201310326473.6A CN103425615B (en) | 2013-07-31 | 2013-07-31 | Three-channel data sends adapter |
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| CN201310326473.6A CN103425615B (en) | 2013-07-31 | 2013-07-31 | Three-channel data sends adapter |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6968407B2 (en) * | 2001-12-15 | 2005-11-22 | Lg Electronics Inc. | System and method for managing CPCI buses in a multi-processing system |
| CN101963948A (en) * | 2010-08-26 | 2011-02-02 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN203350873U (en) * | 2013-07-31 | 2013-12-18 | 中国人民解放军海军装备研究院信息工程技术研究所 | Three-channel data sending adapter |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6968407B2 (en) * | 2001-12-15 | 2005-11-22 | Lg Electronics Inc. | System and method for managing CPCI buses in a multi-processing system |
| CN101963948A (en) * | 2010-08-26 | 2011-02-02 | 北京航空航天大学 | BMCH protocol data transceiver module based on CPCI bus |
| CN203350873U (en) * | 2013-07-31 | 2013-12-18 | 中国人民解放军海军装备研究院信息工程技术研究所 | Three-channel data sending adapter |
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