CN103414365B - Vector sequence selection method of diode-clamped five-level inverter - Google Patents

Abstract

The invention discloses a vector sequence selection method of a diode-clamped five-level inverter. The method is based on objective function optimization and employs a great number of redundancy vectors of hexagons of inner two layers, so as to construct seven-segment and five-segment vector sequences and to determine a vector sequence narrow-pulse elimination rule. When a reference vector is in a triangle 1, a three-phase optimal switching seven-segment sequence is selected to control balance of a capacitor voltage, and the five-segment sequence assists the narrow-pulse elimination; and when the reference vector is in a triangle 2 to 4, three-phase next-optimal switching seven-segment and five-segment sequences are selected to jointly control a capacitor voltage-sharing at a direct current side, and as a result, the narrow-pulse elimination is carried out. The vector sequence selection method realizes the balance control of the capacitor voltage at the direct current side when the diode-clamped five-level inverter is at the low modulation ratio, and the algorithm eliminates the narrow-pulse problem and is not influenced by the inverter power factor.

Description

The system of selection of a kind of diode clamp type five-electrical level inverter vector sequence

Technical field

The present invention relates to the system of selection of a kind of diode clamp type five-electrical level inverter vector sequence, belong to multi-electrical level inverter field.

Background technology

In recent years, a focus of research is become in high-power application multi-level power converter technology.Multi-electrical level inverter can realize high voltage with withstand voltage lower power device and export, relative to two-level inverter, there is the advantages such as output voltage grade is high, harmonic characterisitic good, switching loss is little, thus have good application prospect in fields such as high-voltage AC motor speed governing, distributed power generation, static reactive, VSC-HVDCs.

Multi-level converter mainly contains H bridge cascade connection type, diode clamp type and striding capacitance type three kinds of typical topology, and other structures all can derive from this basis and obtain.Wherein H bridge cascade connection type easily can realize High voltage output by multiple units in series, and more shortcoming needs complicated phase shifting transformer to provide to organize insulating power supply; The clamp capacitor of the many level of striding capacitance to One's name is legion all presses difficulty, and considers that the reliability of clamp capacitor own is lower, and therefore the application of the many level of striding capacitance is less; Diode clamp type level without the need to organizing independent current source and reliability is higher more, but its main circuit structure and modulation algorithm complexity sharply rise along with the increase of level number, generally only studies five level and the many level of following clamper type.

The subject matter that multi-level NPC inverter exists is that DC capacitor voltage is unbalanced, wherein the capacitor voltage equalizing research of three-level NPC inverter is quite ripe, and more clamper type many level DCs lateral capacitance balance of voltage of high level number does not also have ripe scheme at present.Diode clamp type five-electrical level inverter polar plot forms by 4 hexagonal centre are nested, and wherein internal layer hexagon contains 6 effective vectors, and each vector has 4 kinds of redundant states, and second layer hexagon contains 12 effective vectors, and each vector has 3 kinds of redundant states.

When modulating less, the redundant vectors of interior two-layer hexagon One's name is legion can be utilized to control DC capacitor voltage balance, but have various ways at the nearest three vector S VM vector sequences of structure, conventional has seven segmentations and five-part form two kinds, vector sequence make is different, also different on the impact of DC capacitor voltage.Select in addition to need during vector sequence to consider that inverter is to the requirement of output voltage saltus step, for diode clamp type five-electrical level inverter, state keeps or single-phase single-grade switches to three-phase state optimal switching, and inverter output line voltage burr can be increased during the switching of two-phase single-stage, be therefore that suboptimum switches.Select three-phase state optimal switching no doubt can reduce output line voltage burr, but available vector sequence also reduces, and weakens the control ability of DC capacitor voltage, and need the problem considering burst pulse.Therefore, how effectively selecting vector sequence, is very important to realizing the balance of DC capacitor voltage.

Summary of the invention

Goal of the invention: the present invention proposes the system of selection of a kind of diode clamp type five-electrical level inverter vector sequence, the balance realizing the DC capacitor voltage of diode clamp type five-electrical level inverter under low modulation ratio controls.

Technical scheme: the technical solution used in the present invention is the system of selection of a kind of diode clamp type five-electrical level inverter vector sequence, comprises the following steps:

1) 16 triangles are become to each se ctor partition in three-phase five level vector space, and construct seven segmentation vector sequences and five-part form vector sequence by four of this sector internal layer triangles;

2) according to the drive singal of seven segmentations constructed in step 1) and five-part form vector sequence, determine that their vector sequence burst pulse eliminates rule respectively;

3) when reference vector is positioned at sector the first triangle, select five-electrical level inverter three-phase state optimal switching seven segmentation vector sequence to capacitance voltage Pressure and Control, and five-part form vector sequence assist burst pulse to eliminate;

When reference vector is positioned at sector second to the 4th triangle, selects five-electrical level inverter three-phase state suboptimum to switch seven segmentation vector sequences and five-part form vector sequence jointly to capacitance voltage Pressure and Control, consider elimination and the process of burst pulse on this basis.

As a modification of the present invention, the structure of described vector sequence comprises the steps:

1) 10 seven segmentation vector sequences and 11 five-part form vector sequences are constructed at triangle 1;

2) 7 seven segmentation vector sequences and 8 five-part form vector sequences are constructed at triangle 2;

3) 8 seven segmentation vector sequences and 9 five-part form vector sequences are constructed at triangle 3;

4) 7 seven segmentation vector sequences and 8 five-part form vector sequences are constructed at triangle 4.

As a further improvement on the present invention, described vector sequence burst pulse is eliminated and is comprised the steps:

1) by the drive singal of seven segmentation vector sequences, determine that seven segmentation vector sequence burst pulses eliminate rule;

2) by the drive singal of five-part form vector sequence, determine that five-part form vector sequence burst pulse eliminates rule.

Beneficial effect: present invention achieves diode clamp type five-electrical level inverter low modulation than time DC capacitor voltage balance control, algorithm is by the impact of power factor.Play seven advantages that segmentation vector sequence Approximation effect is good and voltage harmonic is little simultaneously, eliminate the impact of burst pulse.

Accompanying drawing explanation

Fig. 1 is the circuit topology figure of the present invention one phase brachium pontis;

Fig. 2 is three-phase five-level inverter polar plot;

Fig. 3 is sector I first to fourth DELTA vectors exploded view;

Fig. 4 is the drive singal that vector sequence is corresponding;

Fig. 5 is M=0.2 simulation waveform;

Fig. 6 is M=0.48 simulation waveform;

Fig. 7 is M=0.2 experimental waveform;

Fig. 8 is M=0.48 experimental waveform.

Embodiment

Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to various equivalents of the present invention has all fallen within the application's claims limited range.

As shown in Figure 1, other two-phase brachium pontis are identical with Fig. 1 for the topological structure of one phase brachium pontis of the diode clamp type five level main circuit that the present invention improves.DC side is by four group capacitor C1 ~ C4,5 grades of level in series, and wherein Rp is auxiliary grading resistor, and Rs, Ds and Cs form RCD absorbing circuit.The output Vxo (x=a, b, c) of inverter can have 5 kinds of level (-2E, E, 0, E, 2E), the operating state (0,1,2,3,4) that correspondence 5 kinds is different.Three-phase five-level inverter has 125 vectors, and as shown in Figure 2, wherein 61 effective vectors, remaining is redundant vectors.

All pressures strategy of based target function optimization is to reduce DC bus capacitor energy error for foundation, and the energy error function definition of diode clamp type five-electrical level inverter is as follows:

$J=\frac{1}{2}C\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}^2---\left(1\right)$

Wherein Δ v _cjfor DC bus capacitor C _jthe voltage deviation of (j=1,2,3,4), i.e. Δ v _cj=v _cj-E, it is zero that ideal all presses the value of J minimum.

$\frac{\mathrm{dJ}}{\mathrm{dt}}=C\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}\frac{{\mathrm{dv}}_{\mathrm{Cj}}}{\mathrm{dt}}=\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}{i}_{\mathrm{Cj}}\≤0---\left(2\right)$

By obtaining formula (2) to formula (1) differentiate, then the value of formula (2) is less, all presses more favourable to DC side.Wherein i _cjfor flowing through electric capacity C _jelectric current, from main circuit, i _cjby the impact of inverter mid point current i x (x=1,2,3), and there is following expression:

$\left\{\begin{array}{c}{i}_{C4}=i_3+i_{C3}\\ i_{C3}=i_2+i_{C2}\\ i_{C2}=i_1+i_{C1}\end{array}\right.---\left(3\right)$

DC input voitage is steady, ignores the ripple voltage of Vdc:

$\frac{{\mathrm{dV}}_{\mathrm{dc}}}{\mathrm{dt}}=\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\frac{{\mathrm{dv}}_{\mathrm{Cj}}}{\mathrm{dt}}=\underset{j=1}{\overset{4}{\mathrm{\Σ}}}{i}_{\mathrm{Cj}}=0---\left(4\right)$

Association type (3) and formula (4) can obtain:

$i_{\mathrm{Cj}}=\frac{1}{4}\underset{x=1}{\overset{3}{\mathrm{\Σ}}}{\mathrm{xi}}_x-\underset{x=j}{\overset{3}{\mathrm{\Σ}}}{i}_x,(j=\mathrm{1,2,3,4})---\left(5\right)$

Formula (5) is substituted into formula (2) obtain:

$\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}(\frac{1}{4}\underset{x=1}{\overset{3}{\mathrm{\Σ}}}{\mathrm{xi}}_x-\underset{x=j}{\overset{3}{\mathrm{\Σ}}}{i}_x)\≤0---\left(6\right)$

From converter main circuit, formula (6) can be reduced to further:

$\underset{j=1}{\overset{3}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}\left(\underset{x=j}{\overset{3}{\mathrm{\Σ}}}{i}_x\right)\≥0---\left(7\right)$

Note control cycle (sampling period) is T _s, can obtain formula (7) integration in a control cycle:

$\frac{1}{T_S}{\∫}_{k{T}_S}^{(k+1)T_S}\underset{j=1}{\overset{3}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}\left(\underset{x=j}{\overset{3}{\mathrm{\Σ}}}{i}_x\right)\mathrm{dt}\≥0---\left(8\right)$

Control cycle T _sgeneral at microsecond or Millisecond, think at this moment that capacitance voltage is similar to constant, formula (8) can be reduced to further:

$\underset{j=1}{\overset{3}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}\left(k\right)\left(\underset{x=j}{\overset{3}{\mathrm{\Σ}}}\frac{1}{T_S}{\∫}_{k{T}_S}^{(k+1)T_S}{i}_x\right)\mathrm{dt}\≥0---\left(9\right)$

Be designated as:

$P=\underset{j=1}{\overset{3}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}\left(k\right)\left(\underset{x=j}{\overset{3}{\mathrm{\Σ}}}\stackrel{\‾}{i_x}\left(k\right)\right)\≥0---\left(10\right)$

Formula (10) is the target function of algorithm, and the larger effect of all pressing of the value of this target function is better, wherein Δ v _cjk () is the voltage deviation value of a kth control cycle, for the mean value of a kth control cycle inverter mid point electric current, can be tried to achieve by following expression:

${\left[\begin{array}{ccc}\stackrel{\‾}{i_3}& \stackrel{\‾}{i_2}& \stackrel{\‾}{i_1}\end{array}\right]}^T=\mathrm{DS}{\left[\begin{array}{ccc}{i}_a& i_b& i_c\end{array}\right]}^T---\left(11\right)$

Wherein:

$D=\left[\begin{array}{ccc}{a}_{11}& a_{12}& a_{13}\\ a_{21}& a_{22}& a_{23}\\ a_{31}& a_{32}& a_{33}\end{array}\right]---\left(12\right)$

$\left\{\begin{array}{c}{a}_{11}=d_{300}+d_{310}+d_{320}+d_{311}+d_{321}+d_{322}-d_{433}\\ a_{12}=d_{430}+d_{431}+d_{432}\\ a_{13}=d_{443}-d_{330}-d_{332}-d_{331}\\ a_{21}=d_{200}+d_{210}+d_{211}-d_{422}-d_{322}\\ a_{22}=d_{321}+d_{420}+d_{421}+d_{320}\\ a_{23}=d_{432}+d_{442}+d_{332}-d_{220}-d_{221}\\ a_{31}=d_{100}-d_{211}-d_{311}-d_{411}\\ a_{32}=d_{410}+d_{310}+d_{210}\\ a_{33}=d_{421}+d_{431}+d_{441}+d_{321}+d_{331}+d_{221}-d_{110}\end{array}\right.---\left(13\right)$

Wherein d _ijk(i, j, k ∈ [0,1,2,3,4]) are the action time of vector (i j k) when reference vector is positioned at sector I, are obtained by following symmetry when reference vector is positioned at other sectors:

$S=\left[\begin{array}{ccc}{s}_1+s_6& s_2+s_3& s_4+s_5\\ s_2+s_5& s_1+s_4& s_3+s_6\\ s_3+s_4& s_5+s_6& s_1+s_2\end{array}\right]---\left(14\right)$

S in formula _i(i=1 ..., 6) and be sector, reference vector place, for reference vector at sector 1, then s ₁=1, s _i=0 (i ≠ 1).

Based target function optimization is all pressed algorithm can realize total power factor scope at low modulation ratio (being less than 0.5) and is all pressed, and when modulating increase, power factor is lower.So the present invention to only considered in Fig. 2 the vector space that two inner hexagons cover, namely modulation ratio is between 0 ~ 0.5.

Conventional Vector modulation has seven segmentations and five-part form two kinds of modes, and wherein the Approximation effect of seven segmentation synthesis modes is better than five-part form, and output harmonic wave content is also less, therefore should pay the utmost attention to seven segmentation sequences.Be illustrated in figure 3 the first to fourth leg-of-mutton polar plot of five-electrical level inverter sector I, find out whole seven segmentations and the five-part form vector sequence of 4 delta-shaped regions according to rotate path in figure.For the first triangle 1, there are 10 seven segmentation vector sequences and 11 five-part form vector sequences, as shown in table 1:

Table 1 sector I triangle 1 vector sequence

Same method can find out 7 seven segmentation vector sequences and 8 five-part form vector sequences respectively at the second triangle 2 and the 4th triangle 4, and the 3rd triangle 3 is containing 8 seven segmentation vector sequences and 9 five-part form vector sequences, respectively as shown in table 2 ~ 4:

Table 2 sector I triangle 2 vector sequence

Table 3 sector I triangle 3 vector sequence

Table 4 sector I triangle 4 vector sequence

Analyze for table 1 sequence number 1 seven segmentation and five-part form, (a), (b) are respectively the drive singal of its correspondence as shown in Figure 4, T1, T2 and T3 are the action time of nearest three vectors of SVM, wherein the start vector of the corresponding vector sequence of T1.The minimum pulse width of Slate device is δ _t, known by analyzing Fig. 4, the condition that seven segmentation vector sequences eliminate burst pulse is T ₁>=3 δ _t, and five-part form is T ₃>=δ _tand T ₁>=2 δ _t.Other vector sequences are analyzed identical, and just vector needs to do corresponding adjustment according to the start vector of sequence action time.

One-phase five-level inverter existence the best switches, for three-phase, definition status keeps and single-phase single-grade switches to five-electrical level inverter three-phase state optimal switching, and two-phase single-stage switches owing to driving the ardware feature difference such as time delay to cause output line voltage burr to increase, therefore definition comprises two-phase single-stage and switches to five-electrical level inverter three-phase state suboptimum to switch.For inverter current operating state for (110) and reference vector is positioned at I sector triangle 1, consider seven segmentation vector sequences.As shown in table 1, the start vector (110) of sequence 3 is identical with inverter current state, therefore sequence 3 is state maintenance sequence, and the start vector of sequence 2 and sequence 4 is respectively (100) and (111), inverter is switched to sequence 2 by current state (110) or sequence 4 needs to carry out single-phase single-grade state transition, therefore sequence 2 and sequence 4 are single-phase single-grade switching sequence, and final nucleotide sequence 1 (000) and sequence 5 (211) are two-phase single-stage switching sequence.According to definition, sequence 3,2 and 4 is five-electrical level inverter three-phase state optimal switching sequence, and sequence 3,2,4,1 and 5 is five level inverse conversion three-phase state suboptimum switching sequences.

Diode clamp type five-electrical level inverter low modulation than time vector sequence switching law as follows:

(1) when reference vector is positioned at triangle 1, select five-electrical level inverter three-phase state optimal switching seven segmentation vector sequence all to press DC bus capacitor, and five-part form vector sequence assist burst pulse to eliminate.

(2) when reference vector is positioned at triangle 2 ~ 4, selection five-electrical level inverter three-phase state suboptimum switches seven segmentations and five-part form vector sequence is all pressed DC bus capacitor jointly, considers that burst pulse is eliminated on this basis.

Simulation parameter is: DC voltage is 400V, switching frequency 2kHz, Dead Time 5us, minimum pulse width 7us, electric capacity C1=C2=C3=C4=6800uF, resistance sense load R=10 Ω, L=15mH.

Modulation ratio M=0.2 is set, frequency of modulated wave is 10Hz, power factor is 0.996, now reference vector is positioned at triangle 1, Fig. 5 (a) is inverter output line voltage Vab and electric current I a waveform, and (b) is DC capacitor voltage waveform, and now power inverter runs with nearly unity power factor, voltage fluctuation of capacitor peak-to-peak value is about 2V, all presses effect more satisfactory.

Modulation ratio M=0.48 is set, frequency of modulated wave is 25Hz, power factor is 0.973, application vectors switching rule (2), Fig. 6 (a) is inverter output line voltage Vab and circuit I a, and (b) is DC capacitor voltage waveform, inverter runs with High Power Factor, can find out, DC capacitor voltage fluctuation peak-to-peak value is being less than 4V, all presses effect better.

Experiment condition: provide 400V DC power supply (having fluctuation according to load difference) by three-phase diode rectifier bridge, switching frequency 2kHz, Dead Time 5us, minimum pulse width 7us, C1=C2=C3=C4=6800uF, load be threephase asynchronous to dragging three-phase permanent synchronous generator, generator export connect 3 1kW electric furnaces, wherein Rated motor voltage is 380V, and rated power is 3kW.Oscilloscope CH1 ~ CH4 corresponding VC1 ~ VC4 during measurement direct voltage.

Modulation ratio M=0.2, frequency of modulated wave is 10Hz, experimental waveform as shown in Figure 7, a () is output line voltage Vab and electric current I a, b () is DC capacitor voltage waveform, time unloaded, VC1 and VC4 is about 220V, and VC2 and VC3 is about 30V, and algorithm needs the 1s time to complete all to press.

Modulation ratio M=0.48, frequency of modulated wave is 25Hz, application vectors switching rule (2) test waveform as shown in Figure 8, a () is output line voltage Vab and electric current I a, b () is DC capacitor voltage waveform, can find out in pressure equalizing to there is a little concussion, algorithm probably needs the 5s time to complete all to press.

Claims (3)

1. a diode clamp type five-electrical level inverter vector sequence system of selection, is characterized in that, comprise the following steps:

1) 16 triangles are become to each se ctor partition in three-phase five level vector space, and construct seven segmentation vector sequences and five-part form vector sequence by four of this sector internal layer triangles;

2) according to step 1) in seven segmentations of structure and the drive singal of five-part form vector sequence, determine that their vector sequence burst pulse eliminates rule respectively;

3) when reference vector is positioned at sector the first triangle, select five-electrical level inverter three-phase state optimal switching seven segmentation vector sequence to capacitance voltage Pressure and Control, and five-part form vector sequence assist burst pulse to eliminate;

When reference vector is positioned at sector second to the 4th triangle, selects five-electrical level inverter three-phase state suboptimum to switch seven segmentation vector sequences and five-part form vector sequence jointly to capacitance voltage Pressure and Control, consider elimination and the process of burst pulse on this basis.

2. diode clamp type five-electrical level inverter vector sequence according to claim 1 system of selection, it is characterized in that, the structure of described vector sequence comprises the steps:

1) at the first triangular construction 10 seven segmentation vector sequences and 11 five-part form vector sequences;

2) at the second triangular construction 7 seven segmentation vector sequences and 8 five-part form vector sequences;

3) at the 3rd triangular construction 8 seven segmentation vector sequences and 9 five-part form vector sequences;

4) at the 4th triangular construction 7 seven segmentation vector sequences and 8 five-part form vector sequences.

3. diode clamp type five-electrical level inverter vector sequence according to claim 1 system of selection, is characterized in that, described vector sequence burst pulse is eliminated and comprised the steps:

1) by the drive singal of seven segmentation vector sequences, determine that seven segmentation vector sequence burst pulses eliminate rule;

2) by the drive singal of five-part form vector sequence, determine that five-part form vector sequence burst pulse eliminates rule.