CN103414365A - Vector sequence selection method of diode-clamped five-level inverter - Google Patents

Abstract

The invention discloses a vector sequence selection method of a diode-clamped five-level inverter. The method is based on objective function optimization and employs a great number of redundancy vectors of hexagons of inner two layers, so as to construct seven-segment and five-segment vector sequences and to determine a vector sequence narrow-pulse elimination rule. When a reference vector is in a triangle 1, a three-phase optimal switching seven-segment sequence is selected to control balance of a capacitor voltage, and the five-segment sequence assists the narrow-pulse elimination; and when the reference vector is in a triangle 2 to 4, three-phase next-optimal switching seven-segment and five-segment sequences are selected to jointly control a capacitor voltage-sharing at a direct current side, and as a result, the narrow-pulse elimination is carried out. The vector sequence selection method realizes the balance control of the capacitor voltage at the direct current side when the diode-clamped five-level inverter is at the low modulation ratio, and the algorithm eliminates the narrow-pulse problem and is not influenced by the inverter power factor.

Description

The system of selection of a kind of diode clamp type five-electrical level inverter vector sequence

Technical field

The present invention relates to the system of selection of a kind of diode clamp type five-electrical level inverter vector sequence, belong to the multi-electrical level inverter field.

Background technology

In recent years, in high-power application multi-level power converter technology, become a focus of research.Multi-electrical level inverter can be realized high voltage output with withstand voltage lower power device, with respect to two-level inverter, have the advantages such as the output voltage grade is high, harmonic characterisitic good, switching loss is little, thereby in fields such as high-voltage AC motor speed governing, distributed power generation, static reactive, VSC-HVDCs, good application prospect is arranged.

Multi-level converter mainly contains H bridge cascade connection type, diode clamp type and three kinds of canonical topology structures of striding capacitance type, and other structures all can derive from and obtain on this basis.Wherein H bridge cascade connection type can easily be realized High voltage output by a plurality of units in series, and shortcoming is to need complicated phase shifting transformer that many group insulating power supplies are provided; The many level of striding capacitance are all pressed difficulty to the clamp capacitor of One's name is legion, and consider that the reliability of clamp capacitor own is lower, so the application of the many level of striding capacitance is less; Diode clamp type level is higher without many group independent current sources and reliability, yet the sharply rising along with the increase of level number of its main circuit structure and modulation algorithm complexity is studied five level and the many level of following clamper type for general.

The subject matter that diode clamp type multi-level converter exists is that DC capacitor voltage is unbalanced, wherein the research of the capacitor voltage equalizing of three-level NPC inverter is quite ripe, and more level DCs of clamper type lateral capacitance balance of voltage of high level number does not also have ripe scheme at present.Diode clamp type five-electrical level inverter polar plot is by 4 hexagonal centre nested compositions, and wherein the internal layer hexagon contains 6 effective vectors, and each vector has 4 kinds of redundant states, and second layer hexagon contains 12 effective vectors, and each vector has 3 kinds of redundant states.

When modulation hour, can utilize the redundancy vector of interior two-layer hexagon One's name is legion to control the DC capacitor voltage balance, yet at the nearest three vector S VM vector sequences of structure, various ways is arranged, commonly used have two kinds of seven segmentations and five-part forms, vector sequence make difference is also different on the impact of DC capacitor voltage.While selecting vector sequence in addition, need the requirement of taking into account inverter to the output voltage saltus step, for diode clamp type five-electrical level inverter, state keeps or single-phase single-grade switches to the optimum switching of three-phase state, and the switching of two-phase single-stage the time can increase inverter output line voltage burr, therefore for suboptimum, switch.Select the optimum switching of three-phase state no doubt can reduce the output line voltage burr, however available vector sequence also reduce, the control ability of DC capacitor voltage is weakened, and needs to consider the problem of burst pulse.Therefore, how effectively to select vector sequence, to realizing that the balance to DC capacitor voltage is very important.

Summary of the invention

Goal of the invention: the present invention proposes the system of selection of a kind of diode clamp type five-electrical level inverter vector sequence, realizes that the balance of the DC capacitor voltage of diode clamp type five-electrical level inverter under the low modulation ratio is controlled.

Technical scheme: the technical solution used in the present invention is the system of selection of a kind of diode clamp type five-electrical level inverter vector sequence, comprises the following steps:

1) each sector in three-phase five level vector spaces is divided into to 16 triangles, and by structure seven segmentation vector sequences and five-part form vector sequence in four triangles of this sector internal layer;

2), according to the driving signal of seven segmentations of constructing in step 1) and five-part form vector sequence, determine that respectively their vector sequence burst pulse is eliminated rule;

3), when reference vector is positioned at sector the first triangle, select the optimum switching of five-electrical level inverter three-phase state seven segmentation vector sequences to the capacitance voltage Pressure and Control, and the auxiliary burst pulse of five-part form vector sequence is eliminated;

When reference vector is positioned at sector second to the 4th triangle, select five-electrical level inverter three-phase state suboptimum switching seven segmentation vector sequences and five-part form vector sequence jointly to the capacitance voltage Pressure and Control, consider on this basis elimination and the processing of burst pulse.

As a modification of the present invention, the structure of described vector sequence comprises the steps:

1) at triangle 1 10 seven segmentation vector sequences of structure and 11 five-part form vector sequences;

2) at triangle 27 seven segmentation vector sequences of structure and 8 five-part form vector sequences;

3) at triangle 38 seven segmentation vector sequences of structure and 9 five-part form vector sequences;

4) at triangle 47 seven segmentation vector sequences of structure and 8 five-part form vector sequences.

As a further improvement on the present invention, described vector sequence burst pulse is eliminated and is comprised the steps:

1), by the driving signal of seven segmentation vector sequences, determine seven segmentation vector sequence burst pulses elimination rules;

2), by the driving signal of five-part form vector sequence, determine five-part form vector sequence burst pulse elimination rule.

Beneficial effect: the present invention realized diode clamp type five-electrical level inverter low modulation than the time DC capacitor voltage balance control, algorithm is not subjected to the impact of power factor.Bring into play simultaneously seven advantages that segmentation vector sequence Approximation effect is good and voltage harmonic is little, eliminated the impact of burst pulse.

The accompanying drawing explanation

Fig. 1 is the circuit topology figure of the present invention's one phase brachium pontis;

Fig. 2 is three-phase five-electrical level inverter polar plot;

Fig. 3 is sector I first to fourth triangle resolution of vectors figure;

Fig. 4 is the driving signal that vector sequence is corresponding;

Fig. 5 is the M=0.2 simulation waveform;

Fig. 6 is the M=0.48 simulation waveform;

Fig. 7 is the M=0.2 experimental waveform;

Fig. 8 is the M=0.48 experimental waveform.

Embodiment

Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is not used in and limits the scope of the invention be used to the present invention is described, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of various equivalents of the present invention.

As shown in Figure 1, other two-phase brachium pontis are identical with Fig. 1 for the topological structure of one phase brachium pontis of the improved diode clamp type five level main circuits of the present invention.DC side is by four group capacitor C1～C4,5 grades of level in series, and wherein Rp is auxiliary grading resistor, and Rs, Ds and Cs form the RCD absorbing circuit.The output Vxo (x=a, b, c) of inverter can have 5 kinds of level (2E, E, 0, E, 2E), corresponding 5 kinds of different operating states (0,1,2,3,4).The three-phase five-electrical level inverter has 125 vectors, as shown in Figure 2,61 effective vectors wherein, remaining is the redundancy vector.

All pressures strategy of based target function optimization be take and reduced the DC bus capacitor energy error and be foundation, and the energy error function definition of diode clamp type five-electrical level inverter is as follows:

$J=\frac{1}{2}C\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}^2---\left(1\right)$

Δ v wherein _CjFor DC bus capacitor C _jThe voltage deviation of (j=1,2,3,4), i.e. Δ v _Cj=v _Cj-E, it is zero that ideal is all pressed the value minimum of J.

$\frac{\mathrm{dJ}}{\mathrm{dt}}=C\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}\frac{{\mathrm{dv}}_{\mathrm{Cj}}}{\mathrm{dt}}=\underset{j=1}{\overset{4}{\mathrm{\Σ}}}\mathrm{\Δ}{v}_{\mathrm{Cj}}{i}_{\mathrm{Cj}}\≤0---\left(2\right)$

By differentiate obtains formula (2) to formula (1), the value of formula (2) is less, all presses more favourable to DC side.I wherein _CjFor flowing through capacitor C _jElectric current, as can be known by main circuit, i _CjBe subjected to the impact of inverter mid point current i x (x=1,2,3), and have following expression:

$\left\{\begin{array}{c}{i}_{C4}=i_3+i_{C3}\\ i_{\mathrm{<figure-callout\; id="3"\; label="C"\; filenames="HDA00003469280800021.png,HDA00003469280800041.png"\; state="\{\{state\}\}">C</figure-callout>}3}=i_2+i_{C2}\\ i_{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA00003469280800021.png,HDA00003469280800022.png"\; state="\{\{state\}\}">C</figure-callout>}2}=i_1+i_{C1}\end{array}\right.---\left(3\right)$

DC input voitage is steady, ignores the ripple voltage of Vdc:

$\frac{{\mathrm{dV}}_{\mathrm{dc}}}{\mathrm{dt}}=\underset{j=1}{\overset{4}{\mathrm{\&Sigma;}}}\frac{{\mathrm{dv}}_{\mathrm{Cj}}}{\mathrm{dt}}=\underset{j=1}{\overset{4}{\mathrm{\&Sigma;}}}{i}_{\mathrm{Cj}}=0---\left(4\right)$

Association type (3) and formula (4) can obtain:

$i_{\mathrm{Cj}}=\frac{1}{4}\underset{x=1}{\overset{3}{\mathrm{\&Sigma;}}}{\mathrm{xi}}_x-\underset{x=j}{\overset{3}{\mathrm{\&Sigma;}}}{i}_x,(j=\mathrm{1,2,3,4})---\left(5\right)$

Formula (5) substitution formula (2) is obtained:

$\underset{j=1}{\overset{4}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{v}_{\mathrm{Cj}}(\frac{1}{4}\underset{x=1}{\overset{3}{\mathrm{\&Sigma;}}}{\mathrm{xi}}_x-\underset{x=j}{\overset{3}{\mathrm{\&Sigma;}}}{i}_x)\&le;0---\left(6\right)$

As can be known by converter main circuit, formula (6) can further be reduced to:

$\underset{j=1}{\overset{3}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{v}_{\mathrm{Cj}}\left(\underset{x=j}{\overset{3}{\mathrm{\&Sigma;}}}{i}_x\right)\&GreaterEqual;0---\left(7\right)$

Note control cycle (sampling period) is T _S, to formula (7) integration in a control cycle, can obtain:

$\frac{1}{T_S}{\&Integral;}_{k{T}_S}^{(k+1)T_S}\underset{j=1}{\overset{3}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{v}_{\mathrm{Cj}}\left(\underset{x=j}{\overset{3}{\mathrm{\&Sigma;}}}{i}_x\right)\mathrm{dt}\&GreaterEqual;0---\left(8\right)$

Control cycle T _SGenerally at microsecond or Millisecond, at this moment between in think that capacitance voltage is approximate constant, formula (8) can further be reduced to:

$\underset{j=1}{\overset{3}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{v}_{\mathrm{Cj}}\left(k\right)\left(\underset{x=\mathrm{<figure-callout\; id="3"\; label="j"\; filenames="HDA00003469280800021.png,HDA00003469280800041.png"\; state="\{\{state\}\}">j</figure-callout>}}{\overset{3}{\mathrm{\&Sigma;}}}\frac{1}{T_S}{\&Integral;}_{k{T}_S}^{(k+1)T_S}{i}_x\right)\mathrm{dt}\&GreaterEqual;0---\left(9\right)$

Be designated as:

$P=\underset{j=1}{\overset{3}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{v}_{\mathrm{Cj}}\left(k\right)\left(\underset{x=j}{\overset{3}{\mathrm{\&Sigma;}}}\stackrel{\&OverBar;}{i_x}\left(k\right)\right)\&GreaterEqual;0---\left(10\right)$

Formula (10) is the target function of algorithm, and the value of this target function more all presses effect better, wherein Δ v _Cj(k) be the voltage deviation value of k control cycle,

Be the mean value of k control cycle inverter mid point electric current, can try to achieve by following expression:

${\left[\begin{array}{ccc}\stackrel{\&OverBar;}{i_3}& \stackrel{\&OverBar;}{i_2}& \stackrel{\&OverBar;}{i_1}\end{array}\right]}^T=\mathrm{DS}{\left[\begin{array}{ccc}{i}_a& i_b& i_c\end{array}\right]}^T---\left(11\right)$

Wherein:

$D=\left[\begin{array}{ccc}{a}_{11}& a_{12}& a_{13}\\ a_{21}& a_{22}& a_{23}\\ a_{31}& a_{32}& a_{33}\end{array}\right]---\left(12\right)$

$\left\{\begin{array}{c}{a}_{11}={\mathrm{<figure-callout\; id="300"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{300}+{\mathrm{<figure-callout\; id="310"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{310}+{\mathrm{<figure-callout\; id="320"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{320}+{\mathrm{<figure-callout\; id="311"\; label="d"\; filenames="HDA00003469280800012.png,HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{311}+{\mathrm{<figure-callout\; id="321"\; label="d"\; filenames="HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{321}+d_{322}-d_{433}\\ a_{12}={\mathrm{<figure-callout\; id="430"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{430}+{\mathrm{<figure-callout\; id="431"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{431}+d_{432}\\ a_{13}=d_{443}-d_{330}-d_{332}-d_{331}\\ a_{21}={\mathrm{<figure-callout\; id="200"\; label="d"\; filenames="HDA00003469280800021.png,HDA00003469280800032.png"\; state="\{\{state\}\}">d</figure-callout>}}_{200}+{\mathrm{<figure-callout\; id="210"\; label="d"\; filenames="HDA00003469280800012.png,HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{210}+d_{211}-d_{422}-d_{322}\\ a_{22}={\mathrm{<figure-callout\; id="321"\; label="d"\; filenames="HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{321}+{\mathrm{<figure-callout\; id="420"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{420}+{\mathrm{<figure-callout\; id="421"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{421}+d_{320}\\ a_{23}={\mathrm{<figure-callout\; id="432"\; label="d"\; filenames="HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{432}+{\mathrm{<figure-callout\; id="442"\; label="d"\; filenames="HDA00003469280800012.png,HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{442}+d_{332}-d_{220}-d_{221}\\ a_{31}=d_{100}-d_{211}-d_{311}-d_{411}\\ a_{32}={\mathrm{<figure-callout\; id="410"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{410}+{\mathrm{<figure-callout\; id="310"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{310}+d_{210}\\ a_{33}={\mathrm{<figure-callout\; id="421"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{421}+{\mathrm{<figure-callout\; id="431"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{431}+{\mathrm{<figure-callout\; id="441"\; label="d"\; filenames="HDA00003469280800012.png"\; state="\{\{state\}\}">d</figure-callout>}}_{441}+{\mathrm{<figure-callout\; id="321"\; label="d"\; filenames="HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{321}+{\mathrm{<figure-callout\; id="331"\; label="d"\; filenames="HDA00003469280800012.png,HDA00003469280800021.png"\; state="\{\{state\}\}">d</figure-callout>}}_{331}+d_{221}-d_{110}\end{array}\right.---\left(13\right)$

D wherein _ijkThe action time of (i, j, k ∈ [0,1,2,3,4]) vector while being positioned at sector I for reference vector (i j k), when being positioned at other sectors, reference vector obtained by following symmetry:

$S=\left[\begin{array}{ccc}{s}_1+s_6& {\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00003469280800021.png,HDA00003469280800022.png"\; state="\{\{state\}\}">s</figure-callout>}}_2+s_3& s_4+s_5\\ {\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00003469280800021.png,HDA00003469280800022.png"\; state="\{\{state\}\}">s</figure-callout>}}_2+s_5& {\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="HDA00003469280800022.png"\; state="\{\{state\}\}">s</figure-callout>}}_1+s_4& {\mathrm{<figure-callout\; id="3"\; label="s"\; filenames="HDA00003469280800021.png,HDA00003469280800041.png"\; state="\{\{state\}\}">s</figure-callout>}}_3+s_6\\ {\mathrm{<figure-callout\; id="3"\; label="s"\; filenames="HDA00003469280800021.png,HDA00003469280800041.png"\; state="\{\{state\}\}">s</figure-callout>}}_3+s_4& {\mathrm{<figure-callout\; id="5"\; label="s"\; filenames="HDA00003469280800031.png"\; state="\{\{state\}\}">s</figure-callout>}}_5+s_6& {\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="HDA00003469280800022.png"\; state="\{\{state\}\}">s</figure-callout>}}_1+s_2\end{array}\right]---\left(14\right)$

S in formula _i(i=1 ..., 6) and be sector, reference vector place, the reference vector of take 1 is example, s in sector ₁=1, s _i=0 (i ≠ 1).

The based target function optimization all presses algorithm than (being less than 0.5), can realize that total power factor scope all presses in low modulation, and when modulation increased, power factor was lower.So the present invention has only considered two vector spaces that inner hexagon covers in Fig. 2, namely modulation ratio is between 0～0.5.

Vector commonly used is synthetic seven segmentations and two kinds of modes of five-part form, and wherein the Approximation effect of seven segmentation synthesis modes is better than five-part form, and output harmonic wave content is also less, therefore should pay the utmost attention to seven segmentation sequences.Be illustrated in figure 3 the first to fourth leg-of-mutton polar plot of five-electrical level inverter sector I, according to rotate path in figure, find out whole seven segmentations and the five-part form vector sequence of 4 delta-shaped regions.First triangle 1 of take is example, and 10 seven segmentation vector sequences and 11 five-part form vector sequences are arranged, as shown in table 1:

Table 1 sector I triangle 1 vector sequence

Same method can be respectively the second triangle 2 and the 4th triangle 4 find out 7 seven segmentation vector sequences and 8 five-part form vector sequences, and the 3rd triangle 3 contains 8 seven segmentation vector sequences and 9 five-part form vector sequences, respectively as shown in table 2～4:

Table 2 sector I triangle 2 vector sequences

Table 3 sector I triangle 3 vector sequences

Table 4 sector I triangle 4 vector sequences

Take table 1 sequence number 1 seven segmentations and five-part form analyzes as example, and (a), (b) are respectively the driving signal of its correspondence as shown in Figure 4, and T1, T2 and T3 are the action time of nearest three vectors of SVM, wherein the start vector of the corresponding vector sequence of T1.The minimum pulse width of Slate device is δ _T, as can be known by Fig. 4 is analyzed, the condition that seven segmentation vector sequences are eliminated burst pulse is T ₁>=3 δ _T, and five-part form is T ₃>=δ _TAnd T ₁>=2 δ _T.Other vector sequences are analyzed identical, and just vector need to be done corresponding adjustment according to the start vector of sequence action time.

The best switching of single-phase five-electrical level inverter existence, for three-phase, definition status keeps and single-phase single-grade switches to the optimum switching of five-electrical level inverter three-phase state, and two-phase single-stage switching causes the output line voltage burr to increase due to ardware feature differences such as driving time delay, therefore definition comprises the two-phase single-stage and switches to the switching of five-electrical level inverter three-phase state suboptimum.The inverter work at present state of take is example as (110) and reference vector are positioned at I sector triangle 1, considers seven segmentation vector sequences.As shown in table 1, the start vector of sequence 3 (110) is identical with the inverter current state, therefore sequence 3 keeps sequence for state, and the start vector of sequence 2 and sequence 4 is respectively (100) and (111), inverter is switched to sequence 2 by current state (110) or sequence 4 need to be carried out the single-phase single-grade state transition, therefore sequence 2 and sequence 4 are the single-phase single-grade switching sequence, and final nucleotide sequence 1 (000) and sequence 5 (211) are two-phase single-stage switching sequence.According to definition, sequence 3,2 and 4 is the optimum switching sequence of five-electrical level inverter three-phase state, and sequence 3,2,4,1 and 5 is five level inverse conversion three-phase state suboptimum switching sequences.

Diode clamp type five-electrical level inverter low modulation than the time vector sequence switching law as follows:

(1), when reference vector is positioned at triangle 1, select the optimum switching of five-electrical level inverter three-phase state seven segmentation vector sequences all to press DC bus capacitor, and the auxiliary burst pulse of five-part form vector sequence is eliminated.

(2) when reference vector is positioned at triangle 2～4, select five-electrical level inverter three-phase state suboptimum switching seven segmentations jointly DC bus capacitor all to be pressed with the five-part form vector sequence, consider on this basis the burst pulse elimination.

Simulation parameter is: DC voltage is 400V, switching frequency 2kHz, Dead Time 5us, minimum pulse width 7us, capacitor C 1=C2=C3=C4=6800uF, resistance sense load R=10 Ω, L=15mH.

Modulation ratio M=0.2 is set, frequency of modulated wave is 10Hz, power factor is 0.996, now reference vector is positioned at triangle 1, Fig. 5 (a) is inverter output line voltage Vab and electric current I a waveform, (b) is the DC capacitor voltage waveform, and now power inverter moves with nearly unity power factor, the voltage fluctuation of capacitor peak-to-peak value is about 2V, all presses effect more satisfactory.

Modulation ratio M=0.48 is set, frequency of modulated wave is 25Hz, power factor is 0.973, application vector switching law (2), Fig. 6 (a) is inverter output line voltage Vab and circuit I a, (b) is the DC capacitor voltage waveform, inverter moves with High Power Factor, can find out, DC capacitor voltage fluctuation peak-to-peak value is being less than 4V, all presses effect better.

Experiment condition: provide 400V DC power supply (fluctuation being arranged according to the load difference) by the three-phase diode rectifier bridge, switching frequency 2kHz, Dead Time 5us, minimum pulse width 7us, C1=C2=C3=C4=6800uF, load be threephase asynchronous to dragging three-phase permanent synchronous generator, generator output connects 3 1kW electric furnaces, wherein the motor rated voltage is 380V, and rated power is 3kW.Corresponding VC1～the VC4 of oscilloscope CH1～CH4 while measuring direct voltage.

Modulation ratio M=0.2, frequency of modulated wave are 10Hz, and experimental waveform as shown in Figure 7, (a) be output line voltage Vab and electric current I a, (b) be the DC capacitor voltage waveform, when unloaded, VC1 and VC4 are about 220V, and VC2 and VC3 are about 30V, algorithm needs the 1s time to complete all pressures.

Modulation ratio M=0.48, frequency of modulated wave is 25Hz, application vector switching law (2) test waveform as shown in Figure 8, (a) be output line voltage Vab and electric current I a, (b) be the DC capacitor voltage waveform, can find out in pressure equalizing that existing a little concussion, algorithm probably to need the 5s time to complete all presses.

Claims (3)

1. diode clamp type five-electrical level inverter vector sequence system of selection, is characterized in that, comprises the following steps:

1) each sector in three-phase five level vector spaces is divided into to 16 triangles, and by structure seven segmentation vector sequences and five-part form vector sequence in four triangles of this sector internal layer;

2), according to the driving signal of seven segmentations of constructing in step 1) and five-part form vector sequence, determine that respectively their vector sequence burst pulse is eliminated rule;

3), when reference vector is positioned at sector the first triangle, select the optimum switching of five-electrical level inverter three-phase state seven segmentation vector sequences to the capacitance voltage Pressure and Control, and the auxiliary burst pulse of five-part form vector sequence is eliminated;

When reference vector is positioned at sector second to the 4th triangle, select five-electrical level inverter three-phase state suboptimum switching seven segmentation vector sequences and five-part form vector sequence jointly to the capacitance voltage Pressure and Control, consider on this basis elimination and the processing of burst pulse.

2. diode clamp type five-electrical level inverter vector sequence according to claim 1 system of selection is characterized in that the structure of described vector sequence comprises the steps:

1) at triangle 1 10 seven segmentation vector sequences of structure and 11 five-part form vector sequences;

2) at triangle 27 seven segmentation vector sequences of structure and 8 five-part form vector sequences;

3) at triangle 38 seven segmentation vector sequences of structure and 9 five-part form vector sequences;

4) at triangle 47 seven segmentation vector sequences of structure and 8 five-part form vector sequences.

3. diode clamp type five-electrical level inverter vector sequence according to claim 1 system of selection, is characterized in that, described vector sequence burst pulse is eliminated and comprised the steps:

1), by the driving signal of seven segmentation vector sequences, determine seven segmentation vector sequence burst pulses elimination rules;

2), by the driving signal of five-part form vector sequence, determine five-part form vector sequence burst pulse elimination rule.

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