CN103412833A - CPCI (Compact Peripheral Component Interconnect) bus scanning ADC (Analog-to-Digital Converter) function module driver under VxWorks operating system and control method thereof - Google Patents
CPCI (Compact Peripheral Component Interconnect) bus scanning ADC (Analog-to-Digital Converter) function module driver under VxWorks operating system and control method thereof Download PDFInfo
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Abstract
A CPCI (Compact Peripheral Component Interconnect) bus scanning ADC function module driver under a VxWorks operating system and a control method thereof relate to a driver for CPCI bus scanning ADC function modules and a control method, and aim to solve the problem that the conventional process of developing a CPCI bus scanning ADC function module driver is complex and highly difficult. The CPCI bus scanning ADC function module driver under the VxWorks operating system, which is disclosed by the invention, comprises an FPGA (field programmable gate array), an acquisition circuit, eight-channel analog switches, an isolating and conditioning circuit, a CPCI bus interface controller, a configuration circuit, a configuration power supply circuit and a CPCI bus. The control method based on the driver includes: opening a data port and loading a driver; setting channel numbers and starting acquisition channels; acquiring signals; reading the acquired signals; and closing the data port and unloading the driver. The driver and the control method are applicable to CPCI bus scanning ADC function modules under the VxWorks operating system.
Description
Technical field
The present invention relates to a kind of driving arrangement and control method of cpci bus scan A/D C functional module.
Background technology
Under vxworks operating system, cpci bus scan A/D C functional module, as test module important in Auto-Test System, is applied in every field widely.
Scan A/D C driver of modules based on cpci bus under traditional vxworks operating system is developed, as required, realize corresponding power function interface, and be packaged into I/O interface (the I/O interface of seven standards of standard, open () for example, close (), read () etc.), be registered in the system drive list, be articulated under the I/O subsystem.In this process, drive the data structure that the developer need to take out equipment, the establishment of finishing equipment and the installation of device driver, this process more complicated, bring a lot of inconvenience for the driving developer.
Summary of the invention
The present invention seeks to drive in order to solve existing cpci bus scan A/D C functional module the process complexity of exploitation, the problem that development difficulty is larger, provide cpci bus scan A/D C functional module driving arrangement and control method thereof under vxworks operating system.
Cpci bus scan A/D C functional module driving arrangement under vxworks operating system of the present invention, it comprises FPGA, Acquisition Circuit, 4 eight path analoging switch, isolation modulate circuit, cpci bus interface controller, configuration circuit, configuration feed circuit and cpci bus
The cpci bus FPDP of cpci bus interface controller connects cpci bus, and the local bus port of cpci bus interface controller connects the data address bus of FPGA, and the configuration data port of cpci bus interface controller connects the FPDP of configuration circuit,
The input end of isolation modulate circuit is 32 road input end of analog signal, 32 signal output parts of isolation modulate circuit are divided into four groups, 8 signal output parts in every group connect respectively eight input end of analog signal of 1 eight path analoging switch, 4 analog signal outputs of 4 eight path analoging switch connect respectively 4 input end of analog signal of Acquisition Circuit, the digital signal output end of Acquisition Circuit connects the digital signal input end of FPGA, FPGA connects for electrical input the power supply output terminal that configures feed circuit, four groups of analog switch control signal output terminals of FPGA connect respectively the control signal input end of 4 eight path analoging switch.
Control method based on cpci bus scan A/D C functional module driving arrangement under vxworks operating system of the present invention, the process of this control method is:
The FPDP of step 1, FPGA is opened, the load driver program;
It is complete that step 4, FPGA judge whether signal gathers, and if it is performs step five, if otherwise return to step 3;
Step 5, FPGA read the signal that Acquisition Circuit gathers;
The present invention proposes Driver Design and the encapsulation of cpci bus scan A/D C functional module under vxworks operating system, according to the common operation to the ADC functional module, propose a kind of new scan A/D C and drive the interface encapsulation form, realizing to the ADC functional module can greatly reducing the development difficulty that drives the developer in effective control.
The objective of the invention is to invent Driver Design and the encapsulation of cpci bus scan A/D C functional module under a kind of vxworks operating system, characteristics according to scan A/D C functional module, the exploitation driver is realized the control to scan A/D C functional module, a kind of driving interface encapsulation form of new scan A/D C functional module is provided simultaneously, application program-oriented method directly defines the form that drives interface, directly the encapsulation function interface function.In the process that drives exploitation, the design, the equipment that do not relate to the device data structure of traditional scan A/D C functional module create and drive installation, on large program, have reduced very much the development difficulty that drives the developer like this.
Advantage of the present invention:
1), the ADC functional module driver that provides of this method can be realized the effective control to functional module;
2), the direct user oriented application program of ADC functional module driver that provides of this method provides general driving function interface;
3), the ADC functional module Driver Design that provides of this method and encapsulation reduce the difficulty that drives exploitation greatly;
4), this method the ADC functional module Driver Design and the encapsulation that provide have independence and versatility, can be applicable to other design.
The accompanying drawing explanation
Fig. 1 is the structural representation of cpci bus scan A/D C functional module driving arrangement under vxworks operating system of the present invention;
Fig. 2 is the FB(flow block) based on the control method of cpci bus scan A/D C functional module driving arrangement under vxworks operating system of the present invention;
Fig. 3 is the method flow block diagram that the FPDP of FPGA of the present invention is opened;
Fig. 4 is the method flow block diagram that the FPDP of FPGA of the present invention is closed;
Fig. 5 is the FB(flow block) of ADC functional module of the present invention read operation;
Fig. 6 is the FB(flow block) of ADC functional module Real-Time Monitoring of the present invention.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 1, cpci bus scan A/D C functional module driving arrangement under the described vxworks operating system of present embodiment, it comprises FPGA1,2,4 eight path analoging switch 3 of Acquisition Circuit, isolation modulate circuit 4, cpci bus interface controller 5, configuration circuit 6, configuration feed circuit 7 and cpci bus 8
The cpci bus FPDP of cpci bus interface controller 5 connects cpci bus 8, the local bus port of cpci bus interface controller 5 connects the data address bus of FPGA1, the configuration data port of cpci bus interface controller 5 connects the FPDP of configuration circuit 6
The input end of isolation modulate circuit 4 is 32 road input end of analog signal, 32 signal output parts of isolation modulate circuit 4 are divided into four groups, 8 signal output parts in every group connect respectively eight input end of analog signal of 1 eight path analoging switch 3, 4 analog signal outputs of 4 eight path analoging switch 3 connect respectively 4 input end of analog signal of Acquisition Circuit 2, the digital signal output end of Acquisition Circuit 2 connects the digital signal input end of FPGA1, FPGA1 connects for electrical input the power supply output terminal that configures feed circuit 7, four groups of analog switch control signal output terminals of FPGA1 connect respectively the control signal input end of 4 eight path analoging switch 3.
In present embodiment, need cpci bus interface controller 5 between cpci bus 8 and scan A/D C functional circuit, cpci bus interface controller 5 adopts the PCI9054 interface chip of PLX company to realize, cpci bus is transformed into to local bus.PCI9054 local bus side is used FPGA to realize bus interface decoding, and simultaneously, FPGA indoor design control register, realize the control to scan A/D C functional circuit.Scan A/D C funtion part forms 32 tunnel scan A/D C functional circuits by the AD7865 data acquisition chip of 1 successive approximation, 48 path analoging switch chips and 32 AD202 isolating chips, and 32 paths are isolated from each other.
Embodiment two: below in conjunction with Fig. 1, present embodiment is described, present embodiment is described further embodiment one, and described Acquisition Circuit 2 adopts the AD7865 acquisition chip to realize, arrives the conversion of digital quantity be used to realizing analog quantity.
Embodiment three: present embodiment is described below in conjunction with Fig. 1, present embodiment is described further embodiment one, described isolation modulate circuit 4 is 32 tunnel isolation modulate circuits, 32 AD202 isolating chips, consists of, for realizing isolation and the signal condition to simulating signal.
Embodiment four: below in conjunction with Fig. 1, present embodiment is described, present embodiment is described further embodiment one, and described cpci bus interface controller 5 adopts the PCI9054 interface chip to realize.
In present embodiment, complete compatible with PCI 2.2 standards of PCI9054 interface chip, and burst transfers of data speed is high, and the interface chip price is low simultaneously, and versatility is good, can effectively reduce development difficulty.
Embodiment five: below in conjunction with Fig. 2, present embodiment is described, the described control method based on cpci bus scan A/D C functional module driving arrangement under vxworks operating system of present embodiment, the process of this control method is:
The FPDP of step 1, FPGA1 is opened, the load driver program;
It is complete that step 4, FPGA1 judge whether signal gathers, and if it is performs step five, if otherwise return to step 3;
Step 5, FPGA1 read the signal that Acquisition Circuit 2 gathers;
In the present invention, ADC functional module driving arrangement is called for short ADC functional module board, and ADC functional module board operates in the CPCI cabinet.Operate in the application program of controlling on computing machine, realize the control to ADC functional module board by cpci bus, therefore need the driver of exploitation based on cpci bus scan A/D C functional module.
Embodiment six: below in conjunction with Fig. 3, present embodiment is described, present embodiment is described further embodiment five, and the concrete grammar that the FPDP of the described FPGA1 of step 1 is opened is:
Step one by one, FPGA1 transmits the plate card number of the ADC functional module board that will open;
Step 1 two, FPGA1 judge in function body whether the plate card number is correct, if otherwise return to step one by one, if it is perform step one or three;
Step 1 three, ADC functional module memory-mapped base value is assigned to a global variable;
Step 1 four, FPDP have been opened.
Embodiment seven: below in conjunction with Fig. 4, present embodiment is described, present embodiment is described further embodiment five, and the concrete grammar that the FPDP of the described FPGA1 of step 6 is closed is:
In the present invention, ADC functional module driving arrangement is inserted in the CPCI cabinet and moves, and controls computing machine and realizes the read-write of scan A/D C functional module is controlled by cpci bus.Between cpci bus and scan A/D C functional circuit, need to realize the cpci bus interface controller, the cpci bus interface controller adopts the PCI9054 interface chip of PLX company to realize, cpci bus is transformed into to local bus.Complete compatible with PCI 2.2 standards of PCI9054 interface chip, and burst transfers of data speed is high, and the interface chip price is low simultaneously, and versatility is good, can effectively reduce development difficulty.PCI9054 local bus side is used FPGA to realize bus interface decoding, and simultaneously, FPGA indoor design control register, realize the control to scan A/D C functional circuit.Scan A/D C funtion part forms 32 tunnel scan A/D C functional circuits by the AD7865 data acquisition chip of 1 successive approximation, 48 path analoging switch chips and 32 AD202 isolating chips, and 32 paths are isolated from each other.
Scan A/D C functional module operates in the CPCI cabinet, operates in the application program of controlling on computing machine, realizes the control to scan A/D C functional module by cpci bus, therefore needs the driver of exploitation based on cpci bus scan A/D C functional module.The Driver Design of scan A/D C functional module mainly comprises initialization apparatus, the realization of power function interface and encapsulation.
First, initialization apparatus: initialization apparatus is as the important step of CPCI Development of device driver, being mainly to be the hardware distributing system resource, is mainly facility information, device memory mapping and the Break Link obtained based on the scan A/D C functional module of cpci bus here.
Obtain the facility information based on the scan A/D C functional module of cpci bus
After the PCI device power, BIOS can PCI allocation equipment.The BIOS of target machine has the information such as interrupt number that the PCI equipment that finds and Vendor ID, Device ID, device type, distribution are listed in an interface when starting.
The initialization function first utilizes function pciFindDevice () to find corresponding equipment according to equipment Vendor ID and Device ID, according to Vendor ID, Device ID and identical device serial number (in a system, identical PCI equipment may be arranged), scan bus, find out BUS No, Device No and the Func No at equipment place.Then according to Bus number, device number and function number, call register base address and the interrupt number that pciConfigInLong () and pciConfigInByte () function are determined equipment.Again base address and I/O mask bit phase with obtain internal register base address on real plate.
2, device memory mapping
VxWorks provides the MMU(memory management unit of standard), the user can distribute with MMU the memory headroom of PCI equipment.After clear and definite base address and memory headroom size, call function sysMmuMapAdd () function can be configured to MMU by memory headroom.After having completed the device memory mapping of ADC functional module, can, by the access to device memory, realize the control to equipment.
3, Break Link
In vxworks operating system, use intConnect () link interruption service routine (ISR), but for CPCI equipment, the general pciIntConncet () that adopts articulates interruption, the main difference of it and intConnect () is that the interrupt vector that intConnect () is used monopolizes, and pciIntConncet () can make a plurality of external interrupt share an interrupt vector.PciIntConncet () is defined in pciIntLib.c, should comprise header file pciIntLib.h during use.Should notice that ventor is interrupt vector, need to be by the INUM_TO_IVEC acquisition that converts.
After under the VxWorks system, using pciIntConnect () function to interrupt and specifically c program couples together, this function interrelates the C function of appointment and the interrupt vector of appointment, and the address of function will be stored in this interrupt vector.When an interrupt occurs, system will be called this specific c program function, i.e. interrupt service routine.
The second, the realization of power function interface and encapsulation:
The realization of power function interface
The power function interface is used for realizing the concrete operations to the ADC functional module, and for the operation of ADC functional module, common mainly containing opened, closed, read data and Real-Time Monitoring in place operation.To the major control process of ADC functional module as shown in Figure 2.
The major control process of ADC functional module as shown in Figure 2, at first application program is carried out and is opened the operation of specifying ADC module board, load the driver of ADC module, next step calls the adc data acquisition interface, application program is imported ADC module board number and channel number into, start corresponding ADC passage, start collection signal, it is complete that next step judges whether signal gathers, then read the signal gathered, next step stops the acquisition function of ADC module respective channel, finally closes the board operation, the unloading driver.Above-mentioned is once the operation of complete ADC module collection signal, and application program completes the signals collecting operation of other passages by repeating above step.
Performed operation in A/D functional circuit control procedure, the driving hardware interface register handbook according to the hardware design personnel provide, operate concrete control register, can realize above operation.
According to the common operation that will realize the ADC functional module, the detailed design of each power function interface is as follows:
1, open the ADC functional module, as shown in table 1, the specific implementation flow process of program as shown in Figure 3.
Table 1
At first the ADC module board card number that will open of application passes, in function body, judge whether plate is number correct, if ADC functional module memory-mapped base value correct that obtain after the initialization function is carried out is assigned to a global variable, last function returns to OK, if not being the user, the plate parameter do not allow, the Returning plate mistake.
2, close the ADC functional module, as shown in table 2, the specific implementation process flow diagram of program as shown in Figure 4.
Table 2
At first the appointment ADC module board number that will close of application passes, in function body, whether the plate parameter that judgement is transmitted is correct, if correct, the global variable zero clearing that will preserve memory base address, function returns to OK, if plate card number mistake, Returning plate mistake.
3, the read operation of ADC functional module, as shown in table 3, and the specific implementation process flow diagram of program as shown in Figure 5.
Table 3
At first application passes will be carried out ADC module board number and the channel number parameter of signals collecting, in function body, whether the plate number that first judgement is transmitted is that the user allows the plate number of inputting, if, further whether the channel number of judgement transmission is that the user allows the channel number of inputting again, if, start and specify the dedicated tunnel of ADC module to carry out signals collecting, next step judges whether signal has gathered, if gathered, read the signal of collection, next step reads the correction factor of ADC module, the signal value of collection is converted into to magnitude of voltage and preserves, last function returns to OK, if the process of above-mentioned judgement occurs, according in process flow diagram, carrying out.
4, ADC functional module Real-Time Monitoring, as shown in table 4, and the specific implementation process flow diagram of program as shown in Figure 6.
Table 4
At first application passes is specified ADC functional module plate number, in function body, whether the plate number that judgement is transmitted is the plate number that the user allows, if, next step calls PciFindDevice () function, whether the rreturn value that judges PciFindDevice () function is OK, and if so, function interface returns to OK.If above-mentioned judgement occurs, press the respective operations processing in process flow diagram, explain no longer in detail here.
Performed operation in ADC functional module control procedure, the driving hardware interface register handbook according to the hardware design personnel provide, operate concrete control register, can realize above operation.
Claims (7)
1.VxWorks cpci bus scan A/D C functional module driving arrangement under operating system, it is characterized in that, it comprises FPGA(1), Acquisition Circuit (2), 4 eight path analoging switch (3), isolation modulate circuit (4), cpci bus interface controller (5), configuration circuit (6), configuration feed circuit (7) and cpci bus (8)
The cpci bus FPDP of cpci bus interface controller (5) connects cpci bus (8), the local bus port connection FPGA(1 of cpci bus interface controller (5)) data address bus, the configuration data port of cpci bus interface controller (5) connects the FPDP of configuration circuit (6)
The input end of isolation modulate circuit (4) is 32 road input end of analog signal, 32 signal output parts of isolation modulate circuit (4) are divided into four groups, 8 signal output parts in every group connect respectively eight input end of analog signal of 1 eight path analoging switch (3), 4 analog signal outputs of 4 eight path analoging switch (3) connect respectively 4 input end of analog signal of Acquisition Circuit (2), the digital signal output end connection FPGA(1 of Acquisition Circuit (2)) digital signal input end, FPGA(1) the power supply output terminal for electrical input connection configuration feed circuit (7), FPGA(1) four groups of analog switch control signal output terminals connect respectively the control signal input end of 4 eight path analoging switch (3).
2. cpci bus scan A/D C functional module driving arrangement under vxworks operating system according to claim 1, is characterized in that, described Acquisition Circuit (2) adopts the AD7865 acquisition chip to realize, arrives the conversion of digital quantity be used to realizing analog quantity.
3. cpci bus scan A/D C functional module driving arrangement under vxworks operating system according to claim 1, it is characterized in that, described isolation modulate circuit (4) is 32 tunnel isolation modulate circuits, 32 AD202 isolating chips, consists of, for realizing isolation and the signal condition to simulating signal.
4. cpci bus scan A/D C functional module driving arrangement under vxworks operating system according to claim 1, is characterized in that, described cpci bus interface controller (5) adopts the PCI9054 interface chip to realize.
5. based on the control method of cpci bus scan A/D C functional module driving arrangement under the described vxworks operating system of claim 1, it is characterized in that, the process of this control method is:
Step 1, FPGA(1) FPDP open, the load driver program;
Step 2, FPGA(1) channel number of wanting collection signal is set, start corresponding acquisition channel;
Step 3, Acquisition Circuit (2) start collection signal;
Step 4, FPGA(1) to judge whether signal gathers complete, if it is performs step five, if otherwise return to step 3;
Step 5, FPGA(1) read the signal that Acquisition Circuit (2) gathers;
Step 6, FPGA(1) close FPDP, unload driver.
6. according to claim 5 based on the control method of cpci bus scan A/D C functional module driving arrangement under vxworks operating system, it is characterized in that the described FPGA(1 of step 1) the concrete grammar opened of FPDP be:
Step one by one, FPGA(1) transmit the plate card number of the ADC functional module board that will open;
Step 1 two, FPGA(1) in function body, judge whether the plate card number is correct, if otherwise return to step one by one, if it is perform step one or three;
Step 1 three, ADC functional module memory-mapped base value is assigned to a global variable;
Step 1 four, FPDP have been opened.
7. according to claim 5 based on the control method of cpci bus scan A/D C functional module driving arrangement under vxworks operating system, it is characterized in that the described FPGA(1 of step 6) the FPDP concrete grammar of closing be:
Step 6 one, FPGA(1) transmit the parameter of ADC functional module plate card number;
Step 6 two, FPGA(1) in function body, judge whether plate is number correct, if otherwise return to step 6 one, if it is perform step six or three;
Step 6 three, the global variable zero clearing that will preserve ADC functional module memory-mapped plot;
Step 6 four, FPDP have been closed.
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