CN103401537A - Decision circuit and receiver - Google Patents
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- CN103401537A CN103401537A CN2013103293669A CN201310329366A CN103401537A CN 103401537 A CN103401537 A CN 103401537A CN 2013103293669 A CN2013103293669 A CN 2013103293669A CN 201310329366 A CN201310329366 A CN 201310329366A CN 103401537 A CN103401537 A CN 103401537A
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Abstract
The invention discloses a decision circuit, which comprises a delay circuit, a subtracter circuit and a data recovery circuit, wherein a signal to be decided is delayed from a 1/3 symbol period to a 5/3 symbol period, and then the signal is outputted to the subtracter circuit by the delay circuit; difference comparison is carried out on the decision signal and the delayed signal by the subtracter circuit, so that direct current component in the signal to be decided is eliminated, and the signal in which the direct current component is eliminated is outputted to the data recovery circuit; 1 is outputted by the data recovery circuit when the signal in which the direct current component is eliminated is larger than a first threshold voltage, and 0 is outputted by the data recovery circuit when the signal in which the direct current component is eliminated is less than a second threshold voltage; and when the signal in which the direct current component is eliminated is between the first threshold voltage and the second threshold voltage, keeping the last time output. With the adoption of the decision circuit, the data can be accurately recovered. The invention also discloses a receiver containing the above decision circuit.
Description
Technical Field
The invention belongs to the technical field of signal processing, and particularly relates to a decision circuit and a receiver.
Background
The decision circuit is an important component of the receiver, and is used for comparing an analog signal processed by a front end of the receiver with a reference voltage to output a digital signal.
In practical applications, a signal to be determined of the determination circuit often has a dc component due to frequency offset between a carrier and a local frequency, signal distortion during transmission, mismatch between components, and channel interference. When a direct current component exists in a signal to be judged, the judgment circuit can be misjudged.
How to eliminate the influence of the dc component in the signal to be determined and accurately recover the data is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a decision circuit, which can eliminate the influence of the dc component in the signal to be decided, so as to accurately recover data.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention discloses a decision circuit, which is applied to a receiver and comprises a delay circuit, a subtracter circuit and a data recovery circuit;
the input end of the delay circuit is connected with a signal to be judged, the output end of the delay circuit is connected to one input end of the subtracter circuit, the delay circuit delays the signal to be judged for a preset time and outputs the signal to be judged to the subtracter circuit, the preset time is T/3-5T/3, and T is a symbol period of the signal to be judged;
the other input end of the subtractor circuit is connected to the signal to be judged, the subtractor circuit carries out differential comparison on the signal to be judged and the delayed signal, eliminates a direct current component in the signal to be judged, and outputs a signal with the direct current component eliminated to the data recovery circuit;
the data recovery circuit outputs 1 when the signal for canceling the direct current component is greater than a first threshold voltage, outputs 0 when the signal for canceling the direct current component is less than a second threshold voltage, and maintains the previous output when the signal for canceling the direct current component is between the first threshold voltage and the second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.
Preferably, in the above decision circuit, the delay circuit includes N +1 sampling branches and a buffer, where N ≧ M, N and M are integers,t is the period of the sampling clock;
the N +1 sampling branches are connected in parallel, the input ends of the N +1 sampling branches are simultaneously connected with a signal to be judged, the output ends of the N +1 sampling branches are simultaneously connected with the input end of the buffer, and the output end of the buffer is connected with the inverting input end of the subtracter circuit;
the sampling branch circuit comprises a first switch tube, a second switch tube and a capacitor, the input end of the first switch tube is connected to a signal to be judged, the output end of the second switch tube is connected to the input end of the buffer, and the output end of the first switch tube and the input end of the second switch tube are grounded through the capacitor.
Preferably, in the decision circuit, the subtractor circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the signal to be judged is connected to the positive phase input end of the operational amplifier through the first resistor, the output end of the buffer is connected to the negative phase input end of the operational amplifier through the third resistor, the second resistor is connected between the positive phase input end and the negative phase output end of the operational amplifier, and the fourth resistor is connected between the negative phase input end and the positive phase output end of the operational amplifier.
Preferably, in the decision circuit, the data recovery circuit includes a first comparator, a second comparator and an RS flip-flop;
the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the inverting output end of the operational amplifier;
a positive phase input end of the second comparator is connected to the second threshold voltage, and an inverted phase input end of the second comparator is connected with an inverted phase output end of the operational amplifier;
and the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the Q end of the RS trigger is a digital signal output end of the decision circuit.
Preferably, in the decision circuit, the data recovery circuit includes a first comparator, a second comparator and an RS flip-flop;
the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the non-inverting output end of the operational amplifier;
the positive phase input end of the second comparator is connected to the second threshold voltage, and the negative phase input end of the second comparator is connected with the positive phase output end of the operational amplifier;
the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the RS trigger
The terminal is the digital signal output terminal of the decision circuit.
Preferably, in the decision circuit, the on-time of the switching tube in the N +1 sampling branches coincides with the period of the sampling clock, the driving signal of the first switching tube in the sampling branch 0 to the sampling branch N is sequentially delayed by one on-time, and the driving signal of the second switching tube in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube in the current sampling branch.
The invention also discloses a receiver which comprises an antenna, an amplifier, a filter, a mixer, a demodulator and any one of the decision circuits.
Therefore, the beneficial effects of the invention are as follows: the invention discloses a decision circuit which comprises a delay circuit, a subtracter circuit and a data recovery circuit, wherein 1/3 symbol periods are delayed to 5/3 symbol periods by the delay circuit, and then the subtracter circuit carries out differential comparison on a signal Vin to be decided and a delayed signal, so that a direct current component in the signal Vin to be decided can be eliminated, and the data recovery circuit can accurately recover data.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a decision circuit disclosed in the present invention;
FIG. 2 is a schematic diagram of another decision circuit disclosed in the present invention;
FIG. 3 is a schematic diagram of a waveform of a signal to be determined;
FIG. 4 is a schematic diagram of driving signals for the switching transistors of the delay circuit of the decision circuit of FIG. 2;
FIG. 5 is a functional diagram of a data recovery circuit in the decision circuit of FIG. 2;
FIG. 6 is a schematic diagram of another decision circuit disclosed in the present invention;
fig. 7 is a schematic structural diagram of a receiver according to the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention discloses a decision circuit which can eliminate the influence of direct current components in a signal to be decided so as to accurately recover data.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100, a subtractor circuit 200, and a data recovery circuit 300.
Wherein:
the input end of the delay circuit 100 is connected to a signal Vin to be determined, the output end of the delay circuit 100 is connected to one input end of the subtractor circuit 200, the delay circuit 100 delays the signal Vin to be determined for a preset time and outputs the delayed signal Vin to the subtractor circuit 200, wherein the preset time is T/3 to 5T/3, and T is a symbol period of the signal to be determined.
One input end of the subtractor circuit 200 is connected to the delayed signal, and the other input end is connected to the signal Vin to be determined, and the subtractor circuit 200 performs differential comparison between the signal Vin to be determined and the delayed signal, so as to eliminate a direct current component in the signal Vin to be determined, and output a signal with the direct current component eliminated to the data recovery circuit 300.
The data recovery circuit 300 outputs 1 when the signal for removing the dc component is greater than the first threshold voltage, outputs 0 when the signal for removing the dc component is less than the second threshold voltage, and maintains the previous output when the signal for removing the dc component is between the first threshold voltage and the second threshold voltage, where the first threshold voltage is greater than the second threshold voltage.
The decision circuit disclosed by the invention comprises a delay circuit 100, a subtracter circuit 200 and a data recovery circuit 300, wherein firstly, a signal Vin to be decided is delayed from 1/3 symbol periods to 5/3 symbol periods by the delay circuit 100, and then the subtracter circuit 200 performs differential comparison on the signal Vin to be decided and the delayed signal, so that the direct current component in the signal Vin to be decided can be eliminated, and the data recovery circuit 300 can accurately recover data.
A more specific example is described below.
Referring to fig. 2, fig. 2 is a schematic diagram of another decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100, a subtractor circuit 200, and a data recovery circuit 300.
Wherein:
In the application process, by applying the corresponding driving signal to each switch tube in the delay circuit 100, it can be ensured that the delay circuit 100 delays the signal to be decided by 1/3 symbol periods to 5/3 symbol periods. Specifically, the on time T of each switching tube in the N +1 sampling branches is set to be consistent with the period of the sampling clock CLK, the driving signal from the sampling branch 0 to the first switching tube Q1 in the sampling branch N is sequentially delayed by one on time T, and the driving signal of the second switching tube Q2 in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube Q1 in the sampling branch. It should be noted that the delay time of the driving signal of the second switching tube Q2 in each sampling branch relative to the driving signal of the first switching tube Q1 in the present sampling branch is the same.
The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The signal Vin to be judged is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the output terminal of the buffer 101 is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, the second resistor R2 is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier U1, and the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.
The signal Vin to be judged is in the form of Vdc+Vac(DC and AC) as shown in FIG. 3. Due to various factors (such as frequency offset between carrier and local frequency in FSK modulation and demodulation, mismatch of each component, and interference of channel between each demodulated signal, etc.), V may be causeddcThe offset varies, causing a deviation in the data decision.
The subtracter has the following functions:
Vsub＝Vin-Vdelay=(Vdc，in+Vac，in)-(Vdc，delay+Vac，delay)=Vac，in-Vac，delayto eliminate the effect of the dc component.
The data recovery circuit 300 includes a first comparator COM1, a second comparator COM2, and an RS flip-flop 301. An inverting input terminal of the first comparator COM1 is connected to the first threshold voltage Vh, and a non-inverting input terminal thereof is connected to an inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM2 is connected to the second threshold voltage Vl, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The S end of the RS trigger 301 is connected with the output end of the first comparator COM1, the R end is connected with the output end of the second comparator COM2, and the Q end of the RS trigger is the digital signal output end of the decision circuit.
The operation of the decision circuit shown in fig. 2 will be described with reference to the driving signals of the respective switching tubes shown in fig. 4.
In the delay circuit 100, the control terminals of the first switch transistors Q1 in the sampling branch 0 to N respectively apply the driving signals P0 to Pn, that is, the control terminal of the first switch transistor Q1 in the sampling branch 0 applies the driving signal P0, the control terminal of the first switch transistor Q1 in the sampling branch 1 applies the driving signal P1, and so on, the control terminal of the first switch transistor Q1 in the sampling branch N-1 applies the driving signal Pn-1, and the control terminal of the first switch transistor Q1 in the sampling branch N applies the driving signal Pn. In addition, the control terminal of the second switch tube Q2 in the sampling branch 0 applies the driving signal Pn, the control terminals of the second switch tubes Q2 in the sampling branch 1 to N respectively apply the driving signals P0 to Pn-1, that is, the control terminal of the second switch tube Q2 in the sampling branch 1 applies the driving signal P0, the control terminal of the second switch tube Q2 in the sampling branch 2 applies the driving signal P1, and so on, the control terminal of the second switch tube Q2 in the sampling branch N-1 applies the driving signal Pn-2, and the control terminal of the second switch tube Q2 in the sampling branch N applies the driving signal Pn-1. That is, the second switch Q2 in each sampling circuit is turned on with a delay of N/N +1 symbol periods with respect to the first switch Q1 in the present sampling branch.
The delay process of each sampling circuit is described by taking sampling branch 0 as an example. The signal Vin to be judged is input from the node a, passes through the node b and reaches the node c. When the driving signal P0 controls the first switch Q1 to be turned on, the second switch Q2 is turned off, and the signal to be determined Vin charges the capacitor C, that is, the capacitor C samples the tape determination signal Vin, and the voltages at the node b and the node a are the same. When the first switching tube Q1 is turned off, the voltage at the node b remains unchanged. When the driving signal Pn controls the second switch Q2 to be turned on, the voltage at the node c and the voltage at the node b are the same, and the voltage at the node c is transmitted to the buffer 101 and finally to the subtractor circuit 200. When the second switch Q2 is turned off, the first switch Q1 is turned on, and the next cycle is entered. It can be seen that the signal to be decided is delayed by N/N +1 symbol periods.
The voltages output by the N +1 sampling branches in the delay circuit 100 are discrete and may be accompanied by glitches, and the buffer 101 may perform filtering integration on the delayed signal and perform current isolation at the same time, so as to avoid the current of the delayed signal from influencing the current in the subtractor circuit 200.
The signal Vin to be decided is transmitted to the non-inverting input terminal of the operational amplifier U1, the delayed signal is transmitted to the inverting input terminal of the operational amplifier U1, the operational amplifier U1 performs differential comparison between the two, and outputs a signal from which the dc component is removed at the inverting output terminal thereof and an inverted signal from which the dc component is removed at the non-inverting output terminal thereof.
Then, the signal from which the dc component is removed is supplied to the non-inverting input terminal of the first comparator COM1 and the inverting input terminal of the second comparator COM2, respectively, the inverting input terminal of the first comparator COM1 is connected to the first threshold voltage Vh, the non-inverting input terminal of the second comparator COM2 is connected to the second threshold voltage Vl, and the first threshold voltage Vh is greater than the second threshold voltage Vl. The output end of the first comparator COM1 is connected to the S end of the RS flip-flop 301, and the output end of the second comparator COM2 is connected to the R end of the RS flip-flop 301.
The function of the data recovery circuit 300 is shown in fig. 5.
When the signal from which the dc component is removed is greater than the first threshold voltage Vh, the first comparator COM1 outputs a high level, which may be regarded as "1", and the second comparator COM2 outputs a low level, which may be regarded as "0", at which time the Q terminal of the RS flip-flop 301 outputs a high level, which may be regarded as "1". When the signal from which the dc component is removed is less than the second threshold voltage Vl, the first comparator COM1 outputs a low level, which may be regarded as "0", and the second comparator COM2 outputs a high level, which may be regarded as "1", at which time the Q terminal of the RS flip-flop 301 outputs a low level, which may be regarded as "0". When the signal from which the direct current component is eliminated is smaller than the first threshold voltage Vh and larger than the second threshold voltage Vl, the output result remains unchanged. The Q terminal of the RS flip-flop 301 serves as the digital signal output terminal of the entire decision circuit.
Fig. 2 shows only one specific structure of the decision circuit, and the decision circuit may be implemented in other structures. Referring to fig. 6, fig. 6 is a schematic diagram of another decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100, a subtractor circuit 200, and a data recovery circuit 300. The structure of the delay circuit 100 is shown in fig. 2, and is not described herein again.
The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The signal Vin to be judged is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the output terminal of the buffer 101 is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, the second resistor R2 is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier U1, and the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.
The data recovery circuit 300 includes a first comparator COM3, a second comparator COM4, and an RS flip-flop 301. An inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and a non-inverting input terminal thereof is connected to a non-inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage Vl, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The RS flip-flop 301 has an S terminal connected to the output terminal of the first comparator COM1 and an R terminal connected to the output terminal of the second comparator COM2, and
the terminal is a digital signal output terminal of the decision circuit.
In an implementation, the subtractor circuit 200 and the data recovery circuit 300 may also adopt other connection modes.
For example: the subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The output end of the buffer 101 is connected to the positive phase input end of the operational amplifier U1 through a first resistor R1, the signal to be judged Vin is connected to the negative phase input end of the operational amplifier U1 through a third resistor R3, the second resistor R2 is connected between the positive phase input end and the negative phase output end of the operational amplifier U1, and the fourth resistor R4 is connected between the negative phase input end and the positive phase output end of the operational amplifier U1.
The data recovery circuit 300 includes a first comparator COM3, a second comparator COM4, and an RS flip-flop 301. An inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and a non-inverting input terminal thereof is connected to an inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage Vl, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The RS flip-flop 301 has an S terminal connected to the output terminal of the first comparator COM1 and an R terminal connected to the output terminal of the second comparator COM2, and
the terminal is a digital signal output terminal of the decision circuit.
Or,
the subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The output end of the buffer 101 is connected to the positive phase input end of the operational amplifier U1 through a first resistor R1, the signal to be judged Vin is connected to the negative phase input end of the operational amplifier U1 through a third resistor R3, the second resistor R2 is connected between the positive phase input end and the negative phase output end of the operational amplifier U1, and the fourth resistor R4 is connected between the negative phase input end and the positive phase output end of the operational amplifier U1.
The data recovery circuit 300 includes a first comparator COM3, a second comparator COM4, and an RS flip-flop 301. An inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and a non-inverting input terminal thereof is connected to a non-inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage Vl, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The S end of the RS trigger 301 is connected with the output end of the first comparator COM1, the R end is connected with the output end of the second comparator COM2, and the Q end of the RS trigger is the digital signal output end of the decision circuit.
The invention discloses a decision circuit applied to a receiver and also discloses a receiver with the decision circuit. The receiver is constructed as shown in fig. 7, and includes an antenna 1, an amplifier 2, a filter 3, a demodulator 4, and a decision circuit 5 disclosed above in the present invention. The receiver disclosed by the invention can accurately recover data through the decision circuit 5 after demodulating the received signal into an analog signal.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A decision circuit for use in a receiver, wherein the decision circuit comprises a delay circuit, a subtractor circuit, and a data recovery circuit;
the input end of the delay circuit is connected with a signal to be judged, the output end of the delay circuit is connected to one input end of the subtracter circuit, the delay circuit delays the signal to be judged for a preset time and outputs the signal to be judged to the subtracter circuit, the preset time is T/3-5T/3, and T is a symbol period of the signal to be judged;
the other input end of the subtractor circuit is connected to the signal to be judged, the subtractor circuit carries out differential comparison on the signal to be judged and the delayed signal, eliminates a direct current component in the signal to be judged, and outputs a signal with the direct current component eliminated to the data recovery circuit;
the data recovery circuit outputs 1 when the signal for canceling the direct current component is greater than a first threshold voltage, outputs 0 when the signal for canceling the direct current component is less than a second threshold voltage, and maintains the previous output when the signal for canceling the direct current component is between the first threshold voltage and the second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.
2. The decision circuit of claim 1, wherein the delay circuit comprises N +1 sampling branches and a buffer, wherein N ≧ M, N and M are integers,
t is the period of the sampling clock;
the N +1 sampling branches are connected in parallel, the input ends of the N +1 sampling branches are simultaneously connected with a signal to be judged, the output ends of the N +1 sampling branches are simultaneously connected with the input end of the buffer, and the output end of the buffer is connected with the inverting input end of the subtracter circuit;
the sampling branch circuit comprises a first switch tube, a second switch tube and a capacitor, the input end of the first switch tube is connected to a signal to be judged, the output end of the second switch tube is connected to the input end of the buffer, and the output end of the first switch tube and the input end of the second switch tube are grounded through the capacitor.
3. The decision circuit of claim 2, wherein the subtractor circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the signal to be judged is connected to the positive phase input end of the operational amplifier through the first resistor, the output end of the buffer is connected to the negative phase input end of the operational amplifier through the third resistor, the second resistor is connected between the positive phase input end and the negative phase output end of the operational amplifier, and the fourth resistor is connected between the negative phase input end and the positive phase output end of the operational amplifier.
4. The decision circuit of claim 3, wherein the data recovery circuit comprises a first comparator, a second comparator, and an RS flip-flop;
the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the inverting output end of the operational amplifier;
a positive phase input end of the second comparator is connected to the second threshold voltage, and an inverted phase input end of the second comparator is connected with an inverted phase output end of the operational amplifier;
and the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the Q end of the RS trigger is a digital signal output end of the decision circuit.
5. The decision circuit of claim 3, wherein the data recovery circuit comprises a first comparator, a second comparator, and an RS flip-flop;
the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the non-inverting output end of the operational amplifier;
the positive phase input end of the second comparator is connected to the second threshold voltage, and the negative phase input end of the second comparator is connected with the positive phase output end of the operational amplifier;
the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the RS trigger
The terminal is the digital signal output terminal of the decision circuit.
6. The decision circuit according to claim 2, wherein the on-time of the switching tube in the N +1 sampling branches coincides with the period of the sampling clock, the driving signal from the sampling branch 0 to the first switching tube in the sampling branch N is sequentially delayed by one on-time, and the driving signal of the second switching tube in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube in the current sampling branch.
7. A receiver comprising an antenna, an amplifier, a filter, a mixer, a demodulator and a decision circuit, characterized in that the decision circuit is a decision circuit as claimed in any one of claims 1 to 6.
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| US10797853B2 (en) | 2018-12-29 | 2020-10-06 | Amlogic (Shanghai) Co., Ltd. | High-speed decision device |
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| US20070293180A1 (en) * | 2006-06-14 | 2007-12-20 | Freescale Semiconductor, Inc. | DC offset correction for direct conversion receivers |
| CN101567868A (en) * | 2008-04-25 | 2009-10-28 | 中兴通讯股份有限公司 | Decimal frequency deviation estimation method of CMMB cellphone television |
| CN102468865A (en) * | 2010-11-18 | 2012-05-23 | 中兴通讯股份有限公司 | Method and device of cell search coarse synchronization |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10797853B2 (en) | 2018-12-29 | 2020-10-06 | Amlogic (Shanghai) Co., Ltd. | High-speed decision device |
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| CN103401537B (en) | 2016-06-22 |
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