CN103401537A - Decision circuit and receiver - Google Patents

Abstract

The invention discloses a decision circuit, which comprises a delay circuit, a subtracter circuit and a data recovery circuit, wherein a signal to be decided is delayed from a 1/3 symbol period to a 5/3 symbol period, and then the signal is outputted to the subtracter circuit by the delay circuit; difference comparison is carried out on the decision signal and the delayed signal by the subtracter circuit, so that direct current component in the signal to be decided is eliminated, and the signal in which the direct current component is eliminated is outputted to the data recovery circuit; 1 is outputted by the data recovery circuit when the signal in which the direct current component is eliminated is larger than a first threshold voltage, and 0 is outputted by the data recovery circuit when the signal in which the direct current component is eliminated is less than a second threshold voltage; and when the signal in which the direct current component is eliminated is between the first threshold voltage and the second threshold voltage, keeping the last time output. With the adoption of the decision circuit, the data can be accurately recovered. The invention also discloses a receiver containing the above decision circuit.

Description

A decision circuit and receiver

technical field

The invention belongs to the technical field of signal processing, and in particular relates to a decision circuit and a receiver.

Background technique

The decision circuit is an important part of the receiver, which is used to compare the analog signal processed by the front end of the receiver with the reference voltage to output a digital signal.

In practical applications, there is often a DC component in the signal to be decided by the decision circuit due to the frequency offset between the carrier and the local frequency, signal distortion during transmission, mismatch between various components, and channel interference. When there is a DC component in the signal to be judged, it will cause misjudgment in the judgment circuit.

How to eliminate the influence of the DC component in the signal to be decided and restore the data accurately is a problem to be solved urgently by those skilled in the art.

Contents of the invention

In view of this, the object of the present invention is to provide a decision circuit, which can eliminate the influence of the DC component in the signal to be decided, so as to recover data accurately.

To achieve the above object, the present invention provides the following technical solutions:

The invention discloses a judgment circuit, which is applied in a receiver, and the judgment circuit includes a delay circuit, a subtractor circuit and a data recovery circuit;

The input end of the delay circuit is connected to the signal to be decided, and the output end is connected to an input end of the subtracter circuit, and the delay circuit delays the signal to be decided for a preset time and outputs it to the subtracter circuit, The preset time is T/3 to 5T/3, where T is the symbol period of the signal to be decided;

The other input end of the subtractor circuit is connected to the signal to be decided, and the subtracter circuit performs a differential comparison between the signal to be decided and the delayed signal to eliminate the DC component in the signal to be decided, outputting a signal for eliminating the DC component to the data recovery circuit;

The data recovery circuit outputs 1 when the signal with the eliminated DC component is greater than the first threshold voltage, outputs 0 when the signal with the eliminated DC component is lower than the second threshold voltage, and outputs 0 when the signal with the eliminated DC component is in the When the voltage is between the first threshold voltage and the second threshold voltage, the last output is maintained, wherein the first threshold voltage is greater than the second threshold voltage.

Preferably, in the above decision circuit, the delay circuit includes N+1 sampling branches and buffers, where N≥M, N and M are integers, , t is the period of the sampling clock;

The N+1 sampling branches are connected in parallel, the input ends of the N+1 sampling branches are simultaneously connected to the signal to be decided, and the output ends of the N+1 sampling branches are simultaneously connected to the input end of the buffer, and the the output of the buffer is connected to the inverting input of the subtractor circuit;

The sampling branch includes a first switch tube, a second switch tube and a capacitor, the input end of the first switch tube is connected to the signal to be determined, and the output end of the second switch tube is connected to the input of the buffer end, the output end of the first switch tube and the input end of the second switch tube are grounded through the capacitor.

Preferably, in the above decision circuit, the subtractor circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor;

The signal to be decided is connected to the non-inverting input terminal of the operational amplifier through the first resistor, the output terminal of the buffer is connected to the inverting input terminal of the operational amplifier through the third resistor, and the The second resistor is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier, and the fourth resistor is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier.

Preferably, in the above decision circuit, the data recovery circuit includes a first comparator, a second comparator and an RS flip-flop;

The inverting input terminal of the first comparator is connected to the first threshold voltage, and the non-inverting input terminal is connected to the inverting output terminal of the operational amplifier;

The non-inverting input terminal of the second comparator is connected to the second threshold voltage, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier;

The S end of the RS flip-flop is connected to the output end of the first comparator, the R end is connected to the output end of the second comparator, and the Q end of the RS flip-flop is the digital signal of the decision circuit output.

Preferably, in the above decision circuit, the data recovery circuit includes a first comparator, a second comparator and an RS flip-flop;

The inverting input terminal of the first comparator is connected to the first threshold voltage, and the non-inverting input terminal is connected to the non-inverting output terminal of the operational amplifier;

The non-inverting input terminal of the second comparator is connected to the second threshold voltage, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier;

端为所述判决电路的数字信号输出端。The S end of the RS flip-flop is connected to the output end of the first comparator, the R end is connected to the output end of the second comparator, and the RS flip-flop

The terminal is the digital signal output terminal of the decision circuit.

Preferably, in the above decision circuit, the turn-on time of the switches in the N+1 sampling branches is consistent with the period of the sampling clock, and the driving signal from the sampling branch 0 to the first switching tube in the sampling branch N A turn-on time is sequentially delayed, and the driving signal of the second switching tube in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube in this sampling branch.

The invention also discloses a receiver, which includes an antenna, an amplifier, a filter, a mixer, a demodulator and any one of the above decision circuits.

It can be seen that the beneficial effect of the present invention is: the decision circuit disclosed by the present invention includes a delay circuit, a subtractor circuit and a data recovery circuit, and first uses the delay circuit to delay the signal Vin to be decided by 1/3 symbol period to 5/3 The symbol period, and then the subtractor circuit performs a differential comparison between the signal to be decided Vin and the delayed signal, so as to eliminate the DC component in the signal to be decided Vin, thereby ensuring that the data recovery circuit can recover data accurately.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic structural diagram of a decision circuit disclosed by the present invention;

FIG. 2 is a schematic structural diagram of another decision circuit disclosed by the present invention;

Fig. 3 is the schematic diagram of the waveform of the signal to be judged;

Fig. 4 is a kind of schematic diagram of the driving signals of each switching tube of the delay circuit in the decision circuit shown in Fig. 2;

Fig. 5 is the functional schematic diagram of the data recovery circuit in the judgment circuit shown in Fig. 2;

FIG. 6 is a schematic structural diagram of another decision circuit disclosed in the present invention;

Fig. 7 is a schematic structural diagram of a receiver disclosed in the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The invention discloses a judgment circuit, which can eliminate the influence of the direct current component in the signal to be judged, thereby recovering data accurately.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100 , a subtractor circuit 200 and a data recovery circuit 300 .

in:

The input end of the delay circuit 100 is connected to the signal Vin to be decided, the output end of the delay circuit 100 is connected to an input end of the subtracter circuit 200, and the delay circuit 100 delays the signal Vin to be decided for a preset time and outputs it to the subtracter circuit 200, The preset time is T/3 to 5T/3, where T is the symbol period of the signal to be decided.

One input terminal of the subtractor circuit 200 is connected to the delayed signal, and the other input terminal is connected to the signal Vin to be decided. The subtractor circuit 200 performs a differential comparison between the signal Vin to be decided and the delayed signal, thereby eliminating the signal to be decided. The DC component in Vin is output to the data recovery circuit 300 by eliminating the DC component.

The data recovery circuit 300 outputs 1 when the signal of eliminating the DC component is greater than the first threshold voltage, outputs 0 when the signal of eliminating the DC component is smaller than the second threshold voltage, and outputs 0 when the signal of eliminating the DC component is between the first threshold voltage and the second threshold voltage In between, the last output is maintained, wherein the first threshold voltage is greater than the second threshold voltage.

The decision circuit disclosed in the present invention includes a delay circuit 100, a subtractor circuit 200 and a data recovery circuit 300. First, the delay circuit 100 is used to delay the signal Vin to be decided by 1/3 symbol period to 5/3 symbol period, and then the subtractor circuit 200 treats By performing a differential comparison between the decision signal Vin and the delayed signal, the DC component in the signal to be decided Vin can be eliminated, thereby ensuring that the data recovery circuit 300 can recover data accurately.

The following will be described in conjunction with a more specific embodiment.

Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of another decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100 , a subtractor circuit 200 and a data restoration circuit 300 .

in:

，T为待判决信号的符号周期，t为采样时钟的周期。N+1个采样支路并联连接，N+1个采样支路的输入端同时接入待判决信号Vin，N+1个采样支路的输出端同时连接至缓冲器101的输入端，缓冲器101的输出端连接至减法器电路200的反相输入端。每个采样支路包括第一开关管Q1、第二开关管Q2和电容C，第一开关管Q1的输入端接入待判决信号Vin，第二开关管Q2的输出端连接至缓冲器101的输入端，第一开关管Q1的输出端和第二开关管Q2的输入端通过电容C接地。The delay circuit 100 includes N+1 sampling branches (that is, sampling branch 0 to sampling branch N) and a buffer 101, where N≥M, N and M are integers,

, T is the symbol period of the signal to be decided, and t is the period of the sampling clock. The N+1 sampling branches are connected in parallel, the input ends of the N+1 sampling branches are simultaneously connected to the signal Vin to be decided, and the output ends of the N+1 sampling branches are simultaneously connected to the input end of the buffer 101, and the buffer The output terminal of 101 is connected to the inverting input terminal of the subtractor circuit 200 . Each sampling branch includes a first switching tube Q1, a second switching tube Q2 and a capacitor C, the input terminal of the first switching tube Q1 is connected to the signal Vin to be decided, and the output terminal of the second switching tube Q2 is connected to the buffer 101 The input terminal, the output terminal of the first switching transistor Q1 and the input terminal of the second switching transistor Q2 are grounded through the capacitor C.

In the application process, by applying corresponding driving signals to each switch tube in the delay circuit 100, it can be ensured that the delay circuit 100 delays the signal to be decided by 1/3 symbol period to 5/3 symbol period. Specifically, the turn-on time t of each switch tube in the N+1 sampling branches is set to be consistent with the period of the sampling clock CLK, and the driving signal from the sampling branch 0 to the first switching tube Q1 in the sampling branch N is delayed by one The turn-on time is t, and the driving signal of the second switching tube Q2 in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube Q1 in this sampling branch. It should be noted that the delay time of the driving signal of the second switching transistor Q2 in each sampling branch relative to the driving signal of the first switching transistor Q1 in this sampling branch is the same.

The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The signal Vin to be decided is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the output terminal of the buffer 101 is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

The form of the signal Vin to be judged is V _dc +V _ac (direct current and alternating current), as shown in FIG. 3 . Due to the influence of various factors (such as the frequency offset between the carrier and local frequency in FSK modulation and demodulation, the mismatch of various components, and the interference of channels between various demodulated signals, etc.), the V _dc offset may change, As a result, data judgments are biased.

The functions to be implemented by the subtractor are:

V _sub =V _in -V _delay =(V _dc,in +V _ac,in )-(V _dc,delay +V _ac,delay )=V _ac,in -V _ac,delay to eliminate the influence of the DC component.

The data recovery circuit 300 includes a first comparator COM1 , a second comparator COM2 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM1 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM2 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The S terminal of the RS flip-flop 301 is connected to the output terminal of the first comparator COM1, the R terminal is connected to the output terminal of the second comparator COM2, and the Q terminal of the RS flip-flop is the digital signal output terminal of the decision circuit.

The operation process of the decision circuit shown in FIG. 2 will be described below in conjunction with the driving signals of each switch tube shown in FIG. 4 .

In the delay circuit 100, the control terminals of the first switching tube Q1 in the sampling branch 0 to the sampling branch N are respectively applied with driving signals P0 to Pn, that is, the control terminal of the first switching tube Q1 in the sampling branch 0 is applied Drive signal P0, the control terminal of the first switching tube Q1 in the sampling branch 1 applies the driving signal P1, and so on, the control terminal of the first switching tube Q1 in the sampling branch N-1 applies the driving signal Pn-1, A driving signal Pn is applied to the control terminal of the first switching transistor Q1 in the sampling branch N. In addition, the control terminal of the second switching transistor Q2 in the sampling branch 0 is applied with the driving signal Pn, and the control terminals of the second switching transistor Q2 in the sampling branch 1 to the sampling branch N are respectively applied with the driving signals P0 to Pn-1, That is, the control terminal of the second switching tube Q2 in the sampling branch 1 applies the driving signal P0, and the control terminal of the second switching tube Q2 in the sampling branch 2 applies the driving signal P1, and so on, the sampling branch N-1 The driving signal Pn-2 is applied to the control end of the second switching transistor Q2 in the sampling branch N, and the driving signal Pn-1 is applied to the control end of the second switching transistor Q2 in the sampling branch N. That is, the second switching tube Q2 in each sampling circuit is turned on with a delay of N/N+1 symbol periods relative to the first switching tube Q1 in the sampling branch.

Taking the sampling branch 0 as an example, the delay process of each sampling circuit is described. The signal Vin to be decided is input from node a, then passes through node b, and reaches node c. When the drive signal P0 controls the first switch tube Q1 to be turned on, the second switch tube Q2 is turned off, and the pending decision signal Vin charges the capacitor C, that is, the capacitor C samples the judgment signal Vin, at this time the node The voltage at node b and a is the same. After the first switch tube Q1 is turned off, the voltage at node b remains unchanged. When the driving signal Pn controls the second switching transistor Q2 to turn on, the voltage on the node c is the same as the voltage on the node b, and the voltage on the node c is transmitted to the buffer 101 and finally transmitted to the subtractor circuit 200 . After the second switching tube Q2 is turned off, the first switching tube Q1 is turned on and enters the next cycle. It can be seen that the signal to be decided is delayed by N/N+1 symbol periods.

The voltages output by the N+1 sampling branches in the delay circuit 100 are discrete and may be accompanied by glitches. The buffer 101 can filter and integrate the delayed signal, and can also perform current isolation to avoid the delay of the delayed signal. The current interacts with the current in the subtractor circuit 200 .

The signal Vin to be judged is transmitted to the non-inverting input terminal of the operational amplifier U1, and the delayed signal is transmitted to the inverting input terminal of the operational amplifier U1. The signal with the DC component removed, and the inversion signal of the signal with the DC component eliminated is output at the non-inverting output terminal.

After that, the signal with the DC component eliminated is sent to the non-inverting input terminal of the first comparator COM1 and the inverting input terminal of the second comparator COM2 respectively, and the inverting input terminal of the first comparator COM1 is connected to the first threshold voltage Vh, the non-inverting input terminal of the second comparator COM2 is connected to the second threshold voltage Vl, and the first threshold voltage Vh is greater than the second threshold voltage Vl. The output terminal of the first comparator COM1 is connected to the S terminal of the RS flip-flop 301 , and the output terminal of the second comparator COM2 is connected to the R terminal of the RS flip-flop 301 .

The function of the data recovery circuit 300 is shown in FIG. 5 .

When the signal with the DC component eliminated is greater than the first threshold voltage Vh, the first comparator COM1 outputs a high level, which can be regarded as "1", and the second comparator COM2 outputs a low level, which can be regarded as "0". At this time, the Q terminal of the RS flip-flop 301 outputs a high level, which can be regarded as "1". When the signal with the DC component eliminated is less than the second threshold voltage V1, the first comparator COM1 outputs a low level, which can be regarded as "0", and the second comparator COM2 outputs a high level, which can be regarded as "1". At this time, the Q terminal of the RS flip-flop 301 outputs a low level, which can be regarded as "0". When the signal with the DC component eliminated is less than the first threshold voltage Vh and greater than the second threshold voltage Vl, the output result remains unchanged. The Q terminal of the RS flip-flop 301 serves as the digital signal output terminal of the entire decision circuit.

FIG. 2 only shows a relatively specific structure of the decision circuit, and the decision circuit can also be implemented with other structures. Referring to FIG. 6, FIG. 6 is a schematic structural diagram of another decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100 , a subtractor circuit 200 and a data recovery circuit 300 . Wherein, the structure of the delay circuit 100 is shown in FIG. 2 , which will not be repeated here.

The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The signal Vin to be decided is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the output terminal of the buffer 101 is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

端为判决电路的数字信号输出端。The data recovery circuit 300 includes a first comparator COM3 , a second comparator COM4 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The S end of the RS flip-flop 301 is connected to the output end of the first comparator COM1, the R end is connected to the output end of the second comparator COM2, and the RS flip-flop

The terminal is the digital signal output terminal of the decision circuit.

In implementation, the subtracter circuit 200 and the data restoration circuit 300 may also adopt other connection manners.

For example: the subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The output terminal of the buffer 101 is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the signal Vin to be judged is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

端为判决电路的数字信号输出端。The data recovery circuit 300 includes a first comparator COM3 , a second comparator COM4 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The S end of the RS flip-flop 301 is connected to the output end of the first comparator COM1, the R end is connected to the output end of the second comparator COM2, and the RS flip-flop

The terminal is the digital signal output terminal of the decision circuit.

or,

The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The output terminal of the buffer 101 is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the signal Vin to be judged is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

The data recovery circuit 300 includes a first comparator COM3 , a second comparator COM4 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The S terminal of the RS flip-flop 301 is connected to the output terminal of the first comparator COM1, the R terminal is connected to the output terminal of the second comparator COM2, and the Q terminal of the RS flip-flop is the digital signal output terminal of the decision circuit.

The invention above discloses a decision circuit applied to a receiver, and the invention also discloses a receiver with the decision circuit. The structure of the receiver is shown in FIG. 7, including an antenna 1, an amplifier 2, a filter 3, a demodulator 4 and the decision circuit 5 disclosed above in the present invention. After the receiver disclosed in the present invention demodulates the received signal into an analog signal, the data can be recovered accurately through the decision circuit 5 .

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A decision circuit for use in a receiver, wherein the decision circuit comprises a delay circuit, a subtractor circuit, and a data recovery circuit;

the input end of the delay circuit is connected with a signal to be judged, the output end of the delay circuit is connected to one input end of the subtracter circuit, the delay circuit delays the signal to be judged for a preset time and outputs the signal to be judged to the subtracter circuit, the preset time is T/3-5T/3, and T is a symbol period of the signal to be judged;

the other input end of the subtractor circuit is connected to the signal to be judged, the subtractor circuit carries out differential comparison on the signal to be judged and the delayed signal, eliminates a direct current component in the signal to be judged, and outputs a signal with the direct current component eliminated to the data recovery circuit;

the data recovery circuit outputs 1 when the signal for canceling the direct current component is greater than a first threshold voltage, outputs 0 when the signal for canceling the direct current component is less than a second threshold voltage, and maintains the previous output when the signal for canceling the direct current component is between the first threshold voltage and the second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.

2. The decision circuit of claim 1, wherein the delay circuit comprises N +1 sampling branches and a buffer, wherein N ≧ M, N and M are integers,

t is the period of the sampling clock;

the N +1 sampling branches are connected in parallel, the input ends of the N +1 sampling branches are simultaneously connected with a signal to be judged, the output ends of the N +1 sampling branches are simultaneously connected with the input end of the buffer, and the output end of the buffer is connected with the inverting input end of the subtracter circuit;

the sampling branch circuit comprises a first switch tube, a second switch tube and a capacitor, the input end of the first switch tube is connected to a signal to be judged, the output end of the second switch tube is connected to the input end of the buffer, and the output end of the first switch tube and the input end of the second switch tube are grounded through the capacitor.

3. The decision circuit of claim 2, wherein the subtractor circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;

the signal to be judged is connected to the positive phase input end of the operational amplifier through the first resistor, the output end of the buffer is connected to the negative phase input end of the operational amplifier through the third resistor, the second resistor is connected between the positive phase input end and the negative phase output end of the operational amplifier, and the fourth resistor is connected between the negative phase input end and the positive phase output end of the operational amplifier.

4. The decision circuit of claim 3, wherein the data recovery circuit comprises a first comparator, a second comparator, and an RS flip-flop;

the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the inverting output end of the operational amplifier;

a positive phase input end of the second comparator is connected to the second threshold voltage, and an inverted phase input end of the second comparator is connected with an inverted phase output end of the operational amplifier;

and the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the Q end of the RS trigger is a digital signal output end of the decision circuit.

5. The decision circuit of claim 3, wherein the data recovery circuit comprises a first comparator, a second comparator, and an RS flip-flop;

the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the non-inverting output end of the operational amplifier;

the positive phase input end of the second comparator is connected to the second threshold voltage, and the negative phase input end of the second comparator is connected with the positive phase output end of the operational amplifier;

the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the RS trigger

The terminal is the digital signal output terminal of the decision circuit.

6. The decision circuit according to claim 2, wherein the on-time of the switching tube in the N +1 sampling branches coincides with the period of the sampling clock, the driving signal from the sampling branch 0 to the first switching tube in the sampling branch N is sequentially delayed by one on-time, and the driving signal of the second switching tube in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube in the current sampling branch.

7. A receiver comprising an antenna, an amplifier, a filter, a mixer, a demodulator and a decision circuit, characterized in that the decision circuit is a decision circuit as claimed in any one of claims 1 to 6.

Images