CN103401537A - Decision circuit and receiver - Google Patents

Decision circuit and receiver Download PDF

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CN103401537A
CN103401537A CN2013103293669A CN201310329366A CN103401537A CN 103401537 A CN103401537 A CN 103401537A CN 2013103293669 A CN2013103293669 A CN 2013103293669A CN 201310329366 A CN201310329366 A CN 201310329366A CN 103401537 A CN103401537 A CN 103401537A
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comparator
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threshold voltage
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CN103401537B (en
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杨少丹
阴亚东
牟荣增
阎跃鹏
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Kunshan Microelectronics Technology Research Institute
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Institute of Microelectronics of CAS
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Abstract

The invention discloses a decision circuit, which comprises a delay circuit, a subtracter circuit and a data recovery circuit, wherein a signal to be decided is delayed from a 1/3 symbol period to a 5/3 symbol period, and then the signal is outputted to the subtracter circuit by the delay circuit; difference comparison is carried out on the decision signal and the delayed signal by the subtracter circuit, so that direct current component in the signal to be decided is eliminated, and the signal in which the direct current component is eliminated is outputted to the data recovery circuit; 1 is outputted by the data recovery circuit when the signal in which the direct current component is eliminated is larger than a first threshold voltage, and 0 is outputted by the data recovery circuit when the signal in which the direct current component is eliminated is less than a second threshold voltage; and when the signal in which the direct current component is eliminated is between the first threshold voltage and the second threshold voltage, keeping the last time output. With the adoption of the decision circuit, the data can be accurately recovered. The invention also discloses a receiver containing the above decision circuit.

Description

一种判决电路及接收机A decision circuit and receiver

技术领域technical field

本发明属于信号处理技术领域,尤其涉及一种判决电路及接收机。The invention belongs to the technical field of signal processing, and in particular relates to a decision circuit and a receiver.

背景技术Background technique

判决电路是接收机的重要组成部分,用于将接收机前端处理得到的模拟信号与参考电压进行比较,以输出数字信号。The decision circuit is an important part of the receiver, which is used to compare the analog signal processed by the front end of the receiver with the reference voltage to output a digital signal.

在实际应用中,往往由于载波和本地频率之间的频偏、在发送期间的信号失真、各个部件之间的失配和信道干扰,造成判决电路的待判决信号中存在直流分量。当待判决信号中存在直流分量时,会导致判决电路出现误判。In practical applications, there is often a DC component in the signal to be decided by the decision circuit due to the frequency offset between the carrier and the local frequency, signal distortion during transmission, mismatch between various components, and channel interference. When there is a DC component in the signal to be judged, it will cause misjudgment in the judgment circuit.

如何消除待判决信号中直流分量的影响,准确地恢复数据是本领域技术人员亟待解决的问题。How to eliminate the influence of the DC component in the signal to be decided and restore the data accurately is a problem to be solved urgently by those skilled in the art.

发明内容Contents of the invention

有鉴于此,本发明的目的在于提供一种判决电路,可以消除待判决信号中直流分量的影响,从而准确的恢复数据。In view of this, the object of the present invention is to provide a decision circuit, which can eliminate the influence of the DC component in the signal to be decided, so as to recover data accurately.

为实现上述目的,本发明提供如下技术方案:To achieve the above object, the present invention provides the following technical solutions:

本发明公开了一种判决电路,应用于接收机中,所述判决电路包括延迟电路、减法器电路和数据恢复电路;The invention discloses a judgment circuit, which is applied in a receiver, and the judgment circuit includes a delay circuit, a subtractor circuit and a data recovery circuit;

所述延迟电路的输入端接入待判决信号、输出端连接至所述减法器电路的一个输入端,所述延迟电路将所述待判决信号延迟预设时间后输出至所述减法器电路,所述预设时间为T/3至5T/3,其中,T为待判决信号的符号周期;The input end of the delay circuit is connected to the signal to be decided, and the output end is connected to an input end of the subtracter circuit, and the delay circuit delays the signal to be decided for a preset time and outputs it to the subtracter circuit, The preset time is T/3 to 5T/3, where T is the symbol period of the signal to be decided;

所述减法器电路的另一个输入端接入所述待判决信号,所述减法器电路对所述待判决信号和经过延迟后的信号进行差分比较,消除所述待判决信号中的直流分量,输出消除直流分量的信号至所述数据恢复电路;The other input end of the subtractor circuit is connected to the signal to be decided, and the subtracter circuit performs a differential comparison between the signal to be decided and the delayed signal to eliminate the DC component in the signal to be decided, outputting a signal for eliminating the DC component to the data recovery circuit;

所述数据恢复电路在所述消除直流分量的信号大于第一阈值电压时输出1,在所述消除直流分量的信号小于第二阈值电压时输出0,在所述消除直流分量的信号位于所述第一阈值电压和第二阈值电压之间时,保持上次的输出,其中,所述第一阈值电压大于所述第二阈值电压。The data recovery circuit outputs 1 when the signal with the eliminated DC component is greater than the first threshold voltage, outputs 0 when the signal with the eliminated DC component is lower than the second threshold voltage, and outputs 0 when the signal with the eliminated DC component is in the When the voltage is between the first threshold voltage and the second threshold voltage, the last output is maintained, wherein the first threshold voltage is greater than the second threshold voltage.

优选的,在上述判决电路中,所述延迟电路包括N+1个采样支路和缓冲器,其中,N≥M,N和M为整数,,t为采样时钟的周期;Preferably, in the above decision circuit, the delay circuit includes N+1 sampling branches and buffers, where N≥M, N and M are integers, , t is the period of the sampling clock;

N+1个采样支路并联连接,N+1个采样支路的输入端同时接入待判决信号,N+1个采样支路的输出端同时连接至所述缓冲器的输入端,所述缓冲器的输出端连接至所述减法器电路的反相输入端;The N+1 sampling branches are connected in parallel, the input ends of the N+1 sampling branches are simultaneously connected to the signal to be decided, and the output ends of the N+1 sampling branches are simultaneously connected to the input end of the buffer, and the the output of the buffer is connected to the inverting input of the subtractor circuit;

所述采样支路包括第一开关管、第二开关管和电容,所述第一开关管的输入端接入待判决信号,所述第二开关管的输出端连接至所述缓冲器的输入端,所述第一开关管的输出端和所述第二开关管的输入端通过所述电容接地。The sampling branch includes a first switch tube, a second switch tube and a capacitor, the input end of the first switch tube is connected to the signal to be determined, and the output end of the second switch tube is connected to the input of the buffer end, the output end of the first switch tube and the input end of the second switch tube are grounded through the capacitor.

优选的,在上述判决电路中,所述减法器电路包括运算放大器、第一电阻、第二电阻、第三电阻和第四电阻;Preferably, in the above decision circuit, the subtractor circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor;

所述待判决信号通过所述第一电阻接入所述运算放大器的正相输入端,所述缓冲器的输出端通过所述第三电阻连接至所述运算放大器的反相输入端,所述第二电阻连接在所述运算放大器的正相输入端和反相输出端之间,所述第四电阻连接在所述运算放大器的反相输入端和正相输出端之间。The signal to be decided is connected to the non-inverting input terminal of the operational amplifier through the first resistor, the output terminal of the buffer is connected to the inverting input terminal of the operational amplifier through the third resistor, and the The second resistor is connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier, and the fourth resistor is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier.

优选的,在上述判决电路中,所述数据恢复电路包括第一比较器、第二比较器和RS触发器;Preferably, in the above decision circuit, the data recovery circuit includes a first comparator, a second comparator and an RS flip-flop;

所述第一比较器的反相输入端接入所述第一阈值电压、正相输入端与所述运算放大器的反相输出端连接;The inverting input terminal of the first comparator is connected to the first threshold voltage, and the non-inverting input terminal is connected to the inverting output terminal of the operational amplifier;

所述第二比较器的正相输入端接入所述第二阈值电压、反相输入端与所述运算放大器的反相输出端连接;The non-inverting input terminal of the second comparator is connected to the second threshold voltage, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier;

所述RS触发器的S端与所述第一比较器的输出端连接、R端与所述第二比较器的输出端连接,所述RS触发器的Q端为所述判决电路的数字信号输出端。The S end of the RS flip-flop is connected to the output end of the first comparator, the R end is connected to the output end of the second comparator, and the Q end of the RS flip-flop is the digital signal of the decision circuit output.

优选的,在上述判决电路中,所述数据恢复电路包括第一比较器、第二比较器和RS触发器;Preferably, in the above decision circuit, the data recovery circuit includes a first comparator, a second comparator and an RS flip-flop;

所述第一比较器的反相输入端接入所述第一阈值电压、正相输入端与所述运算放大器的正相输出端连接;The inverting input terminal of the first comparator is connected to the first threshold voltage, and the non-inverting input terminal is connected to the non-inverting output terminal of the operational amplifier;

所述第二比较器的正相输入端接入所述第二阈值电压、反相输入端与所述运算放大器的正相输出端连接;The non-inverting input terminal of the second comparator is connected to the second threshold voltage, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier;

所述RS触发器的S端与所述第一比较器的输出端连接、R端与所述第二比较器的输出端连接,所述RS触发器的

Figure BDA00003599183000031
端为所述判决电路的数字信号输出端。The S end of the RS flip-flop is connected to the output end of the first comparator, the R end is connected to the output end of the second comparator, and the RS flip-flop
Figure BDA00003599183000031
The terminal is the digital signal output terminal of the decision circuit.

优选的,在上述判决电路中,所述N+1个采样支路中开关管的开启时间与采样时钟的周期一致,从采样支路0至采样支路N中的第一开关管的驱动信号依次延迟一个开启时间,并且每个采样支路中的第二开关管的驱动信号相对于本采样支路中的第一开关管的驱动信号延迟T/3至5T/3。Preferably, in the above decision circuit, the turn-on time of the switches in the N+1 sampling branches is consistent with the period of the sampling clock, and the driving signal from the sampling branch 0 to the first switching tube in the sampling branch N A turn-on time is sequentially delayed, and the driving signal of the second switching tube in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube in this sampling branch.

本发明还公开了一种接收机,包括天线、放大器、滤波器、混频器、解调器和上述任意一种判决电路。The invention also discloses a receiver, which includes an antenna, an amplifier, a filter, a mixer, a demodulator and any one of the above decision circuits.

由此可见,本发明的有益效果为:本发明公开的判决电路包括延迟电路、减法器电路和数据恢复电路,首先利用延迟电路将待判决信号Vin延迟1/3个符号周期至5/3个符号周期,之后减法器电路对待判决信号Vin和经过延迟后的信号进行差分比较,就可以消除待判决信号Vin中的直流分量,从而保证了数据恢复电路可以准确的恢复数据。It can be seen that the beneficial effect of the present invention is: the decision circuit disclosed by the present invention includes a delay circuit, a subtractor circuit and a data recovery circuit, and first uses the delay circuit to delay the signal Vin to be decided by 1/3 symbol period to 5/3 The symbol period, and then the subtractor circuit performs a differential comparison between the signal to be decided Vin and the delayed signal, so as to eliminate the DC component in the signal to be decided Vin, thereby ensuring that the data recovery circuit can recover data accurately.

附图说明Description of drawings

为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

图1为本发明公开的一种判决电路的结构示意图;Fig. 1 is a schematic structural diagram of a decision circuit disclosed by the present invention;

图2为本发明公开的另一种判决电路的结构示意图;FIG. 2 is a schematic structural diagram of another decision circuit disclosed by the present invention;

图3为待判决信号的波形示意图;Fig. 3 is the schematic diagram of the waveform of the signal to be judged;

图4为图2所示判决电路中延迟电路的各个开关管的驱动信号的一种示意图;Fig. 4 is a kind of schematic diagram of the driving signals of each switching tube of the delay circuit in the decision circuit shown in Fig. 2;

图5为图2所示判决电路中数据恢复电路的功能示意图;Fig. 5 is the functional schematic diagram of the data recovery circuit in the judgment circuit shown in Fig. 2;

图6为本发明公开的另一种判决电路的结构示意图;FIG. 6 is a schematic structural diagram of another decision circuit disclosed in the present invention;

图7为本发明公开的一种接收机的结构示意图。Fig. 7 is a schematic structural diagram of a receiver disclosed in the present invention.

具体实施方式Detailed ways

为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

本发明公开了一种判决电路,可以消除待判决信号中直流分量的影响,从而准确的恢复数据。The invention discloses a judgment circuit, which can eliminate the influence of the direct current component in the signal to be judged, thereby recovering data accurately.

参见图1,图1为本发明公开的一种判决电路的结构示意图。该判决电路包括延迟电路100、减法器电路200和数据恢复电路300。Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100 , a subtractor circuit 200 and a data recovery circuit 300 .

其中:in:

延迟电路100的输入端接入待判决信号Vin,延迟电路100的输出端连接至减法器电路200的一个输入端,延迟电路100将待判决信号Vin延迟预设时间后输出至减法器电路200,该预设时间为T/3至5T/3,其中,T为待判决信号的符号周期。The input end of the delay circuit 100 is connected to the signal Vin to be decided, the output end of the delay circuit 100 is connected to an input end of the subtracter circuit 200, and the delay circuit 100 delays the signal Vin to be decided for a preset time and outputs it to the subtracter circuit 200, The preset time is T/3 to 5T/3, where T is the symbol period of the signal to be decided.

减法器电路200的一个输入端接入经过延迟后的信号、另一个输入端接入待判决信号Vin,减法器电路200对待判决信号Vin和经过延迟后的信号进行差分比较,从而消除待判决信号Vin中的直流分量,输出消除直流分量的信号至数据恢复电路300。One input terminal of the subtractor circuit 200 is connected to the delayed signal, and the other input terminal is connected to the signal Vin to be decided. The subtractor circuit 200 performs a differential comparison between the signal Vin to be decided and the delayed signal, thereby eliminating the signal to be decided. The DC component in Vin is output to the data recovery circuit 300 by eliminating the DC component.

数据恢复电路300在消除直流分量的信号大于第一阈值电压时输出1,在消除直流分量的信号小于第二阈值电压时输出0,在消除直流分量的信号位于第一阈值电压和第二阈值电压之间时,保持上次的输出,其中,第一阈值电压大于第二阈值电压。The data recovery circuit 300 outputs 1 when the signal of eliminating the DC component is greater than the first threshold voltage, outputs 0 when the signal of eliminating the DC component is smaller than the second threshold voltage, and outputs 0 when the signal of eliminating the DC component is between the first threshold voltage and the second threshold voltage In between, the last output is maintained, wherein the first threshold voltage is greater than the second threshold voltage.

本发明公开的判决电路包括延迟电路100、减法器电路200和数据恢复电路300,首先利用延迟电路100将待判决信号Vin延迟1/3符号周期至5/3符号周期,之后减法器电路200对待判决信号Vin和经过延迟后的信号进行差分比较,就可以消除待判决信号Vin中的直流分量,从而保证了数据恢复电路300可以准确的恢复数据。The decision circuit disclosed in the present invention includes a delay circuit 100, a subtractor circuit 200 and a data recovery circuit 300. First, the delay circuit 100 is used to delay the signal Vin to be decided by 1/3 symbol period to 5/3 symbol period, and then the subtractor circuit 200 treats By performing a differential comparison between the decision signal Vin and the delayed signal, the DC component in the signal to be decided Vin can be eliminated, thereby ensuring that the data recovery circuit 300 can recover data accurately.

下面结合一更为具体的实施例进行说明。The following will be described in conjunction with a more specific embodiment.

参见图2,图2为本发明公开的另一种判决电路的结构示意图。该判决电路包括延迟电路100、减法器电路200和数据恢复电路300。Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of another decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100 , a subtractor circuit 200 and a data restoration circuit 300 .

其中:in:

延迟电路100包括N+1个采样支路(即采样支路0至采样支路N)和缓冲器101,其中,N≥M,N和M为整数,

Figure BDA00003599183000051
,T为待判决信号的符号周期,t为采样时钟的周期。N+1个采样支路并联连接,N+1个采样支路的输入端同时接入待判决信号Vin,N+1个采样支路的输出端同时连接至缓冲器101的输入端,缓冲器101的输出端连接至减法器电路200的反相输入端。每个采样支路包括第一开关管Q1、第二开关管Q2和电容C,第一开关管Q1的输入端接入待判决信号Vin,第二开关管Q2的输出端连接至缓冲器101的输入端,第一开关管Q1的输出端和第二开关管Q2的输入端通过电容C接地。The delay circuit 100 includes N+1 sampling branches (that is, sampling branch 0 to sampling branch N) and a buffer 101, where N≥M, N and M are integers,
Figure BDA00003599183000051
, T is the symbol period of the signal to be decided, and t is the period of the sampling clock. The N+1 sampling branches are connected in parallel, the input ends of the N+1 sampling branches are simultaneously connected to the signal Vin to be decided, and the output ends of the N+1 sampling branches are simultaneously connected to the input end of the buffer 101, and the buffer The output terminal of 101 is connected to the inverting input terminal of the subtractor circuit 200 . Each sampling branch includes a first switching tube Q1, a second switching tube Q2 and a capacitor C, the input terminal of the first switching tube Q1 is connected to the signal Vin to be decided, and the output terminal of the second switching tube Q2 is connected to the buffer 101 The input terminal, the output terminal of the first switching transistor Q1 and the input terminal of the second switching transistor Q2 are grounded through the capacitor C.

在应用过程中,通过在延迟电路100中的各个开关管上施加相应的驱动信号,可以保证延迟电路100将待判决信号延时迟1/3个符号周期至5/3个符号周期。具体的,设置N+1个采样支路中各个开关管的开启时间t与采样时钟CLK的周期一致,从采样支路0至采样支路N中的第一开关管Q1的驱动信号依次延迟一个开启时间t,并且每个采样支路中的第二开关管Q2的驱动信号相对于本采样支路中的第一开关管Q1的驱动信号延迟T/3至5T/3。需要说明的是,各个采样支路中的第二开关管Q2的驱动信号相对于本采样支路中的第一开关管Q1的驱动信号延迟的时间是相同的。In the application process, by applying corresponding driving signals to each switch tube in the delay circuit 100, it can be ensured that the delay circuit 100 delays the signal to be decided by 1/3 symbol period to 5/3 symbol period. Specifically, the turn-on time t of each switch tube in the N+1 sampling branches is set to be consistent with the period of the sampling clock CLK, and the driving signal from the sampling branch 0 to the first switching tube Q1 in the sampling branch N is delayed by one The turn-on time is t, and the driving signal of the second switching tube Q2 in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube Q1 in this sampling branch. It should be noted that the delay time of the driving signal of the second switching transistor Q2 in each sampling branch relative to the driving signal of the first switching transistor Q1 in this sampling branch is the same.

减法器电路200包括运算放大器U1、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。待判决信号Vin通过第一电阻R1接入运算放大器U1的正相输入端,缓冲器101的输出端通过第三电阻R3连接至运算放大器U1的反相输入端,第二电阻R2连接在运算放大器U1的正相输入端和反相输出端之间,第四电阻R4连接在运算放大器U1的反相输入端和正相输出端之间。The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The signal Vin to be decided is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the output terminal of the buffer 101 is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

待判决信号Vin的形式是Vdc+Vac(直流和交流),如图3所示。由于各种因素(如FSK调制解调中载波和本地频率之间的频偏、各个部件的失配和各个解调信号之间信道的干扰等)的影响,可能导致Vdc偏量发生变化,从而造成数据判决出现偏差。The form of the signal Vin to be judged is V dc +V ac (direct current and alternating current), as shown in FIG. 3 . Due to the influence of various factors (such as the frequency offset between the carrier and local frequency in FSK modulation and demodulation, the mismatch of various components, and the interference of channels between various demodulated signals, etc.), the V dc offset may change, As a result, data judgments are biased.

减法器要实现的功能是:The functions to be implemented by the subtractor are:

Vsub=Vin-Vdelay=(Vdc,in+Vac,in)-(Vdc,delay+Vac,delay)=Vac,in-Vac,delay以消除直流分量的影响。V sub =V in -V delay =(V dc,in +V ac,in )-(V dc,delay +V ac,delay )=V ac,in -V ac,delay to eliminate the influence of the DC component.

数据恢复电路300包括第一比较器COM1、第二比较器COM2和RS触发器301。第一比较器COM1的反相输入端接入第一阈值电压Vh、正相输入端与运算放大器U1的反相输出端连接。第二比较器COM2的正相输入端接入第二阈值电压Vl、反相输入端与运算放大器U1的反相输出端连接。RS触发器301的S端与第一比较器COM1的输出端连接、R端与第二比较器COM2的输出端连接,RS触发器的Q端为判决电路的数字信号输出端。The data recovery circuit 300 includes a first comparator COM1 , a second comparator COM2 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM1 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM2 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The S terminal of the RS flip-flop 301 is connected to the output terminal of the first comparator COM1, the R terminal is connected to the output terminal of the second comparator COM2, and the Q terminal of the RS flip-flop is the digital signal output terminal of the decision circuit.

下面结合图4示出的各个开关管的驱动信号对图2所示判决电路的运行过程进行说明。The operation process of the decision circuit shown in FIG. 2 will be described below in conjunction with the driving signals of each switch tube shown in FIG. 4 .

在延迟电路100中,采样支路0至采样支路N中的第一开关管Q1的控制端分别施加驱动信号P0至Pn,也就是采样支路0中的第一开关管Q1的控制端施加驱动信号P0,采样支路1中的第一开关管Q1的控制端施加驱动信号P1,以此类推,采样支路N-1中的第一开关管Q1的控制端施加驱动信号Pn-1,采样支路N中的第一开关管Q1的控制端施加驱动信号Pn。另外,采样支路0中的第二开关管Q2的控制端施加驱动信号Pn,采样支路1至采样支路N中的第二开关管Q2的控制端分别施加驱动信号P0至Pn-1,也就是采样支路1中的第二开关管Q2的控制端施加驱动信号P0,采样支路2中的第二开关管Q2的控制端施加驱动信号P1,以此类推,采样支路N-1中的第二开关管Q2的控制端施加驱动信号Pn-2,采样支路N中的第二开关管Q2的控制端施加驱动信号Pn-1。也就是,各个采样电路中的第二开关管Q2相对于本采样支路中的第一开关管Q1延迟N/N+1个符号周期导通。In the delay circuit 100, the control terminals of the first switching tube Q1 in the sampling branch 0 to the sampling branch N are respectively applied with driving signals P0 to Pn, that is, the control terminal of the first switching tube Q1 in the sampling branch 0 is applied Drive signal P0, the control terminal of the first switching tube Q1 in the sampling branch 1 applies the driving signal P1, and so on, the control terminal of the first switching tube Q1 in the sampling branch N-1 applies the driving signal Pn-1, A driving signal Pn is applied to the control terminal of the first switching transistor Q1 in the sampling branch N. In addition, the control terminal of the second switching transistor Q2 in the sampling branch 0 is applied with the driving signal Pn, and the control terminals of the second switching transistor Q2 in the sampling branch 1 to the sampling branch N are respectively applied with the driving signals P0 to Pn-1, That is, the control terminal of the second switching tube Q2 in the sampling branch 1 applies the driving signal P0, and the control terminal of the second switching tube Q2 in the sampling branch 2 applies the driving signal P1, and so on, the sampling branch N-1 The driving signal Pn-2 is applied to the control end of the second switching transistor Q2 in the sampling branch N, and the driving signal Pn-1 is applied to the control end of the second switching transistor Q2 in the sampling branch N. That is, the second switching tube Q2 in each sampling circuit is turned on with a delay of N/N+1 symbol periods relative to the first switching tube Q1 in the sampling branch.

以采样支路0为例对各个采样电路的延迟过程进行说明。待判决信号Vin从节点a输入,之后经过节点b,到达节点c。当驱动信号P0控制第一开关管Q1导通的时候,第二开关管Q2是关断的,待判决信号Vin对电容C进行充电,即电容C对带判决信号Vin进行了采样,此时节点b和节点a的电压是相同的。当第一开关管Q1关断后,节点b的电压保持不变。当驱动信号Pn控制第二开关管Q2导通时,节点c上的电压和节点b上的电压是相同的,节点c上的电压传输至缓冲器101,最终传输至减法器电路200。当第二开关管Q2关断后,第一开关管Q1导通,进入下一个循环。可以看到,待判决信号被延迟了N/N+1个符号周期。Taking the sampling branch 0 as an example, the delay process of each sampling circuit is described. The signal Vin to be decided is input from node a, then passes through node b, and reaches node c. When the drive signal P0 controls the first switch tube Q1 to be turned on, the second switch tube Q2 is turned off, and the pending decision signal Vin charges the capacitor C, that is, the capacitor C samples the judgment signal Vin, at this time the node The voltage at node b and a is the same. After the first switch tube Q1 is turned off, the voltage at node b remains unchanged. When the driving signal Pn controls the second switching transistor Q2 to turn on, the voltage on the node c is the same as the voltage on the node b, and the voltage on the node c is transmitted to the buffer 101 and finally transmitted to the subtractor circuit 200 . After the second switching tube Q2 is turned off, the first switching tube Q1 is turned on and enters the next cycle. It can be seen that the signal to be decided is delayed by N/N+1 symbol periods.

延迟电路100中N+1个采样支路输出的电压是离散的,并可能伴随着毛刺,缓冲器101可以对延迟后的信号进行滤波积分,同时还可以进行电流隔离,避免经过延迟的信号的电流与减法器电路200中的电流相互影响。The voltages output by the N+1 sampling branches in the delay circuit 100 are discrete and may be accompanied by glitches. The buffer 101 can filter and integrate the delayed signal, and can also perform current isolation to avoid the delay of the delayed signal. The current interacts with the current in the subtractor circuit 200 .

待判决信号Vin被传输至运算放大器U1的正相输入端,经过延迟的信号被传输至运算放大器U1的反相输入端,运算放大器U1对两者进行差分比较,在其反相输出端输出消除了直流分量的信号,在正相输出端输出消除了直流分量的信号的反相信号。The signal Vin to be judged is transmitted to the non-inverting input terminal of the operational amplifier U1, and the delayed signal is transmitted to the inverting input terminal of the operational amplifier U1. The signal with the DC component removed, and the inversion signal of the signal with the DC component eliminated is output at the non-inverting output terminal.

之后,消除了直流分量的信号被分别送入第一比较器COM1的正相输入端和第二比较器COM2的反相输入端,第一比较器COM1的反相输入端接入第一阈值电压Vh,第二比较器COM2的正相输入端接入第二阈值电压Vl,并且第一阈值电压Vh大于第二阈值电压Vl。第一比较器COM1的输出端连接至RS触发器301的S端,第二比较器COM2的输出端连接至RS触发器301的R端。After that, the signal with the DC component eliminated is sent to the non-inverting input terminal of the first comparator COM1 and the inverting input terminal of the second comparator COM2 respectively, and the inverting input terminal of the first comparator COM1 is connected to the first threshold voltage Vh, the non-inverting input terminal of the second comparator COM2 is connected to the second threshold voltage Vl, and the first threshold voltage Vh is greater than the second threshold voltage Vl. The output terminal of the first comparator COM1 is connected to the S terminal of the RS flip-flop 301 , and the output terminal of the second comparator COM2 is connected to the R terminal of the RS flip-flop 301 .

数据恢复电路300的功能如图5所示。The function of the data recovery circuit 300 is shown in FIG. 5 .

当消除了直流分量的信号大于第一阈值电压Vh时,第一比较器COM1输出高电平、可视为“1”,第二比较器COM2输出低电平、可视为“0”,此时RS触发器301的Q端输出高电平、可视为“1”。当消除了直流分量的信号小于第二阈值电压Vl时,第一比较器COM1输出低电平、可视为“0”,第二比较器COM2输出高电平、可视为“1”,此时RS触发器301的Q端输出低电平、可视为“0”。当消除了直流分量的信号小于第一阈值电压Vh且大于第二阈值电压Vl时,输出结果保持不变。RS触发器301的Q端作为整个判决电路的数字信号输出端。When the signal with the DC component eliminated is greater than the first threshold voltage Vh, the first comparator COM1 outputs a high level, which can be regarded as "1", and the second comparator COM2 outputs a low level, which can be regarded as "0". At this time, the Q terminal of the RS flip-flop 301 outputs a high level, which can be regarded as "1". When the signal with the DC component eliminated is less than the second threshold voltage V1, the first comparator COM1 outputs a low level, which can be regarded as "0", and the second comparator COM2 outputs a high level, which can be regarded as "1". At this time, the Q terminal of the RS flip-flop 301 outputs a low level, which can be regarded as "0". When the signal with the DC component eliminated is less than the first threshold voltage Vh and greater than the second threshold voltage Vl, the output result remains unchanged. The Q terminal of the RS flip-flop 301 serves as the digital signal output terminal of the entire decision circuit.

图2仅示出了判决电路一种较为具体的结构,判决电路还可以采用其他结构实现。参见图6,图6为本发明公开的另一种判决电路的结构示意图。该判决电路包括延迟电路100、减法器电路200和数据恢复电路300。其中,延迟电路100的结构如图2所示,在此不再赘述。FIG. 2 only shows a relatively specific structure of the decision circuit, and the decision circuit can also be implemented with other structures. Referring to FIG. 6, FIG. 6 is a schematic structural diagram of another decision circuit disclosed in the present invention. The decision circuit includes a delay circuit 100 , a subtractor circuit 200 and a data recovery circuit 300 . Wherein, the structure of the delay circuit 100 is shown in FIG. 2 , which will not be repeated here.

减法器电路200包括运算放大器U1、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。待判决信号Vin通过第一电阻R1接入运算放大器U1的正相输入端,缓冲器101的输出端通过第三电阻R3连接至运算放大器U1的反相输入端,第二电阻R2连接在运算放大器U1的正相输入端和反相输出端之间,第四电阻R4连接在运算放大器U1的反相输入端和正相输出端之间。The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The signal Vin to be decided is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the output terminal of the buffer 101 is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

数据恢复电路300包括第一比较器COM3、第二比较器COM4和RS触发器301。第一比较器COM3的反相输入端接入第一阈值电压Vh、正相输入端与运算放大器U1的正相输出端连接。第二比较器COM4的正相输入端接入第二阈值电压Vl、反相输入端与运算放大器U1的正相输出端连接。RS触发器301的S端与第一比较器COM1的输出端连接、R端与第二比较器COM2的输出端连接,RS触发器的

Figure BDA00003599183000091
端为判决电路的数字信号输出端。The data recovery circuit 300 includes a first comparator COM3 , a second comparator COM4 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The S end of the RS flip-flop 301 is connected to the output end of the first comparator COM1, the R end is connected to the output end of the second comparator COM2, and the RS flip-flop
Figure BDA00003599183000091
The terminal is the digital signal output terminal of the decision circuit.

实施中,减法器电路200和数据恢复电路300还可以采用其他连接方式。In implementation, the subtracter circuit 200 and the data restoration circuit 300 may also adopt other connection manners.

例如:减法器电路200包括运算放大器U1、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。缓冲器101的输出端通过第一电阻R1接入运算放大器U1的正相输入端,待判决信号Vin通过第三电阻R3连接至运算放大器U1的反相输入端,第二电阻R2连接在运算放大器U1的正相输入端和反相输出端之间,第四电阻R4连接在运算放大器U1的反相输入端和正相输出端之间。For example: the subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The output terminal of the buffer 101 is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the signal Vin to be judged is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

数据恢复电路300包括第一比较器COM3、第二比较器COM4和RS触发器301。第一比较器COM3的反相输入端接入第一阈值电压Vh、正相输入端与运算放大器U1的反相输出端连接。第二比较器COM4的正相输入端接入第二阈值电压Vl、反相输入端与运算放大器U1的反相输出端连接。RS触发器301的S端与第一比较器COM1的输出端连接、R端与第二比较器COM2的输出端连接,RS触发器的

Figure BDA00003599183000101
端为判决电路的数字信号输出端。The data recovery circuit 300 includes a first comparator COM3 , a second comparator COM4 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the inverting output terminal of the operational amplifier U1. The S end of the RS flip-flop 301 is connected to the output end of the first comparator COM1, the R end is connected to the output end of the second comparator COM2, and the RS flip-flop
Figure BDA00003599183000101
The terminal is the digital signal output terminal of the decision circuit.

或者,or,

减法器电路200包括运算放大器U1、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。缓冲器101的输出端通过第一电阻R1接入运算放大器U1的正相输入端,待判决信号Vin通过第三电阻R3连接至运算放大器U1的反相输入端,第二电阻R2连接在运算放大器U1的正相输入端和反相输出端之间,第四电阻R4连接在运算放大器U1的反相输入端和正相输出端之间。The subtractor circuit 200 includes an operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. The output terminal of the buffer 101 is connected to the non-inverting input terminal of the operational amplifier U1 through the first resistor R1, the signal Vin to be judged is connected to the inverting input terminal of the operational amplifier U1 through the third resistor R3, and the second resistor R2 is connected to the operational amplifier U1. Between the non-inverting input terminal and the inverting output terminal of U1, the fourth resistor R4 is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier U1.

数据恢复电路300包括第一比较器COM3、第二比较器COM4和RS触发器301。第一比较器COM3的反相输入端接入第一阈值电压Vh、正相输入端与运算放大器U1的正相输出端连接。第二比较器COM4的正相输入端接入第二阈值电压Vl、反相输入端与运算放大器U1的正相输出端连接。RS触发器301的S端与第一比较器COM1的输出端连接、R端与第二比较器COM2的输出端连接,RS触发器的Q端为判决电路的数字信号输出端。The data recovery circuit 300 includes a first comparator COM3 , a second comparator COM4 and an RS flip-flop 301 . The inverting input terminal of the first comparator COM3 is connected to the first threshold voltage Vh, and the non-inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The non-inverting input terminal of the second comparator COM4 is connected to the second threshold voltage V1, and the inverting input terminal is connected to the non-inverting output terminal of the operational amplifier U1. The S terminal of the RS flip-flop 301 is connected to the output terminal of the first comparator COM1, the R terminal is connected to the output terminal of the second comparator COM2, and the Q terminal of the RS flip-flop is the digital signal output terminal of the decision circuit.

本发明上述公开了应用于接收机的判决电路,本发明还公开具有该判决电路的接收机。接收机的结构如图7所示,包括天线1、放大器2、滤波器3、解调器4和本发明上述公开的判决电路5。本发明公开的接收机在将接收到的信号解调为模拟信号后,可以通过判决电路5准确的恢复数据。The invention above discloses a decision circuit applied to a receiver, and the invention also discloses a receiver with the decision circuit. The structure of the receiver is shown in FIG. 7, including an antenna 1, an amplifier 2, a filter 3, a demodulator 4 and the decision circuit 5 disclosed above in the present invention. After the receiver disclosed in the present invention demodulates the received signal into an analog signal, the data can be recovered accurately through the decision circuit 5 .

本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A decision circuit for use in a receiver, wherein the decision circuit comprises a delay circuit, a subtractor circuit, and a data recovery circuit;
the input end of the delay circuit is connected with a signal to be judged, the output end of the delay circuit is connected to one input end of the subtracter circuit, the delay circuit delays the signal to be judged for a preset time and outputs the signal to be judged to the subtracter circuit, the preset time is T/3-5T/3, and T is a symbol period of the signal to be judged;
the other input end of the subtractor circuit is connected to the signal to be judged, the subtractor circuit carries out differential comparison on the signal to be judged and the delayed signal, eliminates a direct current component in the signal to be judged, and outputs a signal with the direct current component eliminated to the data recovery circuit;
the data recovery circuit outputs 1 when the signal for canceling the direct current component is greater than a first threshold voltage, outputs 0 when the signal for canceling the direct current component is less than a second threshold voltage, and maintains the previous output when the signal for canceling the direct current component is between the first threshold voltage and the second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage.
2. The decision circuit of claim 1, wherein the delay circuit comprises N +1 sampling branches and a buffer, wherein N ≧ M, N and M are integers,
Figure FDA00003599182900011
t is the period of the sampling clock;
the N +1 sampling branches are connected in parallel, the input ends of the N +1 sampling branches are simultaneously connected with a signal to be judged, the output ends of the N +1 sampling branches are simultaneously connected with the input end of the buffer, and the output end of the buffer is connected with the inverting input end of the subtracter circuit;
the sampling branch circuit comprises a first switch tube, a second switch tube and a capacitor, the input end of the first switch tube is connected to a signal to be judged, the output end of the second switch tube is connected to the input end of the buffer, and the output end of the first switch tube and the input end of the second switch tube are grounded through the capacitor.
3. The decision circuit of claim 2, wherein the subtractor circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the signal to be judged is connected to the positive phase input end of the operational amplifier through the first resistor, the output end of the buffer is connected to the negative phase input end of the operational amplifier through the third resistor, the second resistor is connected between the positive phase input end and the negative phase output end of the operational amplifier, and the fourth resistor is connected between the negative phase input end and the positive phase output end of the operational amplifier.
4. The decision circuit of claim 3, wherein the data recovery circuit comprises a first comparator, a second comparator, and an RS flip-flop;
the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the inverting output end of the operational amplifier;
a positive phase input end of the second comparator is connected to the second threshold voltage, and an inverted phase input end of the second comparator is connected with an inverted phase output end of the operational amplifier;
and the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the Q end of the RS trigger is a digital signal output end of the decision circuit.
5. The decision circuit of claim 3, wherein the data recovery circuit comprises a first comparator, a second comparator, and an RS flip-flop;
the inverting input end of the first comparator is connected to the first threshold voltage, and the non-inverting input end of the first comparator is connected with the non-inverting output end of the operational amplifier;
the positive phase input end of the second comparator is connected to the second threshold voltage, and the negative phase input end of the second comparator is connected with the positive phase output end of the operational amplifier;
the S end of the RS trigger is connected with the output end of the first comparator, the R end of the RS trigger is connected with the output end of the second comparator, and the RS trigger
Figure FDA00003599182900021
The terminal is the digital signal output terminal of the decision circuit.
6. The decision circuit according to claim 2, wherein the on-time of the switching tube in the N +1 sampling branches coincides with the period of the sampling clock, the driving signal from the sampling branch 0 to the first switching tube in the sampling branch N is sequentially delayed by one on-time, and the driving signal of the second switching tube in each sampling branch is delayed by T/3 to 5T/3 relative to the driving signal of the first switching tube in the current sampling branch.
7. A receiver comprising an antenna, an amplifier, a filter, a mixer, a demodulator and a decision circuit, characterized in that the decision circuit is a decision circuit as claimed in any one of claims 1 to 6.
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CN1368797A (en) * 2001-02-02 2002-09-11 三星电子株式会社 Data amplitude limiter and radio frequency receiver using it
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