CN103399831A - Implementation method for automatic circulating memory of NANDFLASH memorizer - Google Patents
Implementation method for automatic circulating memory of NANDFLASH memorizer Download PDFInfo
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- CN103399831A CN103399831A CN2013103532867A CN201310353286A CN103399831A CN 103399831 A CN103399831 A CN 103399831A CN 2013103532867 A CN2013103532867 A CN 2013103532867A CN 201310353286 A CN201310353286 A CN 201310353286A CN 103399831 A CN103399831 A CN 103399831A
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Abstract
The invention discloses an implementation method for automatic circulating memory of an NANDFLASH memorizer. The implementation method comprises an electrifying record process of a memory system and a data playback read process of the memory system, wherein the NANDFLASH memorizer serves as a mass memory carrier; an FPGA serves as a control and data processing system, and is used for realizing circulating writing, circulating reading, circulating erasing and bad block checking of data; the USB 2.0 serial port technology is adopted for realizing high-speed playback of large volume data; a host computer can read data in a visualized sectional manner during data matching with a real-time clock. The implementation method has the advantages that defects of slow reading, manual erasing, failure in circulating memorizing, and un-intelligent read manner of large volume data are overcome; requirements of memorizing and managing of large volume high-speed data of an aviation digital acquisition system in the future are met.
Description
Technical field
The present invention relates to a kind of large capacity storage control technology, be applicable to possess the missile-borne mass storage system of data automatic cycle storage, specifically relate to a kind of implementation method of NANDFLASH storer automatic cycle storage.
Background technology
Development along with aeronautical technology, for signal type variation, hyperchannel, the high sampling rate that number is adopted, register system is inputted, no matter missile-borne, spaceborne or carrier-borne measurement requirement, all a kind of memory capacity of active demand is large, data are preserved, are wiped intellectuality, and data read memory device fast, easily.And be applied at present the digital data recording system of missile-borne, and usually can't the automatic cycle storage, can't carry out selections to data segment and read.
Summary of the invention
The present invention is directed to the demand, a kind of novel mass data storage control technology is provided, can make the data capacity of digital data recording system larger, the better automatic cycle of executing data storage, data management is more intelligent, the speed of data readback is faster, more convenient, can effectively solve the high request of Aviation Test to the data register system.
The present invention takes following technical scheme, a kind of NANDFLASH storage system, comprise control and data processing module, data readback module, mass data storage module and real-time clock module, described control and data processing module receive the signal of signal source and real-time clock module, and with described data readback module, described mass data storage module by signal, be connected respectively, described mass data storage module is connected with described data readback module by signal;
Described control and data processing module complete and receive the signal source image data and form 64 * 32 standard telemetry frame formatted datas, for large capacity storage module provides reading and writing and wipes sequential;
Described large capacity storage module completes the storage of real-time frame structured data;
Described data readback module completes the serial port command that receives and send USB; The data of capacity storage module reading and wiping greatly; The send and receive of usb data;
Described real-time clock module is for providing the standard time to frame structure in real time.
The implementation method of a kind of NANDFLASH storage system automatic cycle storage, comprise that storage system powers on to record flow process and flow process is read in the memory system data playback,
Described storage system powers on and records flow process, and its job step is as follows:
Step 1: find out system initial block address and the chip select address of large capacity storage module, and as the upper electrographic initial address of this time;
Step 2: write this segment data head, in data inserting head writing time that will power on;
Step 3: periodically receive data and with standard telemetry frame form framing, initial address inserted in the present frame form, data are write in large capacity storage module;
Step 4: when writing full one, whether the data after this block address of Real-Time Monitoring are empty, clash if not empty this blocks of data, to reach circulation storage and the bad piece real-time detection function of data;
Flow process is read in described memory system data playback, and its job step is as follows:
Step 1: PC sends instruction to controlling and data processing module by the data readback module;
Step 2: response instruction, find the storage system original block;
Step 3: take out the first page data of first the good full piece block address that back finds by the system initial block address, and take out the initial block address that this data data segment is contained in this page data the inside;
Step 4: take out the first page data of current initial block address, take out this initial frame the inside and contain powering on writing time of this data segment;
Step 5: find out starting block address, end block address, the chip select address of second from the bottom section and power on writing time by step 2, three, four toward backtracking first good full piece again from current initial block address, the rest may be inferred can obtain starting block address, end block address, the chip select address of whole all data segments of storer and power on writing time, according to starting block address, end block address, chip select address, can calculate the size of data of this data segment, can reach the visual of data segment, and intelligent selections operation;
Described response instruction is first the good empty block address that finds this NANDFLASH, and this address is back being fallen of finding and write the block address that has expired data.
The obtained beneficial effect of the present invention is, utilize NANDFLASH as large capacity storage carrier, adopt FPGA as controlling and data handling system, for realizing that the circulation of data writes, circulation is read and is circulated and wipes and the detection of bad piece, adopts the USB2.0 Serial technology to realize the high-speed playback of Large Volume Data; By real-time clock to the data timing, realize host computer to data visual selections read.Can overcome for Large Volume Data storage, the reading manner disadvantage such as intelligence not that reads slowly, wipes manually, can't circulate, meet the demand that extraction system high-capacity and high-speed data storages, management are counted in following aviation.
The accompanying drawing explanation
Fig. 1 electrical relation of the present invention connects block diagram.
Section organization chart of Fig. 2 K9WAG08U1B.
Embodiment
The invention will be further described below in conjunction with drawings and Examples, referring to Fig. 1 and Fig. 2, the NANDFLASH storer, comprise and controlling and data processing module 1, data readback module 3, mass data storage module 2 and real-time clock module 4, it is characterized in that, described control and data processing module 1 receive the signal of signal source 5 and real-time clock module 4, and with described data readback module 3, described mass data storage module 2 signals, be connected respectively, described mass data storage module 2 is connected with described data readback module by signal 3.
Described control and data processing module 1 complete and receive the signal source image data and form 64 * 32 standard telemetry frame formatted datas, for large capacity storage module provides reading and writing and wipes sequential;
Described large capacity storage module 2 completes the storage of real-time frame structured data;
Described data readback module 3 completes the serial port command that receives and send USB; The reading and wiping of the data of mass storage; The send and receive of usb data;
Described real-time clock module 4 is for providing in real time the standard time to frame structure.
NANDFLASH memory operation principle of the present invention is as follows:
Control with data processing module and accept in real time analog quantity or the digital quantity signal of whole system under test (SUT), the same period real-time clock send time signal to controlling and data processing module, and data by concrete frame format requirement composition standard telemetry frame.Telemetry frame is sent to large capacity storage module real-time storage within each cycle, but large capacity storage module is returned to write address in real time to controlling and data processing module.When data readback, the data readback module is connected to PC by the USB extended line, PC sends instruction to controlling and data processing module by this data readback module, when control and data processing module receive the reading out data instruction, control with data processing module and read large capacity storage module data, and by the data readback module, send to PC in real time.
Implementation method of the present invention, comprise that storage system powers on to record flow process and flow process is read in the memory system data playback,
Described storage system powers on and records flow process, and its job step is as follows:
When the present invention carries out the circulation data writing when electrographic recording on system:
Step 1: control with data processing module and at first to large capacity storage module, find the good address block of a sky, and the output chip select address, and this block address and chip select address are gone up to electrographic initial address as this time.
Step 2: write the data of one page as this segment data head, this page comprises the real-time time that powers on from real-time clock module, the information such as data frame format size.
Step 3: system cycle reception data with standard telemetry frame form framing, and the initial address that this time powers on is inserted in the present frame form.When data reach the data volume of one page, data are write in large capacity storage module NANDFALSH, in every one cycle of execution, the page counting adds one, does not meet 64 pages, continues to carry out the 3rd step.
Step 4: when page counts full 64, namely write full one, whether the data in 1000 block address after this block address of Real-Time Monitoring are empty, clash if not empty this blocks of data, by that analogy.To reach circulation storage and the bad piece real-time detection function of data.
When system is in data readback (reading) function:
Step 1: PC sends instruction to controlling and data processing module by the data readback module.
Step 2: response instruction, write the block address (F1_Adress) that has expired data for one that finds first good empty block address of this NANDFLASH, this address back falling to find.
Step 3: take out the first page data of (F1_Adress) block address, take out the initial block address (init1_Adress) that this final data data segment is contained in this page data the inside.
Step 4: take out the first page data of (init1_Adress) initial block address, take out this initial frame the inside and contain powering on writing time of this data segment.
Step 5: find out starting block address, end block address, the chip select address of second from the bottom section and power on writing time by step 2, three, four toward backtracking first good full piece from (init1_Adress) initial block address, the rest may be inferred can obtain starting block address, end block address, the chip select address of whole all data segments of NANDFLASH storer and power on writing time, according to starting block address, end block address, chip select address, can calculate the size of data of this data segment, can reach the visual of data segment, and intelligent selections operation.
This programme solve the time NANDLFLASH storer automatic cycle storage implementation method, the problem that needs to solve is divided two substantially:
First is how to allow data not waste in the situation of resource, realizes data writing limit, limit obliterated data, and the data that record before can keeping as much as possible;
Second is that the data of storing can be read out easily, but also can reach, arbitrarily selects data segment to read.
Embodiment of the present invention are to be divided into by functional module: control and data processing module, data readback module, mass data storage module and real-time clock module.Control and data processing module employing large scale integrated chip (LSI chip) FPGA(complex programmable logic gate array) realize, adopt Samsung NANDFLASH chip to realize the mass data storage module, the data readback module adopts the USB2.0 control chip, as the control module of data importing computer.But employing is from the real-time timepiece chip of charged pool continuous working more than 5 years.Fig. 1 is that mass storage control system connects block diagram.
Nucleus module of the present invention is large capacity storage module, NANDFLASH flash chip namely, and the NANDFLASH flash chip is take K9WAG08U1B as example, divide two sections, by two sheet selected control systems, each section is 8192 pieces, each piece is by 64 pages, and every one page is comprised of (2K+64) byte.Be illustrated in figure 2 a section: a section is vertically superposeed and forms by 8192 piece _ 201,64 page register _ 207 are combined into one, each page register is merged and is formed by 2K byte _ 204 and 64 bytes 205 respectively, therefore each section is comprised of 0.5M page _ 206, and the data I/O port address is 8 202 and is specially I/O 0-I/O7 203.
The NANDFLASH flash chip writes, reading out data is that page writes and reads for basis, therefore makes page programming and page read, and wipes take piece as basis, therefore makes piece wipe.During the appearance of bad piece of NANDFLASH, in the process of wiping, just may occur, therefore when piece is wiped, carry out the sign of bad piece.
The job step of native system is as follows:
When system is carried out the circulation storage.Control with data processing module and at first to large capacity storage module, find the good address block of a sky, and the output chip select address, and this block address and chip select address are gone up to electrographic initial address as this time.Write the data of one page as this segment data head, this page comprises the real-time time that powers on from real-time clock module, the information such as data frame format size; System cycle reception data with standard telemetry frame form framing, and the initial address that this time powers on is inserted in the present frame form.When data reach the data volume of one page, data are write in large capacity storage module NANDFLASH, in every one cycle of execution, the page counting adds one.When page counts full 64, namely write full one, the zero clearing of page counting, whether the data in 1000 block address after this block address of Real-Time Monitoring are sky, clash if not empty this blocks of data, by that analogy.To reach circulation storage and the bad piece real-time detection function of data.
When system is in data readback (reading) function.PC sends instruction to controlling and data processing module by the data readback module, response instruction, write the block address that has expired data, be last full block address of the data segment of for the last time upper electrographic data of storage system for one that finds first good empty block address of this NANDFLASH, this address back falling to find, take out the first page data of last full block address, according to the data mode that writes, learn, the initial block address of this final data data segment is contained in this page data the inside, take out the first page data of the initial block address of final data data segment, according to the data mode that writes, learn, this page data is an initial frame of this last segment data, and the writing time that powers on of this data segment is contained in this initial frame the inside, from past first the good full piece of backtracking of the initial block address of final data section, deducibility goes out, the full piece that has been somebody's turn to do is the full data block of the last moment of second from the bottom period, and this data block the inside comprises the initial address of this data segment, take out the first page data of initial block address, can learn powering on writing time of this data segment, the rest may be inferred can obtain the starting block address of whole all data segments of NANDFLASH storer, the end block address, chip select address and powering on writing time, according to the starting block address, the end block address, chip select address can calculate the size of data of this data segment.
Therefore by the data frame head of finding out every section, read starting block address, the end address of every segment data, and power-on time, can realize the visual intelligent selections read functions of data.USB2.0 data readback module is as the bridge of PC and storer, as the transmission instruction of host computer and mass-storage system and the transmission of response instruction, major function is for to be uploaded to fast at short notice PC by a large amount of memory datas, to realize the quick playback of data.
No matter be the large capacity data writing of NANDFLASH or reading out data, what at first complete is that concrete implementation is as follows to the searching of first good empty piece (storage system initial address):
System take the NANDFLASH model as example as K9WAG08U1B, it has two sections (Flash_Num), 8192 of every sections piece, storage system be upper electrographic recording be circulate in real time stored program, namely, whenever having stored 1 blocks of data, just wipe that piece of latter 1000.Thereby keep in real time the empty piece of 1000.During just upper electrographic recording, look for the method for the good piece of first sky to be, separate four kinds of situations, be respectively:
1) the 0th from first section looks for first good piece, and whether first good piece is empty, if whether sky looks for the 2000th to be empty, if be also that the whole FLASH of empty explanation is for empty.The system initial address is first good piece of first section;
2) the 0th from first section looks for first good piece, and whether first good piece is empty, if sky looks for the 2000th whether to be empty, illustrates that if not sky the head of the first section of whole FLASH is empty, and the tail of second section may be empty.From the good piece of second first sky of section as the system initial address;
3) the 0th from first section looks for first good piece, and first good piece is not the sky piece, from first good block address, starts to look for the sky piece.Looked for a section not find the sky piece, illustrated that this section is for for full, the empty piece that finds from 0, the ground of next section, and as the system initial address;
4) the 0th from first section looks for first good piece, and first good piece is not the sky piece, from first good block address, starts to look for the sky piece.From this section, find empty good piece, illustrate this section less than, using the address of empty piece as the system initial address.
The steering order that the playback of memory system data is read has three, is respectively:
1) selections reading out data: the method can well solve the random selections of data and read, more humane operation, paragraph to be read is contained in the instruction the inside, after system receives instruction, by paragraph, find at once initial address and the end address of this paragraph data, find this paragraph data, and send to PC by USB;
2) show full segment data title: by finding the power-on time of each paragraph, initial end block address and chip select address, and this information exchange is crossed to USB send to PC, can well realize visualized operation;
3) all wipe: the data that empty whole mass storage.
Claims (3)
1. NANDFLASH storer, comprise control and data processing module, data readback module, mass data storage module and real-time clock module, it is characterized in that, described control and data processing module receive the signal of signal source and real-time clock module, and with described data readback module, described mass data storage module by signal, be connected respectively, described mass data storage module is connected with described data readback module by signal;
Described control and data processing module complete and receive the signal source image data and form 64 * 32 standard telemetry frame formatted datas, for large capacity storage module provides reading and writing and wipes sequential;
Described large capacity storage module completes the storage of real-time frame structured data;
Described data readback module completes the serial port command that receives and send USB; The reading and wiping of the data of mass storage; The send and receive of usb data;
Described real-time clock module is for providing the standard time to frame structure in real time.
2. the implementation method of a NANDFLASH storer automatic cycle as claimed in claim 1 storage, comprising that storage system powers on records flow process and flow process is read in the memory system data playback, it is characterized in that, described storage system powers on and records flow process, and its job step is as follows:
The first step: find large capacity storage modular system initial block address and chip select address, and as the upper electrographic initial address of this time;
Second step: write this segment data head, in power-on time data inserting head;
The 3rd step: periodically receive data and with standard telemetry frame form framing, the upper electrographic initial address of this time inserted in the present frame form; Data are write in large capacity storage module, and in every one cycle of execution, the page counting adds one, if do not met 64 pages, continues to carry out the 3rd step;
The 4th step: when page counts full 64, write full one, whether the data in 1000 block address after this block address of Real-Time Monitoring are empty, clash if not empty this blocks of data, to reach circulation storage and the bad piece real-time detection function of data;
Flow process is read in described memory system data playback, and its job step is as follows:
The first step: PC sends instruction to controlling and data processing module by the data readback module;
Second step: response instruction;
The 3rd step: take out the first page data of first the good full block address that back finds by the system initial block address, and take out the initial block address of this data segment that contains this page data the inside;
The 4th step: take out the first page data of current data section initial block address, take out powering on writing time of the current data section that contains this initial frame the inside;
The 5th step: find out starting block address, end block address, the chip select address of second from the bottom section and power on writing time by step 2, three, four toward backtracking first good full piece again from initial block address, the rest may be inferred can obtain starting block address, end block address, the chip select address of whole all data segments of storer and power on writing time, according to starting block address, end block address, chip select address, can calculate the size of data of this data segment, can reach the visual of data segment, and intelligent selections operation.
3. the implementation method of NANDFLASH storer automatic cycle as claimed in claim 2 storage, it is characterized in that, described response instruction is first the good empty block address that finds this NANDFLASH, and this address is back being fallen of finding and write the block address that has expired data.
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