CN103399831B - The implementation method that NANDFLASH storer automatic cycle stores - Google Patents
The implementation method that NANDFLASH storer automatic cycle stores Download PDFInfo
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Abstract
The invention discloses the implementation method that a kind of NANDFLASH storer automatic cycle stores, it comprise storage system power on record flow process and memory system data playback read flow process, utilize NANDFLASH as massive store carrier, adopt FPGA as control and data handling system, for realizing the recurrent wrIting of data, circulation is read and circulation is wiped and bad block detects, and adopts USB2.0 Serial technology to realize the high-speed playback of Large Volume Data; By real-time clock to data timing, realize host computer and data visualization selections are read.The present invention can overcome disadvantages such as slowly, manually wiping for Large Volume Data reading, cannot circulate storage, reading manner are intelligent not, meets the demand that following aviation data actuation high-capacity and high-speed data store, manage.
Description
Technical field
The present invention relates to a kind of massive store control technology, be applicable to the missile-borne mass storage system possessing the storage of data automatic cycle, specifically relate to the implementation method that a kind of NANDFLASH storer automatic cycle stores.
Background technology
Along with the development of aeronautical technology, for number adopt, register system input signal type variation, hyperchannel, high sampling rate, no matter missile-borne, spaceborne or carrier-borne measurement requirement, a kind of memory capacity of equal active demand is large, data are preserved, erasing is intelligent, and digital independent is memory device fast, easily.And be applied to the digital data recording system of missile-borne at present, usually cannot store by automatic cycle, selections reading cannot be carried out to data segment.
Summary of the invention
The present invention is directed to the demand, a kind of novel mass data storage control technology is provided, the data capacity of digital data recording system can be made larger, the automatic cycle that better can perform data stores, data management is more intelligent, the speed of data readback is faster, more convenient, effectively can solve the high request of Aviation Test to digital data recording system.
The present invention takes following technical scheme, a kind of implementation method of NANDFLASH storer, control the signal with data processing module Received signal strength source and real-time clock module, and be connected with data readback module, mass data storage module by signal respectively, mass data storage module is connected with data readback module by signal; Described control and data processing module complete Received signal strength source image data and form 64 × 32 standard telemetry frame formatted datas, for high-capacity storage module provides reading and writing and erasing sequential; Comprise storage system power on record flow process and memory system data playback read flow process;
Described storage system powers on record flow process, and its job step is as follows:
The first step: find high-capacity storage module system initial block address and chip select address, and as upper electrographic initial address;
Second step: write data head, by power-on time data inserting head;
3rd step: periodic receipt data also with standard telemetry frame form framing, are inserted this upper electrographic initial address in current frame format; Data write in high-capacity storage module, often perform a cycle, page counting adds one, if do not met 64 pages, continues execution the 3rd step;
4th step: when page counting full 64 time write full one piece, whether the data in 1000 block address after this block address of Real-Time Monitoring are empty, if not empty then obliterated data, store and bad block real-time detection function with the circulation reaching data;
Flow process is read in described memory system data playback, and its job step is as follows:
The first step: PC sends instruction to control and data processing module by data readback module;
Second step: response instruction;
3rd step: the first page data of taking out the good full block address of first of back being found by system initial block address, and take out the initial block address of this data segment contained inside this page data;
4th step: the first page data of taking out current data section initial block address, takes out powering on writing time of the current data section contained inside this initial frame;
5th step: find out starting block address, end block address, the chip select address of second from the bottom section and power on writing time from initial block address toward backtracking the step 2, three, four that first good full block read flow process by described memory system data playback again, the rest may be inferred can obtain starting block address, end block address, the chip select address of all data segments of whole storer and power on writing time, the size of data of this data segment can be calculated according to starting block address, end block address, chip select address, the visual of data segment can be reached, and intelligent selections operation.
Described response instruction finds first of this NANDFLASH good empty block address, and back upside down of finding from this address and write the block address having expired data.
Beneficial effect acquired by the present invention is, utilize NANDFLASH as massive store carrier, adopt FPGA as control and data handling system, for realizing the recurrent wrIting of data, circulation is read and circulation is wiped and bad block detects, and adopts USB2.0 Serial technology to realize the high-speed playback of Large Volume Data; By real-time clock to data timing, realize host computer and data visualization selections are read.Disadvantages such as Large Volume Data reading slowly, manually being wiped, cannot circulate storage, reading manner are intelligent not can be overcome, meet the demand that following aviation data actuation high-capacity and high-speed data store, manage.
Accompanying drawing explanation
Fig. 1 electrical relation of the present invention connects block diagram.
Fig. 2 K9WAG08U1B section organization chart.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described, see Fig. 1 and Fig. 2, NANDFLASH storer, comprise and controlling and data processing module 1, data readback module 3, mass data storage module 2 and real-time clock module 4, it is characterized in that, the signal of described control and data processing module 1 Received signal strength source 5 and real-time clock module 4, and be connected with described data readback module 3, described mass data storage module 2 signal respectively, described mass data storage module 2 is connected with described data readback module by signal 3.
Described control and data processing module 1 complete Received signal strength source image data and form 64 × 32 standard telemetry frame formatted datas, for high-capacity storage module provides reading and writing and erasing sequential;
Described high-capacity storage module 2 completes the storage of real-time frame structured data;
Described data readback module 3 completes the serial port command receiving and send USB; The reading of the data of mass storage and erasing; The transmission of usb data and reception;
Described real-time clock module 4 is for providing the standard time to frame structure in real time.
NANDFLASH memory operation principle of the present invention is as follows:
Control the analog quantity or the digital quantity signal that accept whole system under test (SUT) with data processing module in real time, same period real-time clock send time signal to control and data processing module, and data by concrete frame format requirement composition standard telemetry frame.Within each cycle, telemetry frame is sent to high-capacity storage module real-time storage, high-capacity storage module return in real time can write address give control and data processing module.When data readback, data readback module is connected to PC by USB extended line, PC sends instruction to control and data processing module by this data readback module, when control with data processing module receive read data command time, control to read high-capacity storage module data with data processing module, and send to PC by data readback module in real time.
Implementation method of the present invention, comprise storage system power on record flow process and memory system data playback read flow process,
Described storage system powers on record flow process, and its job step is as follows:
The present invention is when system electrification record performs recurrent wrIting data:
Step one: control first to find an empty good address block to high-capacity storage module with data processing module, and export chip select address, and using this block address and chip select address as upper electrographic initial address.
Step 2: write the data of one page as data head, this page comprises the real-time time that powers on from real-time clock module, the information such as data frame format size.
Step 3: system periodic receipt data with standard telemetry frame form framing, and the initial address powered on is inserted in current frame format.When data reach the data volume of one page, data write in high-capacity storage module NANDFALSH, often perform a cycle, page counting adds one, does not meet 64 pages, continues execution the 3rd step.
Step 4: when page counting full 64 time, namely write full one piece, whether the data in 1000 block address after this block address of Real-Time Monitoring are empty, if not empty then obliterated data, by that analogy.Store and bad block real-time detection function with the circulation reaching data.
When system is in data readback (reading) function:
Step one: PC sends instruction to control and data processing module by data readback module.
Step 2: response instruction, finds the empty block address that first of this NANDFLASH good, and back upside down of finding from this address and write the block address (F1_Adress) having expired data.
Step 3: the first page data of taking out (F1_Adress) block address, takes out the initial block address (init1_Adress) containing this final data data segment inside this page data.
Step 4: the first page data of taking out (init1_Adress) initial block address, takes out powering on writing time containing this data segment inside this initial frame.
Step 5: find out starting block address, end block address, the chip select address of second from the bottom section by step 2, three, four from (init1_Adress) initial block address toward backtracking first good full block and power on writing time, the rest may be inferred can obtain starting block address, end block address, the chip select address of all data segments of whole NANDFLASH storer and power on writing time, the size of data of this data segment can be calculated according to starting block address, end block address, chip select address, the visual of data segment can be reached, and intelligent selections operation.
The implementation method that the time NANDLFLASH storer automatic cycle that this programme solves stores, needs the problem solved substantially to divide two pieces:
First is when how to allow data can not waste resource, realizes write data limit, limit obliterated data, and the data recorded before can retaining as much as possible;
Second is how to enable the data of storage read out easily in this case, but also can reach and arbitrarily select data segment to read.
Embodiment of the present invention are, are divided into by functional module: control and data processing module, data readback module, mass data storage module and real-time clock module.Control and data processing module employing large scale integrated chip (LSI chip) FPGA(complex programmable logic gate array) realize, Samsung NANDFLASH chip is adopted to realize mass data storage module, data readback module adopts USB2.0 control chip, as the control module of data importing computer.Adopting can the continuous working real-time timepiece chip of more than 5 years from charged pool.Fig. 1 is that mass storage control system connects block diagram.
Nucleus module of the present invention is high-capacity storage module, namely NANDFLASH flash chip, and NANDFLASH flash chip is for K9WAG08U1B, divide two sections, by two sheet selected control systems, each section is 8192 blocks, each block is by 64 pages, and every one page is made up of (2K+64) byte.Be illustrated in figure 2 a section: a section is longitudinally superposed by 8192 block _ 201 and forms, 64 page register _ 207 are combined into one piece, each page register is formed by 2K byte _ 204 and the merging of 64 bytes 205 respectively, therefore each section is made up of 0.5M page _ 206, and data I/O port address is 8 202 and is specially I/O0-I/O7203.
The write of NANDFLASH flash chip, reading data carry out based on page writing and reading, and therefore make page programme and page reading, erasing, based on block, therefore makes block wipe.Just may occur in the process of erasing during the appearance of NANDFLASH bad block, therefore carry out the sign of bad block when block erasing.
The job step of native system is as follows:
When system performs circulation storage.Control first to find an empty good address block to high-capacity storage module with data processing module, and export chip select address, and using this block address and chip select address as this upper electrographic initial address.Write the data of one page as this segment data head, this page comprises the real-time time that powers on from real-time clock module, the information such as data frame format size; System periodic receipt data with standard telemetry frame form framing, and the initial address that this time powers on is inserted in current frame format.When data reach the data volume of one page, data write in high-capacity storage module NANDFLASH, often perform a cycle, page counting adds one.When page counts full 64, namely write full one piece, page counting resets, and whether the data in 1000 block address after this block address of Real-Time Monitoring are sky, then clash this blocks of data if not empty, by that analogy.Store and bad block real-time detection function with the circulation reaching data.
When system is in data readback (reading) function.PC sends instruction to control and data processing module by data readback module, response instruction, finds the empty block address that first of this NANDFLASH good, and this address back upside down of finding and writes the block address having expired data, for storage system goes up last full block address of the data segment of electrographic data for the last time, take out the first page data of last full block address, the data mode according to write is learnt, the initial block address containing this final data data segment inside this page data, take out the first page data of the initial block address of final data data segment, the data mode according to write is learnt, this page data is the head initial frame of this last segment data, and the writing time that powers on containing this data segment inside this initial frame, from the initial block address of final data section toward backtracking first good full block, deducibility goes out, this good full block is the full data block of the last moment of second from the bottom period, and inside this data block, comprise the initial address of this data segment, take out the first page data of initial block address, powering on writing time of this data segment can be learnt, the rest may be inferred can obtain the starting block address of all data segments of whole NANDFLASH storer, end block address, chip select address and powering on writing time, according to starting block address, end block address, chip select address can calculate the size of data of this data segment.
Therefore the data frame head by finding out every section reads starting block address, the end address of every segment data, and power-on time, can realize the visual intelligent selections read functions of data.USB2.0 data readback module is as the bridge of PC and storer, as host computer and the transmission instruction of mass-storage system and the transmission of response instruction, major function is that a large amount of memory datas is uploaded to PC at short notice fast, to realize the quick playback of data.
Be no matter NANDFLASH Large Copacity write data or read data, what first complete is searching to first good empty block (storage system initial address), and concrete implementation is as follows:
System for NANDFLASH model for K9WAG08U1B, it has two sections (Flash_Num), 8192, every section block, and storage system is that to carry out circulation in real time stored program in upper electrographic recording, namely whenever having stored 1 blocks of data, just wipe that block of latter 1000 pieces.Thus keep the empty block of 1000 pieces in real time.The method of just having looked for first empty good block during upper electrographic recording separates four kinds of situations, respectively:
1) look for first good block from the 0th piece of first section, whether first good block is empty, if whether sky then looks for the 2000th piece to be empty, if it is empty for being also the empty whole FLASH of explanation.System initial address is first good block of first section;
2) look for first good block from the 0th piece of first section, whether first good block is empty, if whether sky then looks for the 2000th piece to be empty, illustrate that if not sky the head of first section of whole FLASH is empty, the tail of second section may be empty.The good block empty from first, second section is as system initial address;
3) look for first good block from the 0th piece of first section, first good block is not sky block, from first good block address, look for sky block.Look for a section not find sky block, illustrated that this section is full, from the empty block that 0 piece, the ground of next section finds, and as system initial address;
4) look for first good block from the 0th piece of first section, first good block is not sky block, from first good block address, look for sky block.Find empty good block from this section, illustrate this section less than, using the address of empty block as system initial address.
The steering order that the playback of memory system data is read has three, respectively:
1) data are read in selections: the random selections that the method well can solve data are read, more humane operation, containing paragraph to be read inside instruction, after system acceptance to instruction, initial address and the end address of this paragraph data is found at once by paragraph, find this paragraph data, and send to PC by USB;
2) show full segment data title: by finding the power-on time of each paragraph, state pause judgments block address and chip select address, and this information is sent to PC by USB, well can realize visualized operation;
3) all wipe: the data emptying whole mass storage.
Claims (2)
1. the implementation method of a NANDFLASH storer automatic cycle storage, control the signal with data processing module Received signal strength source and real-time clock module, and be connected with data readback module, mass data storage module by signal respectively, mass data storage module is connected with data readback module by signal; Described control and data processing module complete Received signal strength source image data and form 64 × 32 standard telemetry frame formatted datas, for high-capacity storage module provides reading and writing and erasing sequential; It is characterized in that, comprise storage system power on record flow process and memory system data playback read flow process;
Described storage system powers on record flow process, and its job step is as follows:
The first step: find high-capacity storage module system initial block address and chip select address, and as upper electrographic initial address;
Second step: write data head, by power-on time data inserting head;
3rd step: periodic receipt data also with standard telemetry frame form framing, are inserted this upper electrographic initial address in current frame format; Data write in high-capacity storage module, often perform a cycle, page counting adds one, if do not met 64 pages, continues execution the 3rd step;
4th step: when page counting full 64 time write full one piece, whether the data in 1000 block address after this block address of Real-Time Monitoring are empty, if not empty then obliterated data, store and bad block real-time detection function with the circulation reaching data;
Flow process is read in described memory system data playback, and its job step is as follows:
The first step: PC sends instruction to control and data processing module by data readback module;
Second step: response instruction;
3rd step: the first page data of taking out the good full block address of first of back being found by system initial block address, and take out the initial block address of the data segment contained inside this page data;
4th step: the first page data of taking out current data section initial block address, takes out powering on writing time of the current data section contained inside initial frame;
5th step: find out starting block address, end block address, the chip select address of second from the bottom section and power on writing time from initial block address toward backtracking the step 2, three, four that first good full block read flow process by described memory system data playback again, the rest may be inferred can obtain starting block address, end block address, the chip select address of all data segments of whole storer and power on writing time, the size of data of this data segment can be calculated according to starting block address, end block address, chip select address, the visual of data segment can be reached, and intelligent selections operation.
2. the implementation method of NANDFLASH storer automatic cycle storage as claimed in claim 1, it is characterized in that, described response instruction finds first of this NANDFLASH good empty block address, and back upside down of finding from this address and write the block address having expired data.
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| CN1287290C (en) * | 2003-07-15 | 2006-11-29 | 中兴通讯股份有限公司 | Dynamic allocation method for non-buffering memory in embedded real-time operating system |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
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| CN1287290C (en) * | 2003-07-15 | 2006-11-29 | 中兴通讯股份有限公司 | Dynamic allocation method for non-buffering memory in embedded real-time operating system |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
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