CN103390543A - Method for increasing surface area of inductor - Google Patents
Method for increasing surface area of inductor Download PDFInfo
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- CN103390543A CN103390543A CN2013103209847A CN201310320984A CN103390543A CN 103390543 A CN103390543 A CN 103390543A CN 2013103209847 A CN2013103209847 A CN 2013103209847A CN 201310320984 A CN201310320984 A CN 201310320984A CN 103390543 A CN103390543 A CN 103390543A
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Abstract
The invention discloses a method for increasing a surface area of an inductor. The method comprises the steps that a silicon wafer with a first area and a second area is provided, wherein the first area comprises a lamination layer of a first oxide layer and a second oxide layer, and the second area comprises lamination layers of the first oxide layer, a middle metal layer and the second oxide layer; strip-shaped wire lead grooves are etched in the second oxide layer of the first area when circuit wire lead holes are etched in the second area; tungsten layers are formed at the bottoms and on side walls of the strip-shaped lead wire grooves when tungsten is settled in the circuit wire lead holes; aluminum is settled after the tungsten layers are subjected to chemical-mechanical grinding, so that an aluminum layer is formed on the second oxide layer; the strip-shaped lead wire grooves are filled, so that the second oxide layer isolated by the strip-shaped lead wire grooves is connected due to the fact that the strip-shaped lead wire grooves are filled; and gaps formed by the strip-shaped lead wire grooves in the second oxide layer are not filled completely.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of method that increases the surface area of inductance.
Background technology
Skin effect also is called " kelvin effect ".Specifically, when alternating current (alternatingelectric current, AC) passed through conductor, because induction effect causes that on cross-sectional area of conductor, CURRENT DISTRIBUTION is inhomogeneous, the nearly conductive surface current density that heals was larger; This phenomenon claims " skin effect ".Skin effect increases the effective resistance of conductor.When the very high electric current of frequency during by wire, can think that electric current only flows through in very thin one deck on conductive line surfaces, this cross section that is equivalent to wire reduces, and resistance increases.
Skin depth refers to that the current density under this degree of depth is the 1/e of surface current density, namely 0.368 times, be not there is no electric current. surpass after the twice of skin depth the thickness that increases wire limited but be not useless to increasing the Q value, when 1GHz, the skin depth of Al is 2.8um.
For the alternating current in conductor, the current density at close conductive surface place is greater than the phenomenon of conductor internal current density.Along with the raising of power frequency, skin effect increases the resistance of conductor, and inductance reduces.
Prior art has proposed a kind of method of the Litz of being called coiling, the method can effectively improve the Q value (particularly in the situation that high frequency) of inductance, the method of existing techniques in realizing Litz coiling is to adopt the method for photoetching and etching to realize the multiply coiling, yet be subject to lithographic dimensioned and the ability etching processing procedure, distance between the coiling that the method realizes can be larger, and density is lower.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, provides a kind of and can realize high density Litz coiling by simple process, increases the method for the surface area of inductance.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of high density Litz wire-wound inductor method, it comprises:
First step: the silicon chip with first area and second area is provided, and wherein first area comprises the lamination of the first oxide skin(coating) and the second oxide skin(coating), and second area comprises the lamination of the first oxide skin(coating), intermediate metal layer and the second oxide skin(coating);
Second step: in second area in the etched circuit fairlead, etching strip wire lead slot in the second oxide skin(coating) of first area;
Third step: in the circuit lead hole in deposits tungsten, form tungsten layer on the bottom of strip wire lead slot and sidewall;
The 4th step: thus deposition of aluminum forms aluminium lamination on the second oxide skin(coating) after tungsten layer being carried out cmp, simultaneously described strip wire lead slot is filled, so that described the second oxide skin(coating) that is separated by described strip wire lead slot is because the filling to described strip wire lead slot connects, wherein said strip wire lead slot forms in described the second oxide skin(coating) gap is not completely filled.
Preferably, the width of described strip wire lead slot be greater than or equal to described strip wire lead slot thickness 1/3rd.
Preferably, form many parallel described strip wire lead slots in second step.
Preferably, the first oxide skin(coating) and the second oxide skin(coating) are all silicon dioxide layers.
In the method for the invention,, by forming the strip wire lead slot, single inductance can be become the inductance of multiply structure; Increased effective surface area, improved the performance of inductance, the structure of simultaneously this multiply coiling can be accomplished maximum coiling density.
Thus, the invention provides a kind ofly can increase the surface area of inductance and the list of inductance coiling be become the methods of many coilings by simple process, and the method can effectively increase the Q value of inductance.
Description of drawings
By reference to the accompanying drawings, and, by reference to following detailed description, will more easily to the present invention, more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the flow chart according to the method for the surface area of the increase inductance of the embodiment of the present invention.
Fig. 2 to Fig. 5 schematically shows each step according to the method for the surface area of the increase inductance of the embodiment of the present invention.
Need to prove, accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Note, the accompanying drawing of expression structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
, in order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 1 schematically shows the flow chart according to the method for the surface area of the increase inductance of the embodiment of the present invention.
Specifically, as shown in Figure 1, according to the method for the surface area of the increase inductance of the embodiment of the present invention, comprise:
First step S1: the silicon chip with first area and second area is provided, wherein first area comprises the lamination of the first oxide skin(coating) 100 and the second oxide skin(coating) 10, second area comprises the lamination of the first oxide skin(coating) 100, intermediate metal layer 200 and the second oxide skin(coating) 10, as shown in the sectional view of Fig. 3, the dotted line left side belongs to first area, and the dotted line right side belongs to second area;
Wherein, for example, the first oxide skin(coating) 100 and the second oxide skin(coating) 10 are all silicon dioxide layers.
Second step S2: in second area in etched circuit fairlead 21, etching strip wire lead slot 20 in the second oxide skin(coating) 10 of first area.
Wherein, first area does not have intermediate metal layer 200 as etching barrier layer, and strip wire lead slot 20 can enter described the first oxide skin(coating) 100; Have the intermediate metal layer 200 as etching barrier layer in second area, circuit lead hole 21 stops at intermediate metal layer 200, and as shown in Figures 2 and 3, wherein Fig. 2 is vertical view, and Fig. 3 is sectional view;
In the present invention, the width of described strip wire lead slot 20 is larger.Preferably, in the preferred embodiment of the present invention, the width of described strip wire lead slot 20 be greater than or equal to described strip wire lead slot 20 thickness 1/3rd.
Wherein, preferably, form many parallel described strip wire lead slots 20 in second step S2.
Preferably, the circuit lead hole (through hole) that described second step S2 can be integrated in the semiconductor manufacturing forms in technique, thereby need not to add new processing step,
Third step S3: in deposits tungsten in circuit lead hole 21 (tungsten fills up circuit lead hole 21 fully), form tungsten layer 31 on the bottom of strip wire lead slot 20 and sidewall.Described third step S3 can be integrated in the tungsten depositing operation of the fairlead (through hole) that semiconductor makes, thereby need not to add new processing step.
The 4th step S4: tungsten layer 31 is carried out cmp (CMP) thus deposition of aluminum forms aluminium lamination 40 on the second oxide skin(coating) 10 afterwards, simultaneously described strip wire lead slot 20 is filled, so that described the second oxide skin(coating) 10 that is separated by described strip wire lead slot 20 is because the filling to described strip wire lead slot 20 connects, wherein said strip wire lead slot 20 forms in described the second oxide skin(coating) 10 gap is not completely filled (that is, the technique of deposition of aluminum only is partially filled the gap that forms in described the second oxide skin(coating) 10).
In the 4th step S4, because strip wire lead slot 20 is spaced apart, so the aluminium lamination 40 that forms on the second oxide skin(coating) 10 forms cutting apart of nature, thereby the aluminium lamination 40 of formation inductance is formed the induction structure of multiply structure.
Like this, in the method for the above embodiment of the present invention, by the strip wire lead slot, form inductance, wherein, by forming the strip wire lead slot, single inductance can be become the inductance of multiply structure; And, due to the appearance of the second oxide skin(coating) sidewall (referring to the sidewall 41 of Fig. 5) of strip wire lead slot both sides, increased effective surface area, and having improved the performance of inductance, the structure of simultaneously this multiply coiling can be accomplished maximum coiling density.And of the present invention all being integrated in steps in the manufacturing process of circuit through hole, can not increase new technique or cost.
Thus, above preferred embodiment of the present invention provides a kind of method that increases the surface area of inductance and the coiling of the list of inductance is become many coilings, and the method can effectively increase the Q value of inductance.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, step or ordinal relation etc.
Be understandable that, although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not breaking away from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention,, all still belong in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (4)
1. method that increases the surface area of inductance is characterized in that comprising:
First step: the silicon chip with first area and second area is provided, and wherein first area comprises the lamination of the first oxide skin(coating) and the second oxide skin(coating), and second area comprises the lamination of the first oxide skin(coating), intermediate metal layer and the second oxide skin(coating);
Second step: in second area in the etched circuit fairlead, etching strip wire lead slot in the second oxide skin(coating) of first area;
Third step: in the circuit lead hole in deposits tungsten, form tungsten layer on the bottom of strip wire lead slot and sidewall;
The 4th step: thus deposition of aluminum forms aluminium lamination on the second oxide skin(coating) after tungsten layer being carried out cmp, simultaneously described strip wire lead slot is filled, so that described the second oxide skin(coating) that is separated by described strip wire lead slot is because the filling to described strip wire lead slot connects, wherein said strip wire lead slot forms in described the second oxide skin(coating) gap is not completely filled.
2. the method for the surface area of increase inductance according to claim 1, is characterized in that, the width of described strip wire lead slot be greater than or equal to described strip wire lead slot thickness 1/3rd.
3. the method for the surface area of increase inductance according to claim 1 and 2, is characterized in that, forms many parallel described strip wire lead slots in second step.
4. the method for the surface area of increase inductance according to claim 1 and 2, is characterized in that, the first oxide skin(coating) and the second oxide skin(coating) are all silicon dioxide layers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310320984.7A CN103390543B (en) | 2013-07-26 | 2013-07-26 | A kind of method for the surface area for increasing inductance |
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| CN201310320984.7A CN103390543B (en) | 2013-07-26 | 2013-07-26 | A kind of method for the surface area for increasing inductance |
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| CN103390543A true CN103390543A (en) | 2013-11-13 |
| CN103390543B CN103390543B (en) | 2017-11-24 |
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Citations (9)
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|---|---|---|---|---|
| US6444517B1 (en) * | 2002-01-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | High Q inductor with Cu damascene via/trench etching simultaneous module |
| US6667217B1 (en) * | 2001-03-01 | 2003-12-23 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process |
| US20060022787A1 (en) * | 2004-07-30 | 2006-02-02 | Brennan Kenneth D | Method to improve inductance with a high-permeability slotted plate core in an integrated circuit |
| TW200625596A (en) * | 2005-01-03 | 2006-07-16 | Samsung Electronics Co Ltd | Inductor and method of forming the same |
| US20080048289A1 (en) * | 2006-08-28 | 2008-02-28 | Han Choon Lee | RF Inductor of Semiconductor Device and Fabrication Method Thereof |
| CN101145511A (en) * | 2006-09-13 | 2008-03-19 | 东部高科股份有限公司 | Method of manufacturing inductor |
| CN101465335A (en) * | 2007-12-20 | 2009-06-24 | 松下电器产业株式会社 | Inductor and manufacturing method threof |
| CN102165576A (en) * | 2008-09-26 | 2011-08-24 | 罗姆股份有限公司 | Semiconductor device and semiconductor device manufacturing method |
| US20120267794A1 (en) * | 2010-11-01 | 2012-10-25 | International Business Machines Corporation | Structure and design structure for high-q value inductor and method of manufacturing the same |
-
2013
- 2013-07-26 CN CN201310320984.7A patent/CN103390543B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667217B1 (en) * | 2001-03-01 | 2003-12-23 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process |
| US6444517B1 (en) * | 2002-01-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | High Q inductor with Cu damascene via/trench etching simultaneous module |
| US20060022787A1 (en) * | 2004-07-30 | 2006-02-02 | Brennan Kenneth D | Method to improve inductance with a high-permeability slotted plate core in an integrated circuit |
| TW200625596A (en) * | 2005-01-03 | 2006-07-16 | Samsung Electronics Co Ltd | Inductor and method of forming the same |
| US20080048289A1 (en) * | 2006-08-28 | 2008-02-28 | Han Choon Lee | RF Inductor of Semiconductor Device and Fabrication Method Thereof |
| CN101145511A (en) * | 2006-09-13 | 2008-03-19 | 东部高科股份有限公司 | Method of manufacturing inductor |
| CN101465335A (en) * | 2007-12-20 | 2009-06-24 | 松下电器产业株式会社 | Inductor and manufacturing method threof |
| CN102165576A (en) * | 2008-09-26 | 2011-08-24 | 罗姆股份有限公司 | Semiconductor device and semiconductor device manufacturing method |
| US20120267794A1 (en) * | 2010-11-01 | 2012-10-25 | International Business Machines Corporation | Structure and design structure for high-q value inductor and method of manufacturing the same |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140506 |
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Effective date of registration: 20140506 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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