CN103389456B - Method for testing and scheduling hard-core-based three-dimensional SoC (system on chip) under constraint of power consumption - Google Patents

Abstract

The invention relates to a method for testing and scheduling a hard-core-based three-dimensional SoC under the constraint of power consumption, belongs to the technical field of three-dimensional SoC testing and scheduling, and solves the problem that the testing time of the three-dimensional SoC cannot be optimized under the condition that the three-dimensional SoC simultaneously comprises coarse-grained IP cores and fine-grained IP cores. The method specifically comprises the process as follows: the hard-core-based three-dimensional SoC comprises the coarse-grained IP cores and the fine-grained IP cores; a three-dimensional SoC testing and scheduling mathematical model is established, and xij represents a binary variable; if an i IP core and a j IP core are in parallel test, xij is equal to one, and otherwise, xij is equal to zero; tj is the testing time of the j IP core, and the absolute value of M represents the sum of IP cores in the SoC and shows the maximum value of IP core testing time in parallel test; yi represents a binary variable, and the mark number j of the IP core is smaller than the mark number I; if any j IP core and any i IP core are in parallel test, yi is equal to zero, and otherwise, yi is equal to one; and a variable and ui which is equal to yiici are introduced to linearize the mathematical model, and the minimum of T is calculated by an ILP (integer linear programming) tool according to a constraint condition. The method is applicable to three-dimensional SoC testing and scheduling.

Description

Based on the D S oC test dispatching method of stone under power constraints

Technical field

The invention belongs to D S oC test dispatching technical field.

Background technology

In recent years, the increase of footprint and the integrated of chip that be reduced to of characteristic dimension are had higher requirement.The multiplexing thought of the integrated general application IP (Intellectual Property) of D S oC, on the basis of conventional two-dimensional SoC, with signal between through-silicon-via (Through-Silicon Via, TSV) transport layer, complete the integrated of D S oC by the binding between many device layers.

For ensureing the reliability of D S oC, need to carry out design for Measurability to it.Design for Measurability is divided into three parts: Test access mechanism (Test Access Mechanism, TAM), test package and test dispatching.Be different from two-dimentional SoC to test, D S oC is due to the singularity of structure and integrated technology, and its test needs the IP kernel considering to pass through multilayer; The high power consumption that multilayer integrated causes and heat dissipation problem, also easily cause chip local temperature too high, defective chip performance.Therefore, design for Measurability also will at consideration power consumption and temperature restraint.SoC test finally will implement to the test of each IP kernel, and also determine first survey which layer with a mathematical algorithm, which IP kernel which layer of rear survey, first survey, which IP kernel of rear survey, the test dispatching of Here it is D S oC.D S oC test dispatching is IP kernel testing sequence of making rational planning for, and reduces the time cost of SoC test, ensures one of important method of test high efficiency.

At present, Chinese scholars has carried out a series of research work for the test dispatching problem of three-dimensional IP kernel.In these researchs, people consider different restrictive conditions respectively, use different optimization methods, classical two-dimentional test dispatching method can be applied due to the test dispatching before binding to realize, so prior art is mostly it is considered that the shortest time of test after binding, some tests and binds rear test synthesis and considers before binding, and intends the minimum value obtaining the two test duration sum from the angle of the overall situation.Some thinks that the quantity of d type flip flop and test duration are a pair important contradiction in test process, therefore takes advantage of power to be added to above two factors, calculates a Cost value, Cost value under optimization different situations.

Three-dimensional IP kernel is divided into coarseness and fine granularity two kinds of situations.So-called coarseness, refers to that in IP kernel, all resources are all arranged in the some device layers of D S oC, very similar to two-dimentional IP kernel, and just its input, output and control signal may from other device layers.Then corresponding IP kernel resource is across the situation of multilayer for fine granularity IP kernel, and the scan chain in IP kernel also can cross over different device layers, is three-dimensional IP kernel truly.In existing research, the IP kernel that different grain size divides difference all to some extent on structure design of test and test dispatching, prior art is only containing coarseness or only study D S oC test dispatching containing when fine granularity IP kernel.

Summary of the invention

The present invention to comprise coarseness, fine granularity IP kernel to solve in D S oC simultaneously, the problem that cannot be optimized the test duration of D S oC, proposes the D S oC test dispatching method based on stone under power constraints.

Based on the D S oC test dispatching method of stone under power constraints, the detailed process of described method is:

Step one: the D S oC based on stone comprises coarseness IP kernel and fine granularity IP kernel, first fine granularity IP kernel is considered as the multiple parts on each layer, part on every layer is equivalent to a coarseness IP kernel, by all coarseness IP kernels and fine granularity IP kernel, the part on each layer is unified is numbered, and sets up the mathematical model of D S oC test dispatching

$T=\underset{i=1}{\overset{\left|M\right|}{\mathrm{\Σ}}}{y}_i\·\left({\max }_{j=i}^{\left|M\right|}\right\{x_{\mathrm{ij}}\·t_j\left\}\right),$

Wherein | M| represents the IP kernel sum in a SoC, x _ijrepresent a binary variable, when being numbered the IP kernel of i and being numbered the IP kernel concurrent testing of j, then x _ijvalue is 1, otherwise x _ijvalue is that 0, i and j is 1 and arrives | any positive integer between M|, t _jfor being numbered the test duration of the IP kernel of j, represent the maximal value of each IP kernel test duration of concurrent testing,

Y _irepresent a binary variable, there is the IP kernel being numbered i, if there is arbitrary number is the IP kernel of j and the IP kernel concurrent testing being numbered i, wherein j<i, with IP kernel i concurrent testing, then y _ivalue be 0; Otherwise y _ivalue be 1;

Step 2: introduce variable

$c_i={\max }_{j=i}^{\left|M\right|}\{x_{\mathrm{ij}}\&CenterDot;t_j\}$ And u _i=y _ic _i,

By the mathematical model linearization in step one, obtain wherein c _irepresent the maximal value being numbered the IP kernel test duration of i of concurrent testing, u _irepresent and introduce variable y _iafter the maximal value being numbered the IP kernel test duration of i,

Try to achieve the minimum value of the test duration T of whole SoC according to constraint condition, namely obtain the testing sequence of IP kernel, then dispatch IP kernel to be measured successively according to this testing sequence and realize SoC test dispatching.

The present invention considers the concrete feature of different grain size IP kernel, studies the situation simultaneously comprising coarseness, fine granularity IP kernel in a D S oC, proposes D S oC test dispatching method.

According to scale, the arrangement information of each IP kernel, under power consumption constraint, by setting up and solve the testing sequence of each IP kernel in mathematical model determination D S oC, calculate scheduling result with ILP instrument.Experiment on ITC ' 02 regular set shows, under the restriction of constraint condition, the testing sequence of this test dispatching method reasonable arrangement IP kernel, optimizes the test duration of SoC from macroscopic perspective.

Accompanying drawing explanation

Fig. 1 under the power constraints described in embodiment one based on the process flow diagram of the D S oC test dispatching method of stone;

Fig. 2 is the structural representation simultaneously comprising coarseness and fine granularity IP kernel in D S oC;

Fig. 3 is that the power consumption of IP2 in Fig. 2 is divided into the two-part structural representation of IP2A and IP2B by device layer;

Fig. 4 is experimental result picture.

Embodiment

Embodiment one: present embodiment is described see Fig. 1, based on the D S oC test dispatching method of stone under the power constraints described in present embodiment, the detailed process of described method is:

Step one: the D S oC based on stone comprises coarseness IP kernel and fine granularity IP kernel, first fine granularity IP kernel is considered as the multiple parts on each layer, part on every layer is equivalent to a coarseness IP kernel, by all coarseness IP kernels and fine granularity IP kernel, the part on each layer is unified is numbered, and sets up the mathematical model of D S oC test dispatching

$T=\underset{i=1}{\overset{\left|M\right|}{\mathrm{\&Sigma;}}}{y}_i\&CenterDot;\left({\max }_{j=i}^{\left|M\right|}\right\{x_{\mathrm{ij}}\&CenterDot;t_j\left\}\right),$

Wherein | M| represents the IP kernel sum in a SoC, x _ijrepresent a binary variable, when being numbered the IP kernel of i and being numbered the IP kernel concurrent testing of j, then x _ijvalue is 1, otherwise x _ijvalue is that 0, i and j is 1 and arrives | any positive integer between M|, t _jfor being numbered the test duration of the IP kernel of j, represent the maximal value of each IP kernel test duration of concurrent testing,

Y _irepresent a binary variable, there is the IP kernel being numbered i, if there is arbitrary number is the IP kernel of j and the IP kernel concurrent testing being numbered i, wherein j<i, with IP kernel i concurrent testing, then y _ivalue be 0; Otherwise y _ivalue be 1;

Step 2: introduce variable

$c_i={\max }_{j=i}^{\left|M\right|}\{x_{\mathrm{ij}}\&CenterDot;t_j\}$ And u _i=y _ic _i,

By the mathematical model linearization in step one, obtain wherein c _irepresent the maximal value being numbered the IP kernel test duration of i of concurrent testing, u _irepresent and introduce variable y _iafter the maximal value being numbered the IP kernel test duration of i,

Try to achieve the minimum value of the test duration T of whole SoC according to constraint condition, namely obtain the testing sequence of IP kernel, then dispatch IP kernel to be measured successively according to this testing sequence and realize SoC test dispatching.

Y in present embodiment _iintroducing avoid IP kernel test duration in summation repeat superposition.Under ILP instrument only can be applied to linear case, so introduce variable and u _i=y _ic _iby model linearization.

Embodiment two: present embodiment be under the power constraints described in embodiment one based on the further restriction of the D S oC test dispatching method of stone, the constraint condition in described step 2 comprises:

$c_i\&GreaterEqual;x_{\mathrm{ij}}\&CenterDot;t_j,\&ForAll;i,j=\mathrm{1,2},...,\left|M\right|,$

$u_i-c_i\&le;0,\&ForAll;i,$

$u_i\&GreaterEqual;0,\&ForAll;i,$

$u_i-t_{\max }\&CenterDot;y_i\&le;0,\&ForAll;i,$

$c_i-u_i+t_{\max }\&CenterDot;y_i\&le;t_{\max },\&ForAll;i,$

$1-x_{\mathrm{ij}}\&GreaterEqual;x_{\mathrm{ik}}-x_{\mathrm{jk}}\&GreaterEqual;x_{\mathrm{ij}}-1,\&ForAll;i,j,k,$

$y_i\&GreaterEqual;\frac{1}{1-i}\underset{j=1}{\overset{i-1}{\mathrm{\&Sigma;}}}(x_{\mathrm{ij}}-1)-C,\&ForAll;i>1,$

Wherein t _maxrepresent the test duration maximal value of all IP kernels, x _ikrepresent a binary variable, when being numbered the IP kernel of i and being numbered the IP kernel concurrent testing of k, then x _ikvalue is 1, otherwise x _ikvalue is that 0, i and k is 1 and arrives | any positive integer between M|, x _jkrepresent a binary variable, when being numbered the IP kernel of j and being numbered the IP kernel concurrent testing of k, then x _jkvalue is 1, otherwise x _jkvalue is that 0, j and k is 1 and arrives | any positive integer between M|, and C is the constant little close to 1 but than 1, and

Embodiment three: present embodiment be under the power constraints described in embodiment one or two based on the further restriction of the D S oC test dispatching method of stone, the constraint condition in described step 2 also comprises namely the test port quantity sum of each concurrent testing IP kernel can not exceed operational TAM total bandwidth W _max, wherein w _irepresent the TAM bandwidth being numbered the test port of the IP kernel of i.

Embodiment four: present embodiment be under the power constraints described in embodiment three based on the further restriction of the D S oC test dispatching method of stone, the constraint condition in described step 2 also comprises

namely each IP kernel testing power consumption sum of concurrent testing can not exceed the power consumption upper limit P that system allows _max, wherein p _irepresent the testing power consumption being numbered the IP kernel of i.

Embodiment five: present embodiment be under the power constraints described in embodiment one based on the further restriction of the D S oC test dispatching method of stone, the part that described each fine granularity IP kernel is positioned in different aspects carries out concurrent testing, namely any fine granularity IP kernel splits into N number of part by level, is designated as IPi respectively ₁, IPi ₂..., IPi _n, then have

$x_{\mathrm{IJ}}=1,\&ForAll;I,J\&Element;\{i_1,i_2,\&CenterDot;\&CenterDot;\&CenterDot;i_N\},$

Wherein x _iJrepresent a binary variable, when being numbered the IP kernel of I and being numbered the IP kernel concurrent testing of J, then x _iJvalue is 1, otherwise x _iJvalue is 0.

Present embodiment is the N number of part parallel test ensureing any fine granularity IP kernel.

IP kernel in the present invention is divided into coarseness IP kernel and fine granularity IP kernel, and the test dispatching of the D S oC containing coarseness IP kernel is similar to the scheduling of two-dimentional SoC, is that temperature and power constraints are relatively strict; When containing fine granularity IP kernel in D S oC, if the resource that same IP kernel is in different components layer is tested respectively, then need to regenerate test vector to the circuit on every one deck, in order to avoid the Self-adaptive repeated, need to ensure that same IP kernel is tested in the resource of different layers simultaneously.

In test dispatching, first fine granularity IP kernel can be considered as the multiple parts on each layer, number respectively each several part, the part on every layer is equivalent to a coarseness IP kernel, then the constraint condition that corresponding increase each several part is tested simultaneously in mathematical model.

The present invention sets up the mathematical model of D S oC test dispatching, the parameters such as each IP kernel serial parallel test relation, test duration, TAM bandwidth are represented with different variablees, power consumption and temperature restraint are incorporated model with the form of boundary condition, solve the process of mathematical model, be the intermediate variable found and meet constraint condition, make the test duration get minimum value, can complete by ILP instrument.

Comprise coarseness and fine granularity IP kernel in D S oC shown in Fig. 2 simultaneously.Wherein, IP kernel 2 is fine granularity IP kernel, and its resource all has distribution two-layer.Ignore the power consumption on TSV, the power consumption of IP kernel 2 is also divided into two parts by device layer, and the power consumption on every layer is directly proportional to resource.IP2 can be considered as IP2A and IP2B two parts shown in Fig. 3 by temperature simulation process, the two concurrent testing.

Constraint condition in test dispatching is except TAM bandwidth, and common also has power consumption and temperature restraint.Power consumption and resource linear, and temperature becomes nonlinear relationship with resource, relative complex.In addition, stone and soft core are also had any different when being applied to test dispatching, and the TAM bandwidth of stone is determined, corresponding unique test duration, and the TAM of soft core is variable, the test duration that each TAM is corresponding differs greatly, and which increases the test dispatching difficulty to soft core.The present invention introduces the D S oC test dispatching algorithm based on stone under power constraints.

Simple explanation is done to the constraint condition in the present invention:

Based in the D S oC test dispatching model of stone under power constraints, when IP kernel i and IP kernel j concurrent testing, if IP kernel k and IP kernel i concurrent testing, then IP kernel k and IP kernel j also concurrent testing.This relation can be expressed as:

$1-x_{\mathrm{ij}}\&GreaterEqual;x_{\mathrm{ik}}-x_{\mathrm{jk}}\&GreaterEqual;x_{\mathrm{ij}}-1,\&ForAll;i,j,k$

Introduce the constraint condition of mathematical model below.Use t _maxrepresent t _imaximal value, the constraint condition relevant to above-mentioned Two Variables has:

$c_i\&GreaterEqual;x_{\mathrm{ij}}\&CenterDot;t_j,\&ForAll;i,j=\mathrm{1,2},...,\left|M\right|$

$u_i\&GreaterEqual;0,\&ForAll;i$

$u_i-t_{\max }\&CenterDot;y_i\&le;0,\&ForAll;i$

$u_i-c_i\&le;0,\&ForAll;i$

Due to 0≤y _i≤ 1, known 1-y _i>=0.At inequality

$t_{\max }\&GreaterEqual;t_i\&GreaterEqual;{\max }_{j=i}^{\left|M\right|}\{x_{\mathrm{ij}}\&CenterDot;t_j\}=c_i,\&ForAll;i$

1-y is multiplied by respectively in both sides _i(1-y _i>=0), obtain

(1-y _i)c _i≤t _max(1-y _i)

Namely

c _i-c _iiy _i≤t _max-t _max·y _i

Finally can be reduced to:

$c_i-u_i+t_{\max }\&CenterDot;y_i\&le;t_{\max },\&ForAll;i$

This is again a constraint condition.In addition, the test bandwidth shared by each IP kernel of concurrent testing, i.e. the test port quantity w of each concurrent testing IP kernel _isum can not exceed operational TAM total bandwidth W _max, that is:

$\underset{j=1}{\overset{\left|M\right|}{\mathrm{\&Sigma;}}}{x}_{\mathrm{ij}}\&CenterDot;w_i\&le;W_{\max },\&ForAll;i$

In like manner, each IP kernel testing power consumption p of concurrent testing _isum can not exceed the power consumption upper limit P that system allows _max, that is:

$\underset{j=1}{\overset{\left|M\right|}{\mathrm{\&Sigma;}}}{x}_{\mathrm{ij}}\&CenterDot;p_i\&le;P_{\max },\&ForAll;i$

According to integer y _iphysical significance, by y _ibe defined by formula as:

y ₁=1

$y_i\&GreaterEqual;\frac{1}{1-i}\underset{j=1}{\overset{i-1}{\mathrm{\&Sigma;}}}(x_{\mathrm{ij}}-1)-C,\&ForAll;i>1$

Wherein C is the constant little close to 1 but than 1.In actual application, reason illustrates in proof.Y is proved below by mathematical induction _iformulism definition.

Prove:

Prove with upper inequality for set up,

1) basic scenario (during i=2)

D S oC only comprises two IP kernels, and the numbering minimum value of IP kernel is 1, there is not IP kernel j and IP kernel 1 concurrent testing that arbitrary numbering is less than 1, y ₁=1, known x simultaneously ₁₁=1, x ₂₂=1.If two IP kernel serial tests, then x ₁₂=0, x ₂₁=0, apply mechanically formula:

$y_2\&GreaterEqual;\frac{1}{1-2}(x_{21}-1)-C$

Obtain:

y ₂≥1-C

Due to the constant that C is little close to 1 but than 1, thus (1-C) for be greater than 0 and close to 0 constant, it can thus be appreciated that binary variable y ₂value can only equal 1.This corresponds to, and to there is not the IP kernel j(that arbitrary numbering is less than 2 may be only IP kernel 1 here) with IP kernel 2 concurrent testing, y ₂=1.Therefore the situation of i=2 must be demonstrate,proved.

2) set up when supposing i=n

When comprising n IP kernel in D S oC, following formula is set up.

y ₁=1

$y_n\&GreaterEqual;\frac{1}{1-n}\underset{j=1}{\overset{n-1}{\mathrm{\&Sigma;}}}(x_{\mathrm{nj}}-1)-C$

3) situation during i=n+1

When comprising (n+1) individual IP kernel in D S oC,

$y_{n+1}\&GreaterEqual;\frac{1}{1-(n+1)}\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}(x_{(n+1)j}-1)-C$

By y _n+1inequality launch obtain:

$y_{n+1}\&GreaterEqual;\frac{1}{1-(n+1)}[(x_{(n+1)1}-1)+(x_{(n+1)2}-1)+...+(x_{(n+1)n}-1)]-C$

Due to the integer that j is from 1 to n change, 1 after each is merged total n item, that is:

$y_{n+1}\&GreaterEqual;\frac{1}{-n}(x_{(n+1)1}+x_{(n+1)2}+{...+x}_{(n+1)n}-n)-C$

If (n+1) individual IP kernel serial test, x _{(n+1) 1}, x _{(n+1) 2}..., x _{(n+1) n}value be 0, above formula can be write as:

$y_{n+1}\&GreaterEqual;\frac{1}{-n}(-n)-C=1-C$

During with i=2, binary variable y ₂value can only equal 1, correspond to the IP kernel j and IP kernel (n+1) concurrent testing that there is not arbitrary numbering and be less than (n+1).

If (n+1) in individual IP kernel, an IP kernel of rear increase and the some concurrent testings in n IP kernel above, then x _{(n+1) 1}, x _{(n+1) 2}..., x _{(n+1) n}in some values be 1, remaining value is 0, then have:

$y_{n+1}\&GreaterEqual;\frac{1}{-n}(-(n-1))-C=\frac{1-n}{n}-C$

At this moment, be an infinitesimal negative of absolute value on the right side of inequality, meet y _n+1, there is IP kernel j and IP kernel (n+1) concurrent testing that certain numbering is less than (n+1) in the situation of=0.

If (n+1) in individual IP kernel, an IP kernel of rear increase and the multiple concurrent testings in n IP kernel above, then have multiple x _{(n+1) j}value be 1, situation and above-mentioned shift onto similar.Limits of application thought, if (n+1) individual IP kernel and the equal concurrent testing of a front n IP kernel, then variable x _{(n+1) 1}, x _{(n+1) 2}..., x _{(n+1) n}value be 1, and to have:

$y_{n+1}\&GreaterEqual;\frac{1}{-n}(-(n-n))-C=-C$

From the above derivation of equation, y _ivariation range on the right side of inequality is each value in interval is negative, meets y _n+1, namely there is certain IP kernel j(j<n+1 in the situation of=0) and IP kernel (n+1) concurrent testing.

Therefore above-mentioned y _imathematic(al) representation can well as the constraint condition of mathematical model.In sum, the D S oC test dispatching algorithm based on stone under power constraints can be expressed as:

Use ILP instrument to solve above-mentioned model and can obtain test dispatching strategy (x _ijwith the value of T).Pass through x _ijvalue determine which IP kernel concurrent testing.T tests whole SoC minimum clock periodicity used under using this test dispatching strategy.

D S oC scheduling experiment based on stone under power constraints is as follows:

Adopt the HP workstation of Intel internal memory 64G to run LP Solve and solve above-mentioned model, temperature required constraint condition is under linux system, under Hotspot-5.0 instrument is operated in raster mode, obtains according to the emulation of circuit specifying information.

The test of D S oC and the research of dispatching method thereof are also in the incipient stage in the world, even international mainstream research institution does not possess the experimental situation of D S oC test yet.ITC ' 02 test set does not provide the detailed location information of IP kernel simultaneously, and IP kernel stochastic distribution in test set is generally formed the D S oC of simulation by foreign scholar to each layer.The present invention adopts the f2126 in ITC ' 02 test set to carry out experimental verification.IP kernel (IP0-IP4) containing 5 different scales in f2126, respectively containing the scan chain that 0-16 bar does not wait, 50-887 the input/output port do not waited.F2126 Random assignment is become the D S oC of 2 layers, wherein larger IP1 is divided into IP1A and IP1B two modules.IP0, IP2 and IP1B occupy the lower floor of D S oC, and IP3, IP4, IP1A occupy the upper strata of D S oC.And above-mentioned IP kernel and module are renumberd, be numbered 1-6 respectively by the order of IP0, IP2, IP1B, IP1A, IP3, IP4, verify the D S oC test dispatching method based on stone under power constraints successively.

Only contain the test dispatching of the D S oC of stone under considering power constraints, experimental result row are write in Table 1.The test port quantity that can provide due to each stone is fixing, in confirmatory experiment, the test bandwidth of each IP kernel is all set to 4.In table, the 2nd row TAM refers to the TAM bandwidth being supplied to whole D S oC, the i.e. upper limit of the test bandwidth sum of the IP kernel of each concurrent testing, in 4th row " scheduling strategy " row, " || " represents several IP kernel concurrent testings connected by it, serial test between several groups of IP kernels having comma to separate, fill in the clock periodicity needed for test during the test duration one arranges.

This test dispatching algorithm has two constraints, be respectively TAM bandwidth sum testing power consumption, table a) shown in data be the test dispatching result of power consumption upper limit when being set to 6.5 (W), wherein the TAM upper limit of D S oC changes successively from 20 to 8, and scheduling strategy and required clock periodicity change all accordingly.Due to the power consumption upper limit be 6.5 relative loose is set, no better than the situation of idle constraint, table is b) scheduling result when power consumption upper limit is 4.8 (W), and its variation tendency is a) similar with table, prove that TAM bandwidth is to the effect of contraction of test dispatching

Table a)

Table b)

Because the test bandwidth of each stone is definite value, therefore when the integral multiple of total TAM bandwidth non-4 of D S oC, its test dispatching result be equivalent to TAM be less than current TAM value maximum 4 multiple time result.Such as: TAM is constrained to 9,10, when 11, coming to the same thing when being 8 with TAM, therefore only lists TAM and is constrained to 4,8,12, result when 16.

In showing two, under identical TAM bandwidth, different power consumption constraint, test duration of obtaining is drawn as histogram, is aggregated in Fig. 4, can finds out, compared to the situation that approximate idle retrains, during relatively tight power constraints 4.8, the test duration is relatively long.This be IP kernel owing to being numbered 2 with the IP kernel being numbered 3 and the IP kernel being numbered 4 while test time, power consumption has exceeded the cause of the upper limit set.And when TAM constraint equals 8, the situation that the IP kernel being numbered 2 is tested with the IP kernel being numbered 4 with the IP kernel being numbered 3 simultaneously is all there is not in the Test Strategy of two kinds of situations, therefore its test duration is identical, the above comparative illustration validity of power constraints in test dispatching algorithm.

Claims (5)

1. under power constraints based on the D S oC test dispatching method of stone, it is characterized in that, the detailed process of described method is:

Step one: the D S oC based on stone comprises coarseness IP kernel and fine granularity IP kernel, first fine granularity IP kernel is considered as the multiple parts on each layer, part on every layer is equivalent to a coarseness IP kernel, by all coarseness IP kernels and fine granularity IP kernel, the part on each layer is unified is numbered, and sets up the mathematical model of D S oC test dispatching

$T=\underset{i=1}{\overset{\left|M\right|}{\mathrm{\&Sigma;}}}{y}_i\&CenterDot;\left(\max \underset{j=i}{\left|M\right|}\right\{x_{\mathrm{ij}}\&CenterDot;t_j\left\}\right),$

Wherein | M| represents the IP kernel sum in a SoC, x _ijrepresent a binary variable, when being numbered the IP kernel of i and being numbered the IP kernel concurrent testing of j, then x _ijvalue is 1, otherwise x _ijvalue is that 0, i and j is 1 and arrives | any positive integer between M|, t _jfor being numbered the test duration of the IP kernel of j, represent the maximal value of each IP kernel test duration of concurrent testing,

Y _irepresent a binary variable, there is the IP kernel being numbered i, if there is arbitrary number is the IP kernel of j and the IP kernel concurrent testing being numbered i, wherein j<i, with IP kernel i concurrent testing, then y _ivalue be 0; Otherwise y _ivalue be 1;

Step 2: introduce variable

$c_i=\max \underset{j=i}{\left|M\right|}\{x_{\mathrm{ij}}\&CenterDot;t_j\}$ And u _i=y _iic _i,

By the mathematical model linearization in step one, obtain wherein c _irepresent the maximal value being numbered the IP kernel test duration of i of concurrent testing, u _irepresent and introduce variable y _iafter the maximal value being numbered the IP kernel test duration of i,

Try to achieve the minimum value of the test duration T of whole SoC according to constraint condition, namely obtain the testing sequence of IP kernel, then dispatch IP kernel to be measured successively according to this testing sequence and realize SoC test dispatching.

2. under power constraints according to claim 1 based on the D S oC test dispatching method of stone, it is characterized in that, the constraint condition in described step 2 comprises:

$c_i\&GreaterEqual;x_{\mathrm{ij}}\&CenterDot;t_j,\&ForAll;i,j=\mathrm{1,2},...,\left|M\right|,$

$u_i-c_i\&le;0,\&ForAll;i,$

$u_i\&GreaterEqual;0,\&ForAll;i,$

$u_i-t_{\max }\&CenterDot;y_i\&le;0,\&ForAll;i,$

$c_i-u_i+t_{\max }\&CenterDot;y_i\&le;t_{\max },\&ForAll;i,$

$1-x_{\mathrm{ij}}\&GreaterEqual;x_{\mathrm{ik}}-x_{\mathrm{jk}}\&GreaterEqual;x_{\mathrm{ij}}-1,\&ForAll;i,j,k,$

$y_i\&GreaterEqual;\frac{1}{1-i}\underset{j=1}{\overset{t-1}{\mathrm{\&Sigma;}}}(x_{\mathrm{ij}}-1)-C,\&ForAll;i>1,$

Wherein t _maxrepresent the test duration maximal value of all IP kernels, x _ikrepresent a binary variable, when being numbered the IP kernel of i and being numbered the IP kernel concurrent testing of k, then x _ikvalue is 1, otherwise x _ikvalue is that 0, i and k is 1 and arrives | any positive integer between M|, x _jkrepresent a binary variable, when being numbered the IP kernel of j and being numbered the IP kernel concurrent testing of k, then x _jkvalue is 1, otherwise x _jkvalue is that 0, j and k is 1 and arrives | any positive integer between M|, and C is the constant little close to 1 but than 1, and

3. under power constraints according to claim 1 and 2 based on the D S oC test dispatching method of stone, it is characterized in that, the constraint condition in described step 2 also comprises

$\underset{j=1}{\overset{\left|M\right|}{\mathrm{\&Sigma;}}}{x}_{\mathrm{ij}}\&CenterDot;w_i\&le;W_{\max },\&ForAll;i,$

Namely the test port quantity sum of each concurrent testing IP kernel can not exceed operational TAM total bandwidth W _max, wherein w _irepresent the TAM bandwidth being numbered the test port of the IP kernel of i.

4. under power constraints according to claim 3 based on the D S oC test dispatching method of stone, it is characterized in that, the constraint condition in described step 2 also comprises

$\underset{j=1}{\overset{\left|M\right|}{\mathrm{\&Sigma;}}}{x}_{\mathrm{ij}}\&CenterDot;p_i\&le;P_{\max },\&ForAll;i,$

Namely each IP kernel testing power consumption sum of concurrent testing can not exceed the power consumption upper limit P that system allows _max, wherein p _irepresent the testing power consumption being numbered the IP kernel of i.

5. under power constraints according to claim 1 based on the D S oC test dispatching method of stone, it is characterized in that, the part that each fine granularity IP kernel is positioned in different aspects carries out concurrent testing, and namely fine granularity IP kernel splits into N number of part by level arbitrarily, is designated as IP i respectively ₁, IP i ₂..., IP i _n, then have

$x_{\mathrm{IJ}}=1,\&ForAll;I,J\&Element;\{i_1,i_2,...i_N\},$

Wherein x _iJrepresent a binary variable, when being numbered the IP kernel of I and being numbered the IP kernel concurrent testing of J, then x _iJvalue is 1, otherwise x _iJvalue is 0.