CN103379734A - Wiring board with built-in electronic component and method for manufacturing the same - Google Patents
Wiring board with built-in electronic component and method for manufacturing the same Download PDFInfo
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- CN103379734A CN103379734A CN2013101587418A CN201310158741A CN103379734A CN 103379734 A CN103379734 A CN 103379734A CN 2013101587418 A CN2013101587418 A CN 2013101587418A CN 201310158741 A CN201310158741 A CN 201310158741A CN 103379734 A CN103379734 A CN 103379734A
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Abstract
The present invention provides a wiring board and a manufacturing method thereof. The wiring board (10) including a substrate (100) having an opening (R10) penetrating from a first surface (F1) to a second surface (F2), an electronic component (200) in the opening (R10) and has first and second electrodes (210,220), a first insulation layer (101) over the first surface (F1), a second insulation layer (102) over the second surface (F2), a first via conductor (311b) in the first layer (101) and has bottom connected to the first electrode (210), a second via conductor (312b) in the first layer (101) and has bottom connected to the second electrode (220), a third via conductor (321b) in the second layer (102) and has bottom connected to the first electrode (210), and a fourth via conductor (322b) in the second layer (102) and has bottom connected to the second electrode (220). The first conductor (311b) is longer than the third conductor (321b) and has the bottom having greater width than the bottom of the third conductor (321b), and the second conductor (312b) is longer than the fourth conductor (322b) and has the bottom having greater width than the bottom of the fourth conductor (322b).
Description
Technical field
The present invention relates to have wiring plate and the manufacture method thereof of built-in electronic assembly.
Background technology
In TOHKEMY 2001-345560 communique, a kind of wiring plate with built-in capacitor has been described.The full content of this application is contained in this by reference.
Summary of the invention
According to an aspect of the present invention, wiring plate has: substrate, and it has peristome, and wherein said peristome connects to the second surface that is positioned at the described substrate of opposite side with respect to the first surface of described substrate from the first surface of described substrate; Electronic building brick, it is configured in the described peristome, and have the first lateral electrode and the second lateral electrode, wherein said the first lateral electrode and described the second lateral electrode extend to the second surface that is positioned at the described electronic building brick of opposite side with respect to the first surface of described electronic building brick from the first surface of described electronic building brick; A plurality of insulating barriers, it comprise the first insulating barrier on the first surface of the first surface that is formed on described substrate and described electronic building brick and be formed on the second surface of described substrate and the second surface of described electronic building brick on the second insulating barrier; And a plurality of via conductors, it comprises: the first via conductor, it is formed in described the first insulating barrier and has the basal surface that is connected to described the first lateral electrode, the alternate path conductor, it is formed in described the first insulating barrier and has the basal surface that is connected to described the second lateral electrode, the three-way conductor, it is formed in described the second insulating barrier and has the basal surface that is connected to described the first lateral electrode, and four-way road conductor, it is formed in described the second insulating barrier and has the basal surface that is connected to described the second lateral electrode.The length of described the first via conductor arranges to such an extent that be longer than the length of described three-way conductor, the width of the basal surface of described the first via conductor forms the width greater than the basal surface of described three-way conductor, the length of described alternate path conductor arranges to such an extent that be longer than the length of described four-way road conductor, and the width of the basal surface of described alternate path conductor is greater than the width of the basal surface of described four-way road conductor.
According to a further aspect in the invention, a kind of manufacture method of wiring plate, may further comprise the steps: form the peristome that connects substrate, wherein said peristome connects to the second surface that is positioned at the described substrate of opposite side with respect to this first surface from the first surface of described substrate; The electronic building brick that configuration has the first lateral electrode and the second lateral electrode in the described peristome of described substrate, wherein said the first lateral electrode and described the second lateral electrode extend to the second surface that is positioned at the described electronic building brick of opposite side with respect to the first surface of described electronic building brick from the first surface of described electronic building brick; Form a plurality of insulating barriers at described substrate, wherein said a plurality of insulating barriers comprise the first insulating barrier on the first surface of the first surface that is positioned at described substrate and described electronic building brick and be positioned at the second surface of described substrate and the second surface of described electronic building brick on the second insulating barrier; And form a plurality of via conductors, wherein said a plurality of via conductor comprises: be arranged in the first via conductor and the alternate path conductor of described the first insulating barrier, wherein said the first via conductor has the basal surface and the described alternate path conductor that are connected to described the first lateral electrode and has the basal surface that is connected to described the second lateral electrode; And the three-way conductor and the four-way road conductor that are arranged in described the second insulating barrier, wherein said three-way conductor has the basal surface and the described four-way road conductor that are connected to described the first lateral electrode and has the basal surface that is connected to described the second lateral electrode.The length of described the first via conductor arranges to such an extent that be longer than the length of described three-way conductor, the width of the basal surface of described the first via conductor forms the width greater than the basal surface of described three-way conductor, the length of described alternate path conductor arranges to such an extent that be longer than the length of described four-way road conductor, and the width of the basal surface of described alternate path conductor is greater than the width of the basal surface of described four-way road conductor.
Description of drawings
Understand better the present invention along with becoming by the following detailed description when engaging accompanying drawing and consider, with a plurality of advantages that obtain easily more complete understanding of the present invention and follow, wherein:
Fig. 1 is the sectional view of wiring plate according to the embodiment of the present invention;
Fig. 2 is the partial enlarged drawing of Fig. 1;
Fig. 3 shows the figure of the example of the first type surface that electronic building brick is installed in wiring plate according to the embodiment of the present invention (install on the surface);
Fig. 4 A shows the figure of the first cross sectional shape of the chip capacitor in the wiring plate of waiting to be built into according to the embodiment of the present invention;
Fig. 4 B shows the figure of the second cross sectional shape of the chip capacitor in the wiring plate of waiting to be built into according to the embodiment of the present invention;
Fig. 5 A is the plane graph of the chip capacitor in the wiring plate of waiting to be built into according to the embodiment of the present invention;
Fig. 5 B shows the figure of formed electrode on the side surface of the chip capacitor in the wiring plate waiting to be built into according to the embodiment of the present invention;
Fig. 6 show in according to the embodiment of the present invention the wiring plate in electronic building brick is accommodated in cavity the time the plane graph of state;
Fig. 7 shows the first via conductor that is connected to the first lateral electrode in the wiring plate shown in Fig. 1 and the amplification sectional view of three-way conductor;
Fig. 8 shows the alternate path conductor that is connected to the second lateral electrode in the wiring plate shown in Fig. 1 and the amplification sectional view of four-way road conductor;
Fig. 9 shows shown in Fig. 1 being formed in the first insulating barrier and being connected to the figure of the first via conductor of the first lateral electrode in the wiring plate;
Figure 10 shows shown in Fig. 1 being formed in the second insulating barrier and being connected to the figure of the three-way conductor of the first lateral electrode in the wiring plate;
Figure 11 shows shown in Fig. 1 being formed in the first insulating barrier and being connected to the figure of the alternate path conductor of the second lateral electrode in the wiring plate;
Figure 12 shows shown in Fig. 1 being formed in the second insulating barrier and being connected to the figure of the four-way road conductor of the second lateral electrode in the wiring plate;
Figure 13 A shows shown in Fig. 1 being formed in the first insulating barrier and not being connected to the figure of via conductor of the electrode of electronic building brick in the wiring plate;
Figure 13 B shows shown in Fig. 1 being formed in the second insulating barrier and not being connected to the figure of via conductor of the electrode of electronic building brick in the wiring plate;
Figure 14 shows the flow chart of Wiring board manufacturing method according to the embodiment of the present invention;
Figure 15 A shows the figure that is used for forming at substrate the first step of conductive layer in the manufacture method shown in Figure 14;
Figure 15 B shows the figure that is used for forming at substrate the second step of conductive layer in the manufacture method shown in Figure 14;
Figure 15 C shows the figure that is used for forming at substrate the third step of conductive layer in the manufacture method shown in Figure 14;
Figure 15 D shows the figure that is used for forming at substrate the 4th step of conductive layer in the manufacture method shown in Figure 14;
Figure 16 shows the figure that is used for forming the step of cavity in substrate in the manufacture method shown in Figure 14;
Figure 17 A shows the figure that is used for the first example of the Ear Mucosa Treated by He Ne Laser Irradiation of the step of formation cavity in substrate in the manufacture method shown in Figure 14;
Figure 17 B shows the figure that is used for the second example of the Ear Mucosa Treated by He Ne Laser Irradiation of the step of formation cavity in substrate in the manufacture method shown in Figure 14;
Figure 18 shows the plane graph that is formed on the peristome (cavity) in the substrate by step shown in Figure 14;
Figure 19 shows the figure that is used for supporting body is attached to the step of the substrate that is formed with cavity in the manufacture method shown in Figure 14;
Figure 20 shows shown in Figure 14 the figure in the step of cavity content nano-electron assembly of being used in the manufacture method;
Figure 21 shows the figure that the electronic building brick in the manufacture method shown in Figure 14 is contained in the state in the cavity;
Figure 22 shows the figure for the first step of filling insulator in the gap between the electronic building brick in substrate and cavity in the manufacture method shown in Figure 14;
Figure 23 shows the figure of the second step after the step in Figure 22;
Figure 24 shows the figure of the third step after the step in Figure 23;
Figure 25 shows the figure that is used for removing from substrate the step of supporting body in the manufacture method shown in Figure 14;
Figure 26 shows the figure of the first step of accumulation section under being used to form in manufacture method shown in Figure 14;
Figure 27 shows the figure of the second step after the step in Figure 26;
Figure 28 shows the figure of the third step after the step in Figure 27;
Figure 29 shows the figure of the 4th step after the step in Figure 28;
Figure 30 shows the figure of the step that is used to form accumulation section in the manufacture method shown in Figure 14;
Figure 31 shows the figure of the example that the via conductor on two surfaces that are connected to electronic building brick in another embodiment of the present invention do not face with each other;
Figure 32 shows the figure of the example that several via conductors on two surfaces that are connected to electronic building brick in the another embodiment of the invention differ from one another;
Figure 33 shows the figure that does not form the example of conductive layer on arbitrary first type surface of core substrate in the another embodiment of the invention;
Figure 34 has showed omission in the another embodiment of the invention figure of example of upper accumulation section; And
Figure 35 shows the figure of the wiring plate with a plurality of built-in electronic assemblies in the another embodiment of the invention.
Embodiment
Now with reference to the description of drawings execution mode, wherein in whole a plurality of figure, identical Reference numeral is specified element corresponding or that be equal to.
In the drawings, arrow (Z1, Z2) represents and stacked direction (or thickness direction of wiring plate) in wiring plate corresponding to the direction of the normal of the first type surface (upper surface and lower surface) of wiring plate separately.On the other hand, arrow (X1, X2) and (Y1, Y2) represent the direction vertical with the stacked direction direction of every layer side (perhaps towards) separately.The first type surface of wiring plate is on X-Y plane.The side surface of wiring plate is on X-Z face or Y-Z face.On stacked direction, a side of close core is known as lower floor's (perhaps internal layer side), and is known as upper strata (or outer layer side) away from a side of core.
Conductive layer is formed with one or more conductive patterns.Conductive layer can comprise the conductive pattern that forms circuit such as wiring (comprising earth terminal), pad, terminal pad.Conductive layer can comprise the plane conductive pattern that does not form circuit.
Peristome comprises recess and the otch except hole and groove.The hole is not limited to through hole, and non-through hole is also referred to as the hole.The hole comprises via hole and through hole.Hereinafter, the conductor that is formed in the via hole (wall or bottom surface) is called via conductor, and the conductor that is formed in the through hole (wall) is called via conductors.
The stacking via conductor that means is formed on the terminal pad of another via conductor that is formed at its lower floor.That is, if the basal surface of via conductor not from the terminal pad of another via conductor of being formed at its lower floor, has then represented stacking via conductor.
Plating (plating) comprises such as the wet method plating of electrolysis plating etc. and such as the dry method of PVD (physical vapour deposition (PVD)) and CVD (chemical vapour deposition (CVD)) etc. plates.
The lateral electrode of electronic building brick is formed in the electrode at least a portion of side surface of electronic building brick.
Unless otherwise, " width " of hole or post (projection) if the circle words then mean diameter, perhaps if except the circle shape then mean
Below, explain with reference to the accompanying drawings embodiments of the present invention.
Shown in Fig. 1 and Fig. 2 (partial enlarged drawing of Fig. 1), the wiring plate 10 of present embodiment (wiring plate with built-in electronic assembly) has substrate 100 (insulated substrate), via conductors (300b), insulating barrier (101,102,103,104) (each interlayer insulating film), conductive layer (301,302,110,120,130,140), electronic building brick 200, via conductor (311b, 312b, 313b, 321b, 322b, 323b, 333b, 341b, 342b, 343b) and solder mask (11,12).The wiring plate 10 of present embodiment is the rigidity wiring plate 10 of for example rectangular shape.Yet this is not unique selection, and wiring plate 10 also can be any other shape except rectangle, and can be flexible distributing board.
In the present embodiment, substrate 100 is core substrates of wiring plate 10.Peristome (R100) (Fig. 2) is formed in the substrate 100.Electronic building brick 200 is built in the core substrate of wiring plate 10 in the mode that is positioned at peristome (R100).In the wiring plate 10 of present embodiment, substrate 100, via conductors (300b), conductive layer (301,302) and electronic building brick 200 consist of core.Below, one of them is known as first surface (F1) upper surface of substrate 100 and lower surface (two first type surfaces), and another is known as second surface (F2).In addition, in the upper surface and lower surface (two first type surfaces) of electronic building brick 200, be called the 3rd surface (F3) with first surface (F1) towards the surface of equidirectional, and another is called the 4th surface (F4).
The conductive layer, interlayer insulating film and the via conductor that are layered on the core substrate are corresponding with accumulation section.Below, the accumulation section in the upper/lower positions is called lower accumulation section, and will be positioned at the position and be called upper accumulation section than more top accumulation section of lower accumulation section.In the present embodiment, lower accumulation section is formed by insulating barrier (101,102), conductive layer (110,120) and via conductor (311b, 312b, 313b, 321b, 322b, 323b).In addition, upper accumulation section is formed by insulating barrier (103,104), conductive layer (130,140) and via conductor (333b, 341b, 342b, 343b).
In substrate 100 (core substrate), be formed with through hole (300a), and form via conductors (300b) by in through hole (300a), filling conductor (such as copper facing).The shape of via conductors (300b) forms for example hourglass shape.Namely, via conductors (300b) has narrowing portion (300c), the width of via conductors (300b) reduces along with close narrowing portion (300c) gradually from first surface (F1), and dwindles gradually along with close narrowing portion (300c) from second surface (F2).Yet this is not unique selection, and via conductors (300b) can have any other shape; For example, can have roughly cylindrical shape.
Insulating barrier 101 is formed on the first surface (F1) and conductive layer 301 of substrate 100.Insulating barrier 102 is formed on the second surface (F2) and conductive layer 302 of substrate 100.Conductive layer 110 is formed on the insulating barrier 101, and conductive layer 120 is formed on the insulating barrier 102.
In the present embodiment, the thickness of cavity (R10) (summation of the thickness of the thickness of the thickness of substrate 100, conductive layer 301 and conductive layer 302) is greater than the thickness (summation of the thickness of main body 201, top (210a) or thickness (220a) and bottom (210c) or thickness (220c)) of the electronic building brick 200 that comprises outer electrode.Therefore, whole electronic building brick 200 is accommodated in the cavity (R10).In addition, arrange greater than the thickness of electronic building brick 200 by the summation with the thickness of the thickness of the thickness of substrate 100, conductive layer 301 and conductive layer 302, the wiring plate 10 of present embodiment (wiring plate with built-in electronic assembly) is warpage seldom.
In the present embodiment, as shown in Figure 2, the 3rd surface (F3) of the upper surface of conductive layer 301 (F13) and electronic building brick 200 (the first electrode surface that particularly illustrates later (F411, F421)) is in differing heights (Z coordinate) each other.Therefore, between insulating barrier 101 and electronic building brick 200, form the gap.Insulator (101a) is filled in this gap.By contrast, the 4th surface (F4) of the upper surface of conductive layer 302 (F14) and electronic building brick 200 (the second electrode surface that illustrates especially later (F412, F422)) has roughly the same each other height (Z coordinate), thereby has formed uniform surface.Therefore, when making the wiring plate 10 of present embodiment, electronic building brick 200 is easy to by utilizing supporting bracket (such as supporting body 1005) to be installed on (being built in) wiring plate (seeing below Figure 19 to Figure 26 of explanation).As a result, even be built in the wiring plate 10 of present embodiment when interior at thin electronic building brick, manufacture process also seldom complicates.So, have the wiring plate of built-in electronic assembly by the method manufacturing that makes it possible to keep high rate/low cost production, high yield etc.
Insulating barrier 101 and insulator (101a) (each the first insulating barrier) are formed on the 3rd surface (F3) of electronic building brick 200, and insulating barrier 102 (the second insulating barrier) is formed on the 4th surface (F4) of electronic building brick 200.Insulating barrier 101 covers opening of cavitys (R10) (on first surface (F1) side), and insulating barrier 102 covers (on second surface (F2) side) another opening of cavitys (R10).
Insulating barrier 103 is formed on insulating barrier 101 and the conductive layer 110, and insulating barrier 104 is formed on insulating barrier 102 and the conductive layer 120.Conductive layer 130 is formed on the insulating barrier 103, and conductive layer 140 is formed on the insulating barrier 104.In the present embodiment, conductive layer (130,140) is outermost layer.Yet this is not unique selection, and further stacked more multi-layered insulating barrier and conductive layer.
In insulating barrier 101, form porose (311a, 312a, 313a) (via hole), and formation porose (321a, 322a, 323a) (via hole) in insulating barrier 102.In insulating barrier 103, form porose (333a) (via hole), and formation porose (341a, 342a, 343a) (via hole) in insulating barrier 104.Then, by in each hole, (for example filling conductor, copper facing), the conductor in each hole becomes respectively via conductor (311b, 312b, 313b, 321b, 322b, 323b, 333b, 341b, 342b, 343b) (each fills conductor).Via conductor (311b, 312b, 321b, 322b, 341b, 342b, 313b, 323b, 333b, 343b) has respectively the terminal pad (311c) of band recess (R1), the terminal pad (312c) of band recess (R2), the terminal pad (321c) of band recess (R3), the terminal pad (322c) of band recess (R4), the terminal pad (341c) of band recess (R5), the terminal pad (342c) of band recess (R6), the terminal pad (313c) of band recess (R71), the terminal pad (323c) of band recess (R72), the terminal pad (343c) of the terminal pad (333c) of band recess (R73) and band recess (R74).
Via conductor (311b) is connected to the electrode 210 (top that particularly illustrates later (210a)) of electronic building brick 200, and via conductor (312b) is connected to the electrode 220 (top that particularly illustrates later (220a)) of electronic building brick 200.In addition, via conductor (321b) is connected to the electrode 210 (bottom that particularly illustrates later (210c)) of electronic building brick 200, and via conductor (322b) is connected to the electrode 220 (bottom that particularly illustrates later (220c)) of electronic building brick 200.Via conductor (311b, 312b) is formed in the insulating barrier 101 separately, and via conductor (321b, 322b) is formed in the insulating barrier 102 separately.In the present embodiment, two of electronic building brick 200 surfaces (being respectively the 3rd surface (F3) and the 4th surface (F4)) are connected to via conductor as mentioned above.Below, such structure is called the bilateral access structure.
About the via conductor that is connected to electrode 210 in the wiring plate 10 of present embodiment be connected to the via conductor of electrode 220, the quantity that is formed on the via conductor in the insulating barrier 101 is identical with the quantity of via conductor in being formed on insulating barrier 102.Especially, in the via conductor that is connected to electrode 210, a via conductor is formed on (via conductor (311b)) in the insulating barrier 101, and a via conductor is formed on (via conductor (321b)) in the insulating barrier 102.In addition, in the via conductor that is connected to electrode 220, a via conductor is formed on (via conductor (312b)) in the insulating barrier 101, and a via conductor is formed on (via conductor (322b)) in the insulating barrier 102.In addition, (with identical XY coordinate) is formed in the position that faces with each other via conductor (311b) by electronic building brick 200 is clipped in the middle with via conductor (321b), and via conductor (312b) and via conductor (322b) (with identical XY coordinate) is formed in the position that faces with each other and (sees below Fig. 6 of explanation) by electronic building brick 200 is clipped in the middle.
Because above-mentioned bilateral access structure, so in the wiring plate 10 of present embodiment, conductive layer 110 and conductive layer 120 are electrically connected to each other by electrode 210 and the via conductor (311b, 321b) of electronic building brick 200, and perhaps electrode 220 and the via conductor (312b, 322b) by electronic building brick 200 is electrically connected to each other.So the conductive layer on second surface (F2) side of the conductive layer on the first surface of substrate 100 (F1) side and substrate 100 does not form in substrate 100 in the situation of through hole and is electrically connected to each other.As a result, be easy to guarantee that the wiring on the substrate 100 is regional.In addition, be formed in the internal layer of such structure owing to be electrically connected, so be conducive to miniaturization.In addition, when comparing with the wiring plate with built-in electronic assembly with one-sided access structure, the heat radiation that in such wiring plate with built-in electronic assembly with bilateral access structure, has improved the built-in electronic assembly.
Other via conductors (341b, 342b) are stacking with via conductor (321b, 322b) respectively.Particularly, via conductor (341b, 342b) is located immediately at respectively via conductor (321b, 322b) upper (direction Z).The via conductor (341b) of via conductor (321b) and top thereof contacts with each other and is electrically connected.In addition, the via conductor (342b) of via conductor (322b) and top thereof contacts with each other and is electrically connected.In the present embodiment, the axis on the direction Z of stacking as mentioned above via conductor (321b, 341b) roughly overlaps each other, and the axis on the direction Z of stacking as mentioned above via conductor (322b, 342b) roughly overlaps each other.Here, the straight line of via conductor on the direction Z of the center of gravity (if the words of circle are the center of circle) in the axis on the direction Z and each X-Y cross section of passing via conductor is corresponding.
On the other hand, there are not via conductor and via conductor (311b, 312b) stacking.
In addition, each in the via conductor (313b, 323b, 333b, 343b) is located immediately at via conductors (300b) upper (direction Z), and adjacent conductor contacts with each other.So via conductors and via conductor or adjacent lanes conductor are electrically connected to each other.In the present embodiment, each fills conductor naturally via conductor (313b, 323b, 333b, 343b) and via conductors (300b), and they are stacking on direction Z.Such stacked structure is conducive to miniaturization.In the present embodiment, the axis on the direction Z of stacking via conductor (313b, 323b, 333b, 343b) and via conductors (300b) roughly overlaps each other as mentioned above.
On conductive layer (130,140) (each outermost conductive layer), form respectively solder mask (11,12).Yet, in solder mask (11,12), be formed with peristome (11a, 12a).Therefore, the predetermined portions of conductive layer 130 (part corresponding with peristome (11a)) exposes and is not covered by solder mask 11, and becomes pad (P11).In addition, the predetermined portions of conductive layer 140 (part corresponding with peristome (12a)) becomes pad (P12).Pad (P11) becomes the external connection terminals that is electrically connected with another wiring plate for for example, and pad (P12) becomes for the external connection terminals that electronic building brick for example is installed.Yet these are not unique selection, and pad (P11, P12) can be used for any other purpose.
The wiring plate 10 of present embodiment has the directly pad of (direction Z) (P11, P12) (external connection terminals) on electronic building brick 200.In addition, wiring plate 10 has the directly pad of (direction Z) (P11, P12) (external connection terminals) on substrate 100.Pad (P11, P12) has the anticorrosive coat by for example nickel/golden film is made in its surface.Can form anticorrosive coat by electrolysis plating or sputter etc.Also can process to form the anticorrosive coat of being made by organic protective film by carrying out OSP.Always do not need anticorrosive coat, and unless necessary otherwise can omit.
In the present embodiment, be layered in outermost conductive layer (pad P11) on first surface (F1) side of substrate 100 and consisted of and be used for installing the terminal of another wiring plate, and the outermost conductive layer (pad P12) that is layered on second surface (F2) side of substrate 100 has consisted of the terminal that is used for installing IC (integrated circuit) chip.
Particularly, pad (P11) for example forms BGA (ball grid array).The wiring plate 10 of present embodiment for example is installed on the motherboard via pad (P11).In addition, IC chip 2001 (such as carries chips) is the FC (flip-chip) that for example is installed in as shown in Figure 3 on the pad (P12).
The structure of the electric appliance component 200 (chip capacitor) in the wiring plate 10 of present embodiment to be built into is described with reference to Fig. 4 A to Fig. 5 B below.Fig. 4 A shows the figure of first cross sectional shape (X-Z cross section) of electronic building brick 200.Fig. 4 B shows the figure of second cross sectional shape (Y-Z cross section) of electronic building brick 200.Fig. 5 A is the plane graph of electronic building brick 200.Fig. 5 B shows the figure of the electrode on the side surface of the main body 201 that is formed on electronic building brick 200.
Below, the part that is formed on the first side surface (F33), the 3rd side surface (F35) and the 4th side surface (F36) of electrode 210 is called respectively the first sidepiece (210b), the 3rd sidepiece (210d) and the 4th sidepiece (210e) (seeing Fig. 5 B).The part that is formed on the second side surface (F34), the 3rd side surface (F35) and the 4th side surface (F36) of electrode 220 is called respectively the second sidepiece (220b), the 3rd sidepiece (220d) and the 4th sidepiece (220e) (seeing Fig. 5 B).In addition, the part that is formed on the first first type surface (F31) of electrode (210,220) is called top (210a, 220a), and the part that is formed on the second first type surface (F32) is called bottom (210c, 220c) (seeing Fig. 4 A).
Below, the upper surface on the top of electrode 210 (210a) is called the first electrode surface (F411), the upper surface on the top of electrode 220 (220a) is called the first electrode surface (F421), the upper surface of the bottom of electrode 210 (210c) is called the second electrode surface (F412), and the upper surface of the bottom of electrode 220 (220c) is called the second electrode surface (F422).Shown in Fig. 4 A, the 3rd surface (F3) of electronic building brick 200 is formed with the first electrode surface (F411), the first first type surface (F31) and the first electrode surface (F421).The 4th surface (F4) of electronic building brick 200 is formed with the second electrode surface (F412), the second first type surface (F32) and the second electrode surface (F422).
In the present embodiment, in electrode 210, top (210a), the first sidepiece (210b), the 3rd sidepiece (210d), the 4th sidepiece (210e) and bottom (210c) are integrally formed each other; And in electrode 220, top (220a), the second sidepiece (220b), the 3rd sidepiece (220d), the 4th sidepiece (220e) and bottom (220c) are integrally formed each other.(the first side surface (F33), the second side surface (F34), the 3rd side surface (F35), the 4th side surface (F36)) covers the first first type surface (F31) to arbitrary end of main body 201 always from the second first type surface (F32) towards side surface by electrode 210 or 220.Conductive layer (211 to 214) (electrode in each) is connected to the first sidepiece (210b) (part of electrode 210), and conductive layer (221 to 224) (electrode in each) is connected to the second sidepiece (220b) (part of electrode 220).
Electrode (210,220) is positioned at the both ends of electronic building brick 200.Shown in Fig. 4 A, the central portion between electrode 210 and electrode 220 of main body 201 is covered by electrode (210,220), and first first type surface (F31) of main body 201 and the second first type surface (F32) (particularly dielectric layer (231,239)) expose.
Fig. 6 is the interior figure of cavity (R10) that electronic building brick 200 is accommodated in core.
In the wiring plate 10 of present embodiment, as shown in Figure 6, the opening shape of (first surface (F1) side and second surface (F2) side) rectangle of respectively doing for oneself on the two ends of cavity (R10).Electrode 210 for example is anodal (+), and electrode 220 for example is negative pole (-).The electrode 210 of electronic building brick 200 for example is electrically connected to power supply via tube core (die).In addition, the electrode 220 of electronic building brick 200 such as via the end such as via conductor (322b) with being electrically connected to.
Shown in Fig. 4 A to Fig. 5 B, the electronic building brick 200 of present embodiment at one end has the symmetrical structure on the direction X on (for example, electrode 210 sides) and the other end (for example, electrode 220 sides).Therefore, even the polarity of electrode 210 and electrode 220 is opposite, electronic building brick 200 is also worked.Therefore, when electronic building brick 200 is arranged in the cavity (R10) of wiring plate 10 of present embodiment, need not to check the direction of electronic building brick 200.
Below, show preferred exemplary for the material of the wiring plate 10 of present embodiment.
In the present embodiment, substrate 100 is made by the resin that comprises core material.Particularly, for example by making substrate 100 with epoxy resin impregnated glass cloth (core material) (below be called glass epoxy resin).The thermal coefficient of expansion of core material is lower than the thermal coefficient of expansion of main material (being epoxy resin in the present embodiment).For core material, such as preferably considering glass fibre (such as glass cloth or glass nonwoven fabrics), aramid fibre (such as aramid nonwoven fabric) or such as the inorganic material of silica filler etc.Yet any material can be selected for substrate 100 basically.For example, substrate 100 can be made by the resin that does not comprise core material.In addition, can use mylar, bismaleimide-triazine resin (BT resin), imide resin (polyimides), phenolic resins, pi-allyl polyphenylene oxide resin (A-PPE resin) etc. to replace epoxy resin.Substrate 100 can form with multiple layers of different materials.
In the present embodiment, insulating barrier (101,102,103,104) is separately by forming with the resin-dipping core material.Particularly, insulating barrier (101,102,103,104) is for example made by glass epoxy resin separately.
In the present embodiment, each resin that freely comprises core material of insulating barrier (101,102) is made.So, in insulating barrier (101,102), unlikely form depression, thereby suppressed to be formed on the line breakage of the conductive pattern on the insulating barrier (101,102).In addition, suppressed electronic building brick 200 and be offset at direction Z, and the position skew of electronic building brick 200 has seldom occured at direction Z.Yet, may during pressure process, increase the impact of core.
Yet more than arranging is not unique selection.For example, insulating barrier (101,102,103,104) can be made by the resin that does not comprise core material.Basically, be used for the not specifically restriction of material of insulating barrier (101,102,103,104).For example, also can use mylar, bismaleimide-triazine resin (BT resin), imide resin (polyimides), phenolic resins, pi-allyl polyphenylene oxide resin (A-PPE resin) etc. to replace epoxy resin.Each insulating barrier can form with multiple layers of different materials.
In the present embodiment, via conductor (311b, 312b, 313b, 321b, 322b, 323b, 333b, 341b, 342b, 343b) is for example made by copper facing separately.The tapered pole (frustum of a cone) that the taper that via conductor shape separately for example forms diameter to be increased towards its upper strata separately from core attenuates.Yet this is not unique selection, and the shape of via conductor can freely be determined.
Conductive layer (110,120,130,140) is for example made by Copper Foil (lower floor) and copper facing (upper strata) separately.Conductive layer (110,120,130,140) comprises separately and has formed circuit, terminal pad, plane conductive pattern with the wiring such as the intensity that improves wiring plate 10 etc.
The material that is used for each conductive layer and each via conductor can freely be selected, as long as conduction; Can be metal or nonmetallic.Each conductive layer and each via conductor can form with multiple layers of different materials.
As depicted in figs. 1 and 2, the wiring plate 10 of present embodiment has with lower member: substrate 100, it has first surface (F1) and the second surface (F2) relative with it, and has from first surface (F1) and connect peristome (R100) to second surface (F2); Electronic building brick 200, it is positioned at peristome (R100), and have with first surface (F1) towards the 3rd surface (F3) of equidirectional, its relative the 4th surface (F4), electrode 210 (the first lateral electrode) and the electrode 220 (second lateral electrode) relative with it; Insulating barrier 101 and insulator (101a) (each the first insulating barrier), it is formed on the 3rd surface (F3) of electronic building brick 200; Insulating barrier 102 (the second insulating barrier), it is formed on the 4th surface (F4) of electronic building brick 200; Via conductor (311b) (the first via conductor), it is formed in insulating barrier 101 and the insulator (101a) (each the first insulating barrier) in the mode that basal surface (F111) is connected to electrode 210 (the first lateral electrode); Via conductor (312b) (alternate path conductor), it is formed in insulating barrier 101 and the insulator (101a) (each the first insulating barrier) in the mode that basal surface (F321) is connected to 220 (the second lateral electrodes); Via conductor (321b) (three-way conductor), it is formed in the insulating barrier 102 (the second insulating barrier) in the mode that basal surface (F331) is connected to electrode 210 (the first lateral electrode); Via conductor (322b) (four-way road conductor), it is formed in the insulating barrier 102 (the second insulating barrier) in the mode that basal surface (F341) is connected to electrode 220 (the second lateral electrode); Via conductor (313b) (five-way road conductor), it is formed in the insulating barrier 101 (the first insulating barrier) and is connected to conductive layer 301 (the first conductive layer); And via conductor (323b) (the 6th via conductor), it is formed in the insulating barrier 102 (the second insulating barrier) and is connected to conductive layer 302 (the second conductive layer).Below, explain the structure of each via conductor in the wiring plate 10 of present embodiment with reference to Fig. 7 and Fig. 8.
In Fig. 7 and Fig. 8, the length (D311) of via conductor (311b) is greater than the length (D331) of via conductor (321b).In addition, the length (D321) of via conductor (312b) is greater than the length (D341) of via conductor (322b).In the present embodiment, the length (D341) of the length (D331) of via conductor (321b) and via conductor (322b) equals the thickness (D2) of insulating barrier 102 separately.The length (D311) of via conductor (311b) is corresponding with the summation of the thickness (D110) of the thickness (D1) of insulating barrier 101 and insulator (101a).
In addition, the width (D312) on the basal surface (F311) of via conductor (311b) is greater than the width (D332) on the basal surface (F331) of via conductor (321b).Width (D322) on the basal surface (F321) of via conductor (312b) is greater than the width (D342) on the basal surface (F341) of via conductor (322b).
Namely, in the wiring plate 10 of present embodiment, via conductor (311b) is longer than via conductor (321b), and the basal surface (F311) of via conductor (311b) has the width greater than the basal surface (F331) of via conductor (321b); And via conductor (312b) is longer than via conductor (322b), and the basal surface (F321) of via conductor (312b) has the width greater than the basal surface (F341) of via conductor (322b).According to such structure, the width of longer via conductor that trends towards being applied in thermal stress is larger, has increased thus the connection reliability of longer via conductor.As a result, be easy to guarantee the required connection reliability of two lip-deep via conductors of electronic building brick 200, thereby so that also be easy to guarantee to relate to high connecting reliability in all electrical connections (path connection) of electronic building brick 200.
In the wiring plate 10 of present embodiment, via conductor (341b, 342b) is stacked on respectively on the via conductor (321b, 322b), so that shorter to the distance of pad (P12) (so to the IC chip that for example is installed on the pad) from the electrode (210,220) (particularly bottom (210c, 220c)) of electronic building brick 200.Except make via conductor (321b, 322b) short, above stacked structure further reduces length of arrangement wire.Length of arrangement wire between MLCC and the IC chip reduces, and loop inductance reduces, and thinks and improved the HF switch behavior.
Although stacked structure is reducing on the length of arrangement wire effectively, the worry of the thermal stress increase on the following via conductor when existing stacking via conductor.For this problem, in the wiring plate 10 of present embodiment, not stacking via conductor on the longer via conductor that trends towards being applied in thermal stress (311b, 312b) (upper via conductor is from these via conductors).By adopting such structure, the thermal stress that has suppressed on the via conductor (311b, 312b) surpasses the permission level.
In the wiring plate 10 of present embodiment, motherboard is electrically connected to pad (P11), and IC chip 2001 (seeing Fig. 3) is electrically connected to pad (P12).Therefore, reduced electrical impedance or noise between electronic building brick 200 and the IC chip 2001.As a result, improved the performance of IC chip 2001.
In via conductor (311b, 312b, 321b, 322b), the ratio of the width on the basal surface and the length of via conductor is (D312/D311, D322/D321, D332/D331 respectively, D342/D341) preferably in 0.5 to 4.0 scope, more preferably in 1.0 to 2.5 scope.
Width (D313) on the open surfaces (F312) in hole (311a) is greater than the width (D333) on the open surfaces (F332) of hole (321a).Width (D323) on the open surfaces (F322) in hole (312a) is greater than the width (D343) on the open surfaces (F342) of hole (322a).
In Fig. 2, the length (D371) of via conductor (313b) roughly is equal to each other with the length (D381) of via conductor (323b).
In Fig. 7 and Fig. 8, be formed on the degree of depth (D334) of the recess (R3) in the terminal pad (321c) of via conductor (321b) less than the degree of depth (D314) of the recess (R1) in the terminal pad that is formed on via conductor (311b) (311c).In addition, be formed on the degree of depth (D344) of the recess (R4) in the terminal pad (322c) of via conductor (322b) less than the degree of depth (D324) of the recess (R2) in the terminal pad that is formed on via conductor (312b) (312c).
In addition, the A/F (D335) of recess (R3) is less than the A/F (D315) of recess (R1).The A/F (D345) of recess (R4) is less than the A/F (D325) of recess (R2).
Preferably, the ratio (D334/D314) of the degree of depth (D334) of recess (R3) and the degree of depth (D314) of recess (R1) is in 0.03 to 0.5 scope, and the ratio (D344/D324) of the degree of depth (D324) of the degree of depth (D344) of recess (R4) and recess (R2) is in 0.03 to 0.5 scope.In addition, preferably, the former ratio (D334/D314) is in 0.05 to 0.25 scope, and the latter's ratio (D344/D324) is in 0.05 to 0.25 scope.
In the wiring plate 10 of present embodiment, because the basal surface (F311) of via conductor (311b) has the large width of basal surface (F331) than via conductor (321b), trend towards the degree of depth (D334) greater than the recess (R3) in the terminal pad that is formed on via conductor (321b) (321c) so be formed on the degree of depth (D314) of the recess (R1) in the terminal pad (311c) of via conductor (311b).In addition, because the basal surface (F321) of via conductor (312b) has the large width of basal surface (F341) than via conductor (322b), trend towards the degree of depth (D344) greater than the recess (R4) in the terminal pad that is formed on via conductor (322b) (322c) so be formed on the degree of depth (D324) of the recess (R2) in the terminal pad (312c) of via conductor (312b).So stacked outermost flatness trends towards being lower than stacked outermost flatness on second surface (F2) side of substrate 100 on the first surface of substrate 100 (F1) side.
If the flatness of base portion insulating barrier via conductor large or that be formed in the base portion insulating barrier is less, then be easy to have less L (line)/S (space) or than a kind of like this base portion insulating barrier conductive pattern (comprising for the terminal that electronic building brick or wiring plate are installed) formation of small terminal pitch.In the present embodiment, the pad (P11) of first surface (F1) side has formed the terminal of another wiring plate of being used for need not high flat degree (such as motherboard etc.), and the pad (P12) of second surface (F2) side has formed the terminal (seeing Fig. 3) of the IC chip 2001 that needing to be used for high flat degree.Be installed in the terminal pitch of the IC chip 2001 on the pad (P12) less than the terminal pitch that is installed in the motherboard on the pad (P11).Therefore, make the wiring plate 10 of present embodiment with high yield.In addition, according to above structure, be easy to form pad (P12) (terminal that is used for IC chip 2001) with finer pitch.In addition, according to above structure, when at pad (P11) and (P12) upper surface is installed respectively, be easy to guarantee required installation reliability.
As shown in Figure 7 and Figure 8, in the wiring plate 10 of present embodiment, conductive layer 110 by metal forming (such as Copper Foil etc.) (110a), for example electroless plating copper (110b) and for example electrolytic copper plating (110c) consist of.Each free for example electroless plating copper (110b) of via conductor (311b, 312b) and for example electrolytic copper plating (110c) consist of.The electroless plating layer (110b) of conductive layer 110 and electro deposition (110c) and via conductor (311b) or electroless plating layer (110b) (312b) and electro deposition (110c) be integrally formed (continuously) separately.In the present embodiment, via conductor (313b) has and via conductor (311b) or (312b) identical structure.
In addition, conductive layer 120 by metal forming (such as Copper Foil) (120a), for example electroless plating copper (120b) and for example electrolytic copper plating (120c) consist of.Each free for example electroless plating copper (120b) of via conductor (321b, 322b) and for example electrolytic copper plating (120c) consist of.The electroless plating layer (120b) of conductive layer 120 and electro deposition (120c) and via conductor (321b) or electro deposition (322b) (120b) and electro deposition (120c) be integrally formed (continuously) separately.In the present embodiment, via conductor (323b) has and via conductor (321b) or (322b) identical structure.
In addition, conductive layer 140 by metal forming (such as Copper Foil) (140a), for example electroless plating copper (140b) and for example electrolytic copper plating (140c) consist of.Each free for example electroless plating copper (140b) of via conductor (341b, 342b) and for example electrolytic copper plating (140c) consist of.The electroless plating layer (140b) of conductive layer 140 and electro deposition (140c) and via conductor (341b) or electroless plating layer (140b) (342b) and electro deposition (140c) be integrally formed (continuously) separately.In the present embodiment, conductive layer 130 has the structure identical with conductive layer 140.Via conductor (333b, 343b) has and via conductor (341b) or (342b) identical structure separately.
Yet, more than be not unique selection.The layer structure of each conductive layer and each via conductor (quantity of layer and every layer material) can freely be determined.For example, can omit metal forming.
As shown in Figure 7, the electrode 210 (top (210a) and bottom (210c) only are shown among Fig. 7) that is connected with respectively the basal surface (F331) of the basal surface (F311) of via conductor (311b) and via conductor (321b) is formed by the first electrode layer 2101 and the second electrode lay 2102.In addition, as shown in Figure 8, the electrode 220 (top (220a) and bottom (220c) only are shown among Fig. 8) that is connected with respectively the basal surface (F341) of the basal surface (F321) of via conductor (321b) and via conductor (322b) is formed by the first electrode layer 2201 and the second electrode lay 2202.Each is for example made the first electrode layer (2101,2201) by nickel, and the second electrode lay (2102,2202) each is for example made by copper facing.The first electrode layer (2101,2201) is separately as the kind layer that for example is used to form (electro deposition) the second electrode lay (2102,2202).
In the wiring plate 10 of present embodiment, the upper surface (F13) that makes conductive layer 301 (Fig. 2) and (Fig. 2) roughening respectively of the upper surface (F14) of conductive layer 302, and the first electrode surface (F411) that does not make electrode 210 (Fig. 2) and the second electrode surface (F412) (Fig. 2) and first electrode surface (F421) of electrode 220 (Fig. 2) and (Fig. 2) roughening of the second electrode surface (F422).Because such difference on roughening is processed, the first electrode surface (F411, F421) and the second electrode surface (F412, F422) 10 mean roughness (Rzjis) separately are all less than any 10 mean roughness (Rzjis) on the upper surface (F14) of the upper surface (F13) of conductive layer 301 and conductive layer 302.
In the wiring plate 10 of present embodiment, the upper surface (F14) that makes the upper surface (F13) of conductive layer 301 and conductive layer 302 separately roughening to have 10 larger mean roughness.So, be easy to obtain between conductive layer 301 and the insulating barrier 101 and the height adhesiveness between conductive layer 302 and the insulating barrier 102.In the present embodiment, the upper surface of conductive layer (110,120,130,140) has and the upper surface (F13) of conductive layer 301 or 302 or (F14) identical roughness separately.Therefore, such upper surface and the adhesiveness between the insulating barrier formed thereon etc. have respectively been improved.
Below, show the preferred exemplary of the size in the wiring plate 10 of present embodiment.
In Fig. 5 A, the width (D21) on the length direction of electronic building brick 200 (direction X) for example is approximately 1000 μ m, and the width (D22) on the horizontal direction of electronic building brick 200 (direction Y) for example is approximately 500 μ m.The width (D23) on the top of electrode 210 (210a) for example is approximately 230 μ m.In the present embodiment, the width of the bottom of electrode 210 (210c) is identical with the width (D23) of top (210a).
The top (210a) of electrode 210 (outer electrode on the first first type surface (F31) and the second first type surface (F32)) and the area of bottom (210c) for example are approximately 0.115mm2 (=230 μ m * 500 μ m) separately.The area of the top of electrode 210 (210a) and bottom (210c) is preferably 0.2mm2 or less separately.
In Fig. 7 and Fig. 8, the thickness of main body 201 (D201) for example is approximately 110 μ m.The thickness (D221) on the thickness (D211) on the top of electrode 210 (210a) and the top (220a) of electrode 220 for example is approximately 15 μ m separately.The thickness (D222) of the thickness (D212) of the bottom of electrode 210 (210c) and the bottom (220c) of electrode 220 for example is approximately 15 μ m separately.In the present embodiment, the summation of the thickness (D222) of the bottom (220c) of the thickness (D221) on the top (220a) of the thickness (D201) of the summation of the thickness (D212) of the bottom (210c) of the thickness (D211) on the top (210a) of the thickness of main body 201 (D201), electrode 210 and electrode 210 (below be called the first component thickness) and main body 201, electrode 220 and electrode 220 (below be called the second component thickness) is roughly the same.Yet this is not unique selection, and the first component thickness and the second component thickness can differ from one another.
In the present embodiment, the first component thickness or the second component thickness are corresponding with the thickness (D200) of electronic building brick 200.Here, if the first component thickness and the second component thickness differ from one another, then the larger thickness (D200) with electronic building brick 200 is corresponding.
In the present embodiment, the size of electrode 220 and electrode 210 is measure-alike.Yet this is not unique selection, and electrode 210 and electrode 220 can have the size that differs from one another.
In Fig. 6, the pitch (D24) of via conductor (311b, 312b) for example is approximately 720 μ m.In the present embodiment, the pitch of via conductor (321b, 322b) is identical with pitch (D24).
In Fig. 6, the width (D101) on the length direction (direction X) of cavity (R10) for example is approximately 1080 μ m, and the width (D102) on the horizontal direction (direction Y) of cavity (R10) for example is approximately 580 μ m.Electronic building brick 200 for example is approximately 80 μ m (=width (D101)-width (D21)) with the gap of cavity (R10) on length direction (direction X), and for example is approximately 80 μ m (=width (D102)-width (D22)) at horizontal direction (direction Y).
In Fig. 2, the thickness of substrate 100 (D10) for example is approximately 150 μ m.The thickness (D12) of the thickness of conductive layer 301 (D11) and conductive layer 302 for example is approximately 15 μ m separately.In the present embodiment, the thickness of conductive layer 301 (D11) is identical with the thickness (D12) of conductive layer 302.Yet this is not unique selection, and the thickness of conductive layer 301 and 302 can differ from one another.
In the present embodiment, the summation of the thickness (D12) of the thickness (D11) of the thickness of substrate 100 (D10), conductive layer 301 and conductive layer 302 is greater than the thickness (D200) of the electronic building brick 200 that comprises electrode (210,220).So electronic building brick 200 is contained in the cavity (R10) by whole, so that electronic building brick 200 is difficult for receiving impact.
In Fig. 2, the thickness (D2) of the thickness of insulating barrier 101 (D1) and insulating barrier 102 for example is approximately 25 μ m separately.In the present embodiment, for example the thickness (D2) with insulating barrier 102 is identical for the thickness of insulating barrier 101 (D1).Yet this is not unique selection, and they can differ from one another.
In Fig. 7 and Fig. 8, the thickness (D110) of insulator (101a) for example is approximately 40 μ m.The 3rd surface (F3) of the thickness (D110) of insulator (101a) and height and the electronic building brick 200 of the upper surface (F13) of conductive layer 301 (poor (measures of dispersion) corresponding (seeing Fig. 2) between the height of the first electrode surface (F411, F421) particularly.
In Fig. 2, the thickness of insulating barrier 103 (D3) for example is approximately 25 μ m separately with the thickness (D4) of insulating barrier 104.In the present embodiment, the thickness of insulating barrier 103 (D3) is identical with the thickness (D4) of insulating barrier 104.Yet this is not unique selection, and they can differ from one another.
In Fig. 2, the thickness (D16) of the thickness (D14) of the thickness of conductive layer 110 (D13), conductive layer 120, the thickness (D15) of conductive layer 130 and conductive layer 140 for example is approximately 15 μ m separately.The thickness (D16) of the thickness (D14) of the thickness of conductive layer 110 (D13), conductive layer 120, the thickness (D15) of conductive layer 130 and conductive layer 140 is for example mutually the same.Yet this is not unique selection, and they can differ from one another.
Here, more than the thickness of each conductive layer be to record as base portion (zero) by the upper surface that utilizes its lower insulating barrier (if the words of lower accumulation section are core substrate) separately, and the thickness of each insulating barrier is (the seeing Fig. 2) that records as base portion (zero) by the upper surface that utilizes its lower conductiving layer separately.
In Fig. 7 and Fig. 8, the length (D311) of via conductor (311b) and the length (D321) of via conductor (312b) for example are approximately 65 μ m separately, and the length (D341) of the length (D331) of via conductor (321b) and via conductor (322b) for example is approximately 50 μ m separately.In the present embodiment, the length (D311) of via conductor (311b) is identical with the length (D321) of via conductor (312b), and the length (D331) of via conductor (321b) is identical with the length (D341) of via conductor (322b).Yet this is not unique selection, and they can differ from one another.
In the present embodiment, as mentioned above, the length (D311) of via conductor (311b) is greater than the length (D331) of via conductor (321b), and the length (D321) of via conductor (312b) is greater than the length (D341) of via conductor (322b).
In Fig. 9 to Figure 12, the width (D312) on the basal surface (F311) of via conductor (311b) (Fig. 7) with the basal surface (F321) of via conductor (312b) on width (D322) (Fig. 8) for example be approximately separately 80 μ m.Width (D332) on the basal surface (F331) of via conductor (321b) (Fig. 7), the width (D342) on the basal surface (F341) of via conductor (322b) (Fig. 8), the width (D372) on the basal surface (F371) of via conductor (313b) (Fig. 2) and the width (D382) on the basal surface (F381) of via conductor (323b) (Fig. 2) for example be approximately separately 60 μ m.In the present embodiment, (D312, D322) is mutually the same for width, and width (D332, D342, D372, D382) is mutually the same.Yet this is not unique selection, and they can differ from one another.
In the present embodiment, as mentioned above, width (D312) on via conductor (311b) basal surface (F311) is greater than the width (D332) on the basal surface (F331) of via conductor (321b), and the width (D322) on the basal surface (F321) of via conductor (312b) is greater than the width (D342) on the basal surface (F341) of via conductor (322b).
In the present embodiment, the ratio (D312/D311, D322/D321, D332/D331, D342/D341) of the width on the basal surface of the via conductor of each and length for example is approximately 1.2 in the via conductor (311b, 312b, 321b, 322b).
In Fig. 9 to Figure 12, the width (D313) on the open surfaces (F312) of hole (311a) (Fig. 7) with the open surfaces (F322) in hole (312a) on width (D323) (Fig. 8) for example be approximately separately 105 μ m.Width (D333) on the open surfaces (F332) in hole (321a) (Fig. 7), the width (D343) on the open surfaces (F342) of hole (322a) (Fig. 8), the width (D373) on the open surfaces (F372) of hole (313a) (Fig. 2) and the width (D383) on the open surfaces (F382) of hole (323a) (Fig. 2) for example be approximately separately 75 μ m.In the present embodiment, (D313, D323) is mutually the same for width, and width (D333, D343, D373, D383) is mutually the same.Yet this is not unique selection, and they can differ from one another.
In the present embodiment, as mentioned above, width (D313) on the open surfaces (F312) in hole (311a) is greater than the width (D333) on the open surfaces (F332) of hole (321a), and the width (D323) on the open surfaces (F322) of hole (312a) is greater than the width (D343) on the open surfaces (F342) of hole (322a).
In Fig. 9 to Figure 12, the width (D316) of the terminal pad (311c) of via conductor (311b) (Fig. 7) and the width (D326) of the terminal pad (312c) of via conductor (312b) (Fig. 8) for example be approximately separately 155 μ m.The width (D336) of the terminal pad (321c) of via conductor (321b) (Fig. 7), the width (D346) of the terminal pad (322c) of via conductor (322b) (Fig. 8), the width (D376) of the terminal pad (313c) of via conductor (313b) (Fig. 2) and the width (D386) of the terminal pad (323c) of via conductor (323b) (Fig. 2) for example be approximately separately 120 μ m.In the present embodiment, (D316, D326) is mutually the same for width, and width (D336, D346, D376, D386) is mutually the same.Yet this is not unique selection, and they can differ from one another.
In Fig. 7 and Fig. 8, the degree of depth (D324) that is formed on the degree of depth (D314) of the recess (R1) in the terminal pad (311c) and is formed on the recess (R2) in the terminal pad (312c) for example is approximately 20 μ m separately.The degree of depth (D344) that is formed on the degree of depth (D334) of the recess (R3) in the terminal pad (321c) and is formed on the recess (R4) in the terminal pad (322c) for example is approximately 2 μ m separately.
In the present embodiment, as mentioned above, the degree of depth (D334) of recess (R3) is less than the degree of depth (D314) of recess (R1), and the degree of depth (D344) of recess (R4) is less than the degree of depth (D324) of recess (R2).
In the present embodiment, the degree of depth (D334) of recess (R3) for example is approximately 0.1 with the ratio (D334/D314) of the degree of depth (D314) of recess (R1), and the ratio (D344/D324) of the degree of depth (D324) of the degree of depth (D344) of recess (R4) and recess (R2) for example is approximately 0.1.
In Fig. 9 to Figure 12, the A/F (D315) of recess (R1) (Fig. 7) and the A/F (D325) of recess (R2) (Fig. 8) for example be approximately separately 80 μ m.The A/F (D335) of recess (R3) (Fig. 7), the A/F (D345) of recess (R4) (Fig. 8), the A/F (D375) of recess (R71) (Fig. 2) and the A/F (D385) of recess (R72) (Fig. 2) for example be approximately separately 20 μ m.In the present embodiment, (D315, D325) is mutually the same for width, and width (D335, D345, D375, D385) is mutually the same.Yet this is not unique selection, and they can differ from one another.
In the present embodiment, as mentioned above, the A/F (D335) of recess (R3) is less than the A/F (D315) of recess (R1), and the A/F (D345) of recess (R4) is less than the A/F (D325) of recess (R2).
Below, method for the manufacture of the wiring plate 10 of present embodiment is described.Figure 14 is content and the flow chart sequentially that schematically shows for the manufacture of the wiring plate 10 of present embodiment.
In the step (S11) of Figure 14, for wiring plate 10 is prepared core substrate, and form conductive layer on its two surface.
Particularly, shown in Figure 15 A, prepare the copper-clad laminated body of bilateral 1000 as parent material.The copper-clad laminated body 1000 of bilateral by the substrate 100 with first surface (F1) and second surface (F2) relative with it, be formed on the metal forming 1001 (for example Copper Foil) on the first surface (F1) of substrate 100 and the metal forming 1002 (for example Copper Foil) that is formed on the second surface (F2) of substrate 100 consists of.In the present embodiment, substrate 100 is made by solidify (C stage) glass epoxy resin fully in this stage.
Shown in Figure 15 B, use for example CO2 laser, by forming hole (1003a) from first surface (F1) side irradiating laser on the copper-clad laminated body 1000 of bilateral, and by forming hole (1003b) from second surface (F2) side irradiating laser on the copper-clad laminated body 1000 of bilateral.Roughly the same position on X-Y plane forms hole (1003a, 1003b), then connects to produce the through hole (300a) that connects the copper-clad laminated body 1000 of bilateral.The shape of through hole (300a) is formed for example hourglass shape.The boundary of hole (1003a) and hole (1003b) is (Fig. 1) corresponding with narrowing portion (300c).Ear Mucosa Treated by He Ne Laser Irradiation on Ear Mucosa Treated by He Ne Laser Irradiation on the first surface (F1) and the second surface (F2) can simultaneously or carry out separately.Preferably afterwards through hole (300a) is carried out scrubbing (desmearing) having formed through hole (300a).Suppressed the conduction (short circuit) do not expected by scrubbing.In addition, in order to strengthen the absorption efficiency of laser, can before Ear Mucosa Treated by He Ne Laser Irradiation, carry out black oxidation on the surface of metal forming (1001,1002) and process.Here, can replace utilizing laser to form through hole (300a) by drill bit or via etching.Yet, utilize laser to be easier to carry out retrofit.
Shown in Figure 15 C, for example utilize the plate face to be plated in the upper and middle formation of through hole (300a) copper facing 1004 of metal forming (1001,1002).Particularly, at first by the execution electroless plating, and then by utilizing electroless plated film in plating liquor, to carry out the electrolysis plating as kind of layer, form thus coating 1004.So, in through hole (300a), be filled with coating 1004, and form via conductors (300b).
Utilize etching solution and for example by the resist layer of lithographic printing (lithographic technique) patterning, will be formed on the first surface (F1) of substrate 100 or each conductive layer pattern on the second surface (F2).Particularly, resist layer is with pattern covers each conductive layer corresponding with conductive layer 301 or 302, and the part that is not covered by resist layer of each conductive layer (part that the peristome by resist layer exposes) is etched away.Such etching is not limited to wet type, and also can adopt dry type.
So, shown in Figure 15 D, form conductive layer 301 at the first surface (F1) of substrate 100, and at second surface (F2) the formation conductive layer 302 of substrate 100.In the present embodiment, conductive layer (301,302) has for example three-decker of Copper Foil (lower floor), electroless plating copper (intermediate layer) and electrolytic copper plating (upper strata) formation separately.Can in the conductive layer 301 or 302 such as step in the back (such as the step that is used for positioning electronic assembly 200 etc.) use, form alignment mark.In addition, can from conductive layer 301 or 302, remove conductor (seeing below Figure 17 A and Figure 17 B of explanation) in the part corresponding with the shape of peristome (R100).
Then, as required, the upper surface (F14) that for example makes the upper surface (F13) of conductive layer 301 and conductive layer 302 by chemical etching is roughening separately.Yet this is not unique selection, and can freely select for the method for roughening.Etching can be wet type or dry type.
In the step (S12) of Figure 14, as shown in figure 16, for example from first surface (F1) side irradiating laser on substrate 100, with form in the substrate 100 respectively at the peristome (R100) (seeing Figure 18) of first surface (F1) and second surface (F2) upper shed.Particularly, for example shown in Figure 17 A, with the mode irradiating laser of the shape (seeing Fig. 6) of drawing peristome (R100), so that the zone corresponding with peristome (R100) in the substrate 100 cut away from its periphery.The angle of irradiating laser is set to for example be approximately perpendicular to the first surface (F11) of substrate 100.
Before above Ear Mucosa Treated by He Ne Laser Irradiation, preferably, for example shown in Figure 17 A, can the mode corresponding with the shape of peristome (R100) to remove the conductive layer 301 (if necessary, also removing its relative conductive layer 302) on the substrate 100.Alternatively, shown in Figure 17 B, can remove along the Ear Mucosa Treated by He Ne Laser Irradiation path conductive layer 301 (if necessary, also removing its relative conductive layer 302) on the substrate 100.By processing conductive layer 301 shown in Figure 17 A or Figure 17 B, because position and the shape of peristome (R100) are clear, so be easy to aim at Ear Mucosa Treated by He Ne Laser Irradiation.In addition, by remove conductor from the processing part, Ear Mucosa Treated by He Ne Laser Irradiation becomes and is easier to.
When from first surface (F11) side on substrate 100 during irradiating laser, the amount of laser processing reduces towards second surface (F12) side, and the removal surface of substrate 100 trends towards taper.Yet, when substrate 100 is thin, be easy to obtain to be approximately perpendicular to the removal surface of the first type surface (first surface (F11) or second surface (F12)) of substrate 100.
When forming peristome (R100) (cavity), can be only from a side irradiating laser of substrate 100, perhaps can be from the both sides of substrate 100 irradiating laser simultaneously.Alternatively, form by the side irradiating laser from substrate 100 end of with hole (non-through hole) afterwards, thereby can form peristome (R100) (cavity) to connect the bottom from the opposite side irradiating laser.
If necessary, preferably carrying out black oxidation before Ear Mucosa Treated by He Ne Laser Irradiation processes.The method that is used to form peristome (R100) is not limited to utilize laser, and also can use for example mould.In addition, forming peristome (R100) afterwards, preferably carry out if necessary scrubbing or soft etching.
So, as shown in figure 18, obtain to have first surface (F1), its relative second surface (F2) and connect to the substrate 100 of the peristome (R100) of second surface (F2) from first surface (F1).In the present embodiment, peristome (R100) is made of the hole that connects substrate 100.The wall towards peristome (R100) of substrate 100 (F10) for example is approximately perpendicular to the first type surface of substrate 100.
Peristome (R100) is formed the spatial accommodation for electronic building brick 200.Below, the part (spatial accommodation that is used for electronic building brick 200) that has from the upper surface (F13) of conductive layer 301 to the thickness of the upper surface (F14) of conductive layer 302 is called cavity (R10).
In the step (S13) of Figure 14, electronic building brick 200 is contained in the cavity (R10) of substrate 100.
Particularly, as shown in figure 19, at a side (for example, second surface (the F2)) supporting body 1005 of setting example as being made by PET (PETG) of substrate 100.Thus, cover an opening of cavity (R10) (hole) by supporting body 1005.In the present embodiment, supporting body 1005 is adhesiveness sheet material (for example, band), and is bonded on substrate 100 sides.For example by stacked supporting body 1005 is bonded to substrate 100 (particularly conductive layer 302).
As shown in figure 20, from a side (Z1 side) relative with the capped opening (hole) of cavity (R10) electronic building brick 200 is placed in the cavity (R10).
At first, prepare electronic building brick 200.Electronic building brick 200 has main body 201 and the electrode (210,220) (each outer electrode) that is formed on the main body 201, and wherein main body 201 has the first first type surface (F31) and second first type surface (F32) relative with it.On first first type surface (F31) and the second first type surface (F32) of main body 201, form the part (top (210a) and bottom (210c), perhaps top (220a) and bottom (220c)) of outer electrode (electrode 210 or 220).
In the present embodiment, comprise that the thickness of electronic building brick 200 of outer electrode (electrode (210,220)) is less than the thickness (summation of the thickness of the thickness of the thickness of substrate 100, conductive layer 301 and conductive layer 302) of cavity (R10).
For example utilize the assembly erector that the electric appliance component 200 of above preparation is placed in the cavity (R10).For example, by the maintenance electronic building bricks 200 such as vacuum fixture, with electronic building brick 200 be sent to cavity (R10) top part (Z1 side), make electronic building brick 200 reduce in vertical direction, be placed in the cavity (R10) and be placed on the supporting body 1005.So, as shown in figure 21, electronic building brick 200 is placed in the cavity (R10) (peristome (R100)) with the mode of first surface (F1) towards equidirectional with the 3rd surface (F3).
In the present embodiment, the 4th surface (F4) of the upper surface of conductive layer 302 (F14) and electronic building brick (200) (the second electrode surface that particularly illustrates later (F412, F422)) is positioned on the flat surfaces of supporting body 1005 separately.Therefore, these several surfaces are in roughly mutually the same height (Z coordinate) to be located, and produces thus flush surfaces.
In the step (S14) of Figure 14, as shown in figure 22, form the insulating barrier 101 of semi-solid preparation (B stage) and metal forming 1006 Copper Foil of resin (as have) at conductive layer 301.Insulating barrier 101 is for example made by the prepreg (prepreg) of thermosetting glass epoxy resin.
In the present embodiment, because the thickness of cavity (R10) is located so the 3rd surface (F3) of the upper surface of conductive layer 301 (F13) and electronic building brick 200 (the first electrode surface that particularly illustrates later (F411, F421)) is in differing heights (Z coordinate) each other greater than the thickness of the electronic building brick 200 that has comprised outer electrode.Therefore, between insulating barrier 101 and electronic building brick 200, form the gap.
As shown in figure 23, to insulating barrier 101 pressurizations of semi-solid preparation, so that resin flows out in the cavity (R10) from insulating barrier 101.So, as shown in figure 24, be filled with insulator (101a) (from the resin of insulating barrier 101) between the electronic building brick 200 in cavity (R10) and substrate 100 or the insulating barrier 101.
In the time of in insulator (101a) is filled in cavity (R10), that potting resin (insulator (101a)) and electronic building brick 200 is tentatively bonding.Especially, potting resin is heated to can supporting electric sub-component 200 degree.Thus, the electronic building brick 200 that comes support bearing body 1005 to support by potting resin now.Then, remove as shown in figure 25 supporting body 1005.
In this stage, insulator (101a) (potting resin) and insulating barrier 101 only are semi-solid preparations, are not completely crued.Yet this is not unique selection, and insulator (101a) and insulating barrier 101 can for example be completely crued in this stage.
In the step (S15) of Figure 14, form lower accumulation section.
Particularly, as shown in figure 26, form insulating barrier 102 and metal forming 1007 Copper Foil of resin (as have) at the electrode (210,220) of conductive layer 302 and electronic building brick 200.Insulating barrier 102 is made by for example prepreg of thermosetting glass epoxy resin.Be bonded to conductive layer 302 and electrode (210,220) by the insulating barrier 102 that for example pressurizes semi-solid preparation (B stage), and this insulating barrier is heated so that insulating barrier (101,102) is cured separately.
So, form insulating barrier (insulating barrier 101 and insulator (101a)) (seeing Figure 27) on the 3rd surface (F3) of first surface (F1), conductive layer 301 and the electronic building brick 200 of substrate 100.In addition, form insulating barrier (insulating barrier 102 and insulator (101a)) (seeing Figure 27) on the 4th surface (F4) of second surface (F2), conductive layer 302 and the electronic building brick 200 of substrate 100.
In the present embodiment, insulating barrier (101,102) is solidified simultaneously.By the two lip-deep insulating barriers (101,102) that are formed on substrate 100 are solidified simultaneously, suppressed the warpage in the substrate 100.As a result, be easy to make substrate 100 attenuation.
The resin that has flowed out from insulating barrier 102, can resin be flowed out from insulating barrier 102 by pressurization here, so that also can form insulator (101a) with the resin that flows out from insulating barrier 101.
In addition, above pressurization and heat treatment can be divided into a plurality of processes.In addition, can be individually or side by side heat-treat and pressurize.
In the present embodiment, electronic building brick 200 entirely is contained in the cavity (R10).Therefore, at above-mentioned pressure dwell, impact on the electronic building brick 200 that is difficult for being applied in the cavity (R10).
As shown in figure 27, for example utilize laser in insulating barrier 101 and metal forming 1006, to form hole (311a, 312a, 313a) (each via hole), and in insulating barrier 102 and metal forming 1007, form hole (321a, 322a, 323a) (each via hole).Hole (311a, 312a) connects metal forming 1006, insulating barrier 101 and insulator (101a) separately, and arrives the electrode 210 or 220 of electronic building brick 200.Hole (313a) connects metal forming 1006 and insulating barrier 101, and arrives conductive layer 301.Hole (321a, 322a) connects metal forming 1007 and insulating barrier 102 separately, and arrives the electrode 210 or 220 of electronic building brick 200.Hole (323a) connects metal forming 1007 and insulating barrier 102, and arrives conductive layer 302.Then, carry out if necessary scrubbing.
Owing to do not make the upper surface roughening of electrode 210 and 220 in the present embodiment, so kept high reflectance on the upper surface of electrode 210 and 220.Therefore, think and when having formed above via hole, suppressed the damage from laser in the electrode 210 and 220.
For example utilize electroless plating method upward and in hole (311a to 313a, 321a to 323a) to form for example electroless plating copper film (1008,1009) (seeing Figure 28) in metal forming (1006,1007).Here, before electroless plating, such as can be by absorbing the catalyst of being made by palladium etc. on the surface that is immersed in insulating barrier (101,102).
Utilize lithographic printing or printing etc., (on the electroless plated film 1008) forms the anti-coating 1010 with peristome (1010a) on first surface (F1) side first type surface, and (on the electroless plated film 1009) forms the anti-coating 1011 (seeing Figure 28) with peristome (1011a) on second surface (F2) side first type surface.With peristome (1010a, 1011a) respectively with conductive layer (110,120) patterning (Figure 29) accordingly.
As shown in figure 28, for example utilize pattern plating method, in the peristome (1010a, 1011a) of anti-coating (1010,1011), form respectively for example electrolytic copper plating (1012,1013).Particularly, will be connected to anode as the copper of plating material, and will be connected to negative electrode as the electroless plated film (1008,1009) of material to be plated and be immersed in the plating liquor.Then, apply DC (direct current) voltage so that streaming current between the two poles of the earth, thereby so that copper be deposited on the surface of electroless plated film (1008,1009).So, with electroless plated film 1008 or 1009 and electro deposition 1012 or 1013 filler openings (311a to 313a, 321a to 323a), and formed the via conductor of for example being made by copper facing (311b to 313b, 321b to 323b).
Then, for example utilize predetermined removal solution, remove anti-coating (1010,1011), then remove unnecessary electroless plated film (1008,1009) and metal forming (1006,1007).So, form as shown in figure 29 conductive layer (110,120).The upper surface that for example makes conductive layer (110,120) by chemical etching is roughening separately.In the present embodiment, conductive layer (110,120) for example has the three-decker that Copper Foil (lower floor), electroless plating copper (intermediate layer) and electrolytic copper plating (upper strata) consist of separately.So, finish lower accumulation section.
The kind layer that is used for the electrolysis plating is not limited to electroless plated film.Also can replace electroless plated film (1008,1009) as kind of a layer with sputtered film etc.
In the step (S16) of Figure 14, for example form as shown in figure 30 upper accumulation section.The mode identical with lower accumulation section (that is, by making the stacked and pressurization of insulating barrier and the metal forming Copper Foil of resin (as have), make resin solidification, form via conductor and forming conductive layer (comprise thick good fortune process)) forms upper accumulation section.
In the step (S17) of Figure 14, on insulating barrier (103,104) and conductive layer (130,140), form respectively the solder mask 11 with peristome (11a) and the solder mask 12 (seeing Fig. 1) with peristome (12a).Except the predetermined portions corresponding with peristome (11a, 12a) (pad (P11, P12) etc.), cover respectively conductive layer (130,140) with solder mask (11,12).Such as forming solder mask (11,12) by silk screen printing, spraying and applying, roll coated or stacked etc.
Utilize electrolysis plating or sputter etc., upper at conductive layer (130,140), particularly for example form anticorrosive coat (seeing Fig. 1) by nickel/golden film is made on the surface that is not covered by solder mask (11,12) of pad (P11, P12).Also can process to form the anticorrosive coat of being made by organic protective film by carrying out OSP.
Finished the wiring plate 10 (Fig. 1) of present embodiment by said process.Then, if necessary, carry out electric test (to check electric capacity and insulation etc.) at electronic building brick 200.
Manufacture method according to present embodiment is suitable for making wiring plate 10.Utilize such manufacture method, think to have obtained good wiring plate 10 with low cost.
The wiring plate 10 of present embodiment can be with the circuit board that acts on such as mobile devices such as mobile phones.For example be electrically connected to another wiring plate (such as motherboard) by the pad (P11) that welds wiring plate 10.In addition, as shown in Figure 3, can be for example by welding IC chip 2001 (carries chips) upside-down mounting on the pad (P12) of wiring plate 10.
The invention is not restricted to above execution mode, and for example modification is as follows.
About the via conductor of the electrode 210 that is connected at least electronic building brick 200 or be connected to the via conductor of the electrode 220 of electronic building brick 200, be formed on the via conductor in the insulating barrier 101 and the via conductor that is formed in the insulating barrier 102 can be formed on the position that does not face with each other under the state that electronic building brick 200 is clipped in the middle.Particularly, for example as shown in figure 31, the via conductor that does not face with each other under the state that electronic building brick 200 is clipped in the middle (311b) and via conductor (321b) are selections.The via conductor that does not face with each other under the state that electronic building brick 200 is clipped in the middle (312b) and via conductor (322b) also are selections.In the example shown in Figure 31, via conductor (311b) is formed on (different X-Y coordinate) in the position that does not face with each other with via conductor (321b), and via conductor (312b) is formed on (different X-Y coordinate) in the position that does not face with each other with via conductor (322b).According to such structure, stress seldom concentration of local in electronic building brick 200.
About the via conductor that is connected at least electrode 210 or the via conductor that is connected to electrode 220, the quantity that is formed on the via conductor in the insulating barrier 101 can differ from one another with the quantity that is formed on the via conductor in the insulating barrier 102.For example, shown in figure 32, about the via conductor that is connected at least electrode 210 or the via conductor that is connected to electrode 220, the quantity that is formed on the via conductor in the insulating barrier 101 can be less than the quantity that is formed on the via conductor in the insulating barrier 102.In the example shown in Figure 32, in the via conductor that is connected to electrode 210, a via conductor is formed on (via conductor 311b) in the insulating barrier 101, and two via conductors are formed on (via conductor 321b) in the insulating barrier 102.In addition, in the via conductor that is connected to electrode 220, a via conductor is formed on (via conductor 312b) in the insulating barrier 101, and two via conductors are formed on (via conductor 322b) in the insulating barrier 102.According to such structure, trend towards being applied in the quantity of longer via conductor of thermal stress less than the quantity of shorter via conductor, and be easy to keep the electrode of electronic building brick and the connection reliability between the via conductor not to reduce.In addition, the quantity that is connected to the via conductor of electrode 210 can be different from the quantity of the via conductor that is connected to electrode 220.
As shown in figure 33, the conductive layer that does not have on two surfaces (two first type surfaces) that are formed on substrate 100 is a selection.In the example shown in Figure 33, the thickness of substrate 100 is greater than the thickness of the electronic building brick 200 that comprises electrode 210 (the first lateral electrode) and electrode 220 (the second lateral electrode).The thickness of substrate 100 is corresponding with the thickness of cavity (R10).
The quantity of the layer in the accumulation section can freely be determined.For example, as shown in figure 34, can omit accumulation section.In the example shown in Figure 34, each outermost conductive layer and form respectively pad (P11) or (P12) (external connection terminals) naturally of conductive layer (110,120).
In addition, the quantity of the layer in the accumulation section on first surface (F1) side of substrate with second surface (F2) side at substrate 100 on can be different.Yet, for relieve stresses, consider preferably so that the quantity of the layer in the accumulation section on first surface (F1) side of substrate 100 with second surface (F2) side at substrate 100 on identical so that increase the symmetry of upper surface and lower surface.
As shown in figure 35, can be by in substrate 100, forming a plurality of cavitys (R10) and by obtain to have a plurality of built-in electronic assemblies at each cavity (R10) content nano-electron assembly wiring plate of (for example, electronic building brick (200a, 200b, 200c, 200d)).Alternatively, can in a cavity (R10), hold a plurality of electronic building bricks.
The type of the structure of wiring plate 10, especially its structural member, quality, size, material, shape, the number of plies and position etc. can freely change in the scope that does not deviate from main idea of the present invention.
The shape of the electrode of the chip capacitor in the cavity to be contained in (R10) (peristome) can freely be determined.
Electronic building brick in the cavity to be contained in (R10) (peristome) can be any kind.Can use any electronic building brick, for example, except such as the active block such as IC chip etc. the passive block of capacitor, resistor or coil etc.In addition, the electronic building brick in the cavity to be contained in (R10) can be so that a plurality of element (such as capacitor) integrates (for example modelling).
Substrate 100 (for example core substrate of wiring plate) can be the insulating properties substrate with built-in metal plate (for example Copper Foil).In such substrate 100, owing to metallic plate has improved heat radiation.
Each via conductor that comprises the via conductor that is connected to electronic building brick all is not limited to fill conductor, and can for example be conformal conductor.
The flat shape (X-Y plane) of via conductor, via hole, electronic building brick and cavity (accommodation section) can freely be determined.For example, they can be circular or polygon (such as essentially rectangular, roughly square, roughly hexagon or octangle roughly) roughly.Polygonal angle like this can have any angle, for example approximate right angle, acute angle or obtuse angle or or even circular arc.Yet, reduce the size of cavity for the purpose that increases the wiring zone on the substrate, preferably, the flat shape (X-Y plane) corresponding (namely consistent) of the flat shape of cavity (X-Y plane) and electronic building brick to be held.
In above execution mode, each resin that freely comprises core material of insulating barrier (101,102,103,104) is made.Yet this is not unique selection.For example, in order to ensure the flatness of each interlayer insulating film, the particularly important is the resin that uses the core material comprise the insulating barrier (101,102) that is used to form lower accumulation section.Therefore, even insulating barrier (103,104) does not comprise core material, as long as insulating barrier (101,102) comprises core material, just be easier to obtain required flatness.In addition, if guaranteed required flatness, then insulating barrier 101,102,103 or 104 all need not to comprise core material.
Method for the manufacture of wiring plate is not limited to the order shown in above Figure 14 and content.Order and content can be in the situation that does not deviate from main idea of the present invention modification freely.In addition, can be according to some steps of omission such as behaviours in service.
For example, the method that is used to form each conductive layer is not restricted especially.For example, can use with lower any one or any two or more combination to form conductive layer: the plating of plate face, pattern plating, fully addition process, semi-additive process (SAP), subtractive process, transfer and protuberance method.
Can adopt Wet-type etching or dry-etching to replace utilizing laser.When carrying out etching, think preferably the part that need not to remove with protections such as resists in advance.
Above execution mode and modified example can freely make up.Think preferably, according to suitable combinations of selection such as behaviours in service.For example, the via conductor of any wiring plate shown in Figure 33 to Figure 35 can be to form such as Figure 31 or mode shown in Figure 32.
The wiring plate with built-in electronic assembly according to embodiment of the present invention has such as lower member: substrate, and it has first surface and the second surface relative with it, wherein, forms from first surface and connects peristome to second surface; Electronic building brick, it is arranged in peristome, and have with first surface towards the 3rd surface of equidirectional and with it relative the 4th surface and the first lateral electrode and second lateral electrode relative with it; The first insulating barrier, it is formed on the 3rd surface of electronic building brick; The second insulating barrier, it is formed on the 4th surface of electronic building brick; The first via conductor, it is formed in the first insulating barrier, and the basal surface of this first via conductor is connected to the first lateral electrode; The alternate path conductor, it is formed in the first insulating barrier, and the basal surface of this alternate path conductor is connected to the second lateral electrode; The three-way conductor, it is formed in the second insulating barrier, and the basal surface of this three-way conductor is connected to the first lateral electrode; And four-way road conductor, it is formed in the second insulating barrier, and the basal surface of this four-way road conductor is connected to the second lateral electrode.In such wiring plate, the first via conductor arranges longlyer than the three-way conductor, and the basal surface of the first via conductor has the width greater than the basal surface of three-way conductor, and the alternate path conductor arranges longlyer than four-way road conductor, and the basal surface of alternate path conductor has the large width of basal surface than four-way road conductor.
Comprise the steps: to prepare to have the substrate of first surface and the second surface relative with it according to the manufacture method of the wiring plate with built-in electronic assembly of another embodiment of the present invention; In substrate, form from first surface and connect peristome to second surface; Preparation has the electronic building brick of the 3rd surface and relative with it the 4th surface and the first lateral electrode and second lateral electrode relative with it; Electronic building brick is configured in the substrate in the formed peristome towards the mode of equidirectional with the 3rd surface and first surface; The 3rd surface at electronic building brick forms the first insulating barrier; The 4th surface at electronic building brick forms the second insulating barrier; In the first insulating barrier, form the first via conductor, the basal surface of this first via conductor is connected to the first lateral electrode; In the first insulating barrier, form the alternate path conductor, the basal surface of this alternate path conductor is connected to the second lateral electrode; In the second insulating barrier, form the three-way conductor, this three-way conductor is shorter than the first via conductor, and has the basal surface of the width less than the basal surface of the first via conductor, and the basal surface of this three-way conductor is connected to the first lateral electrode; And in the second insulating barrier, forming four-way road conductor, this four-way road conductor is shorter than alternate path conductor, and has the basal surface of the width less than the basal surface of alternate path conductor, and the basal surface of this four-way road conductor is connected to the second lateral electrode.
According to the embodiment of the present invention, the lateral electrode and the connection reliability between the via conductor that have suppressed electronic building brick in having the thin wiring plate of built-in electronic assembly reduce.In addition, according to the embodiment of the present invention, suppressed that manufacturing step complicates when making the thin wiring plate with built-in electronic assembly.In addition, according to the embodiment of the present invention, the wiring plate with built-in electronic assembly is warpage seldom.
Obviously, according to above teaching, the present invention can carry out a plurality of modification and variation.Therefore, it will be appreciated that, within the scope of the appended claims, can be to implement the present invention such as the mode beyond the mode that specifies herein.
The cross reference of related application
The application based on and require the U. S. application No.61/639 that submitted on April 27th, 2012, the U. S. application No.13/749 that on January 24th, 285 and 2013 submitted to, 059 priority, the full content of these applications is contained in this by reference.
Claims (18)
1. wiring plate comprises:
Substrate, it has peristome, and wherein said peristome connects to the second surface that is positioned at the described substrate of opposite side with respect to the first surface of described substrate from the first surface of described substrate;
Electronic building brick, it is configured in the described peristome, and have the first lateral electrode and the second lateral electrode, wherein said the first lateral electrode and described the second lateral electrode extend to the second surface that is positioned at the described electronic building brick of opposite side with respect to the first surface of described electronic building brick from the first surface of described electronic building brick;
A plurality of insulating barriers, it comprise the first insulating barrier on the first surface of the first surface that is formed on described substrate and described electronic building brick and be formed on the second surface of described substrate and the second surface of described electronic building brick on the second insulating barrier; And
A plurality of via conductors, it comprises:
The first via conductor, it is formed in described the first insulating barrier and has the basal surface that is connected to described the first lateral electrode,
The alternate path conductor, it is formed in described the first insulating barrier and has the basal surface that is connected to described the second lateral electrode,
The three-way conductor, it is formed in described the second insulating barrier and has the basal surface that is connected to described the first lateral electrode, and
Four-way road conductor, it is formed in described the second insulating barrier and has the basal surface that is connected to described the second lateral electrode,
Wherein, the length of described the first via conductor arranges to such an extent that be longer than the length of described three-way conductor, the width of the basal surface of described the first via conductor forms the width greater than the basal surface of described three-way conductor, the length of described alternate path conductor arranges to such an extent that be longer than the length of described four-way road conductor, and the width of the basal surface of described alternate path conductor is greater than the width of the basal surface of described four-way road conductor.
2. wiring plate according to claim 1 wherein, also comprises:
The first conductive layer, it is formed on the first surface of described substrate; And
The second conductive layer, it is formed on the second surface of described substrate,
Wherein, described a plurality of via conductor also comprises:
Five-way road conductor, it is formed in described the first insulating barrier and is connected to described the first conductive layer, and
The 6th via conductor, it is formed in described the second insulating barrier and is connected to described the second conductive layer,
Wherein, the same length of described five-way road conductor and described the 6th via conductor.
3. wiring plate according to claim 1 and 2 wherein, also comprises the outermost conductive layer, and described outermost conductive layer is layered in the second surface side of described substrate, and comprises a plurality of terminals that are configured to install integrated circuit.
4. wiring plate according to claim 1 and 2, wherein,
The ratio of the length of the width of the basal surface of described the first via conductor and described the first via conductor is arranged in 0.5 to 4.0 the scope,
The ratio of the length of the width of the basal surface of described alternate path conductor and described alternate path conductor is arranged in 0.5 to 4.0 the scope,
The ratio of the width of the basal surface of described three-way conductor and the length of described three-way conductor is arranged in 0.5 to 4.0 the scope, and
The ratio of the width of the basal surface of described four-way road conductor and the length of described four-way road conductor is arranged in 0.5 to 4.0 the scope.
5. wiring plate according to claim 1 and 2, wherein,
Described the first via conductor, described alternate path conductor, described three-way conductor and described four-way road conductor each freely fill the plating material make,
Described the first via conductor, described alternate path conductor, described three-way conductor and described four-way road conductor have the terminal pad section with recess separately,
The degree of depth of the recess of described three-way conductor arranges less than the degree of depth of the recess of described the first via conductor, and
The degree of depth of the recess of described four-way road conductor arranges less than the degree of depth of the recess of described alternate path conductor.
6. wiring plate according to claim 5, wherein,
The ratio of the degree of depth of the recess of the degree of depth of the recess of described three-way conductor and described the first via conductor is arranged in 0.03 to 0.5 the scope, and
The ratio of the degree of depth of the degree of depth of the recess of described four-way road conductor and the recess of described alternate path conductor is arranged in 0.03 to 0.5 the scope.
7. wiring plate according to claim 1 and 2 wherein, also comprises being stacked on described three-way conductor and the described four-way road conductor via conductor on one of them.
8. wiring plate according to claim 1 and 2, wherein,
Described a plurality of via conductor comprises a plurality of via conductors that are connected to described the first lateral electrode and a plurality of via conductors that are connected to described the second lateral electrode, and
The via conductor that is formed in described the first insulating barrier is quantitatively different with the via conductor in being formed on described the second insulating barrier.
9. wiring plate according to claim 8, wherein,
Described a plurality of via conductor comprises a plurality of via conductors that are connected to described the first lateral electrode and a plurality of via conductors that are connected to described the second lateral electrode, and
The a plurality of via conductors that are formed in described the first insulating barrier are set to quantitatively less than a plurality of via conductors that are formed in described the second insulating barrier.
10. wiring plate according to claim 1 and 2, wherein,
Described a plurality of via conductor comprises a plurality of via conductors that are connected to described the first lateral electrode and a plurality of via conductors that are connected to described the second lateral electrode, and
The a plurality of via conductors that are formed in described the first insulating barrier form with the position that is formed on a plurality of via conductors in described the second insulating barrier so that the via conductor that is formed in described the first insulating barrier does not face with each other under the state of the described electronic building brick of clamping with the via conductor that is formed in described the second insulating barrier.
11. wiring plate according to claim 1 and 2 wherein, also comprises:
The first conductive layer, it is formed on the first surface of described substrate; And
The second conductive layer, it is formed on the second surface of described substrate,
Wherein, the summation of the thickness of described substrate, described the first conductive layer and described the second conductive layer arranges greater than the thickness of the described electronic building brick that comprises described the first lateral electrode and described the second lateral electrode.
12. wiring plate according to claim 11, wherein, described the second conductive layer, described the first lateral electrode and described the second lateral electrode have the surface that flushes each other.
13. wiring plate according to claim 1 and 2, wherein,
Described electronic building brick has main body, and described main body has the first first type surface, is positioned at second first type surface, the first side surface of opposite side and is positioned at the second side surface of opposite side with respect to described the first side surface with respect to described the first first type surface,
Described the first lateral electrode is so that described the first lateral electrode is formed on the described main body via the mode that described the first side surface extends to described the second first type surface from described the first first type surface, and
Described the second lateral electrode is so that described the second lateral electrode is formed on the described main body via the mode that described the second side surface extends to described the second first type surface from described the first first type surface.
14. wiring plate according to claim 1 and 2, wherein, described electronic building brick is laminated ceramic capacitor.
15. the manufacture method of a wiring plate may further comprise the steps:
Form the peristome that connects substrate, wherein said peristome connects to the second surface that is positioned at the described substrate of opposite side with respect to this first surface from the first surface of described substrate;
The electronic building brick that configuration has the first lateral electrode and the second lateral electrode in the described peristome of described substrate, wherein said the first lateral electrode and described the second lateral electrode extend to the second surface that is positioned at the described electronic building brick of opposite side with respect to the first surface of described electronic building brick from the first surface of described electronic building brick;
Form a plurality of insulating barriers at described substrate, wherein said a plurality of insulating barriers comprise the first insulating barrier on the first surface of the first surface that is positioned at described substrate and described electronic building brick and be positioned at the second surface of described substrate and the second surface of described electronic building brick on the second insulating barrier; And
Form a plurality of via conductors, wherein said a plurality of via conductor comprises: be arranged in the first via conductor and the alternate path conductor of described the first insulating barrier, wherein said the first via conductor has the basal surface and the described alternate path conductor that are connected to described the first lateral electrode and has the basal surface that is connected to described the second lateral electrode; And the three-way conductor and the four-way road conductor that are arranged in described the second insulating barrier, wherein said three-way conductor has the basal surface and the described four-way road conductor that are connected to described the first lateral electrode and has the basal surface that is connected to described the second lateral electrode,
Wherein, the length of described the first via conductor arranges to such an extent that be longer than the length of described three-way conductor, the width of the basal surface of described the first via conductor forms the width greater than the basal surface of described three-way conductor, the length of described alternate path conductor arranges to such an extent that be longer than the length of described four-way road conductor, and the width of the basal surface of described alternate path conductor is greater than the width of the basal surface of described four-way road conductor.
16. the manufacture method of wiring plate according to claim 15 is wherein, further comprising the steps of:
First surface at described substrate forms the first conductive layer; And
Second surface at described substrate forms the second conductive layer,
Wherein, described electronic building brick is formed so that comprise the thickness of the described electronic building brick of described the first lateral electrode and described the second lateral electrode and is set to the summation less than the thickness of described substrate, described the first conductive layer and described the second conductive layer.
17. the manufacture method of wiring plate according to claim 16 is wherein, further comprising the steps of: before the described electronic building brick of configuration, utilize supporting member to cover the described peristome of described substrate from the second surface side of described substrate,
Wherein, disposing described electronic building brick comprises: from the first surface side of the described peristome of described substrate described electronic building brick is placed on the described supporting member in described peristome.
18. according to claim 16 or the manufacture method of 17 described wiring plates, wherein, forming described a plurality of insulating barrier comprises: form described the first insulating barrier, so that form resin insulating barrier at first surface and described first conductive layer of described electronic building brick, and pressurize to utilize the resin that stems from described resin insulating barrier to fill gap between described resin insulating barrier and the described electronic building brick to described resin insulating barrier.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261639285P | 2012-04-27 | 2012-04-27 | |
| US61/639,285 | 2012-04-27 | ||
| US13/749,059 | 2013-01-24 | ||
| US13/749,059 US9215805B2 (en) | 2012-04-27 | 2013-01-24 | Wiring board with built-in electronic component and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103379734A true CN103379734A (en) | 2013-10-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013101587418A Pending CN103379734A (en) | 2012-04-27 | 2013-05-02 | Wiring board with built-in electronic component and method for manufacturing the same |
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| TWI783324B (en) * | 2020-12-15 | 2022-11-11 | 何崇文 | Circuit carrier and manufacturing method thereof |
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| JP2007258542A (en) * | 2006-03-24 | 2007-10-04 | Ngk Spark Plug Co Ltd | Wiring board |
| US20100224397A1 (en) * | 2009-03-06 | 2010-09-09 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
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| JP2007258542A (en) * | 2006-03-24 | 2007-10-04 | Ngk Spark Plug Co Ltd | Wiring board |
| US20100224397A1 (en) * | 2009-03-06 | 2010-09-09 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108122860A (en) * | 2016-11-28 | 2018-06-05 | 台湾积体电路制造股份有限公司 | Encapsulating structure |
| US20190172818A1 (en) * | 2016-11-28 | 2019-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming package structure |
| CN108122860B (en) * | 2016-11-28 | 2021-10-01 | 台湾积体电路制造股份有限公司 | Method for forming packaging structure |
| US11164852B2 (en) | 2016-11-28 | 2021-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming package structure |
| US11817437B2 (en) | 2016-11-28 | 2023-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming package structure |
| TWI783324B (en) * | 2020-12-15 | 2022-11-11 | 何崇文 | Circuit carrier and manufacturing method thereof |
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Application publication date: 20131030 |