CN103379077A - Frame synchronization and symbol synchronization method and device in wireless communication system - Google Patents

Abstract

The invention discloses a frame synchronization and symbol synchronization method and device in a wireless communication system. The method includes the steps of arranging a state machine including an original state, a synchronization signal determining state and a synchronization signal tracking state and determining the positions and the lengths of main synchronization signal detection windows according to the current state of the state machine, wherein gaps exist between the determined main synchronization signal detection windows when the state of the state machine is the synchronization signal tracking state. When sampling signals are received, main synchronization signal detection is only conducted on the sampling signals used for calculating correlation values in the main synchronization signal detection windows, the other sampling signals can not be processed, therefore, unnecessary calculation can be reduced, and the complexity of synchronization calculation can be reduced.

Description

Frame synchronization in the wireless communication system and symbol timing synchronization method and device

Technical field

The present invention relates to the mobile communication technology field, relate in particular to frame synchronization and symbol timing synchronization method and device in a kind of wireless communication system.

Background technology

In the LTE of 3GPP communication system technical standard, terminal equipment needs to detect after start from the master sync signal in the downlink frame of base station (PSS), obtains sector mark (ID), and finishes frame synchronization.During data that terminal equipment comprises in the demodulation downlink frame, also need with downlink frame in each OFDM symbol carry out synchronously.

Fig. 1 is the LTE system frame structure that is used for time division duplex of regulation among the 3GPP TS 36.211.Each frame length is 10ms, comprises the field of two 5ms.The subframe that it is 1ms that each frame is divided into 10 length.Each subframe comprises 14 OFDM symbols.Wherein comprise master sync signal in the 3rd of the 2nd, the 7th subframe the OFDM symbol, signal format such as 3GPP TS 36.211 definition.The master sync signal that the LTE system uses is the ZC sequence of three kinds of different roots, namely has the master sync signal of three types, and submeter represents 0～2 sector ID.Because LTE system master sync signal negligible amounts, and the ZC sequence all has ideal correlation in time domain and frequency domain, therefore can be used for the detection of frame and OFDM symbol with synchronously.

Owing to detect when synchronous at frequency domain, need to be converted into frequency domain and carry out receiving signal, have higher computation complexity, therefore usually use the time domain correlation detection that master sync signal is detected.

When using the time domain correlation detection to detect master sync signal, need the master sync signal sequence of the local storage of calculating relevant with the slip of the sampled signal of reception, and determine the position of master sync signal by detecting correlation peak.In the practical application, if directly calculate the slip correlation peak with the sampled signal that receives, then for each sampled signal, all need computational length to be at most 2048 correlation, computation complexity is very high.

In order to reduce computation complexity, existing master sync signal detector at first uses low pass filter to carry out to received signal low-pass filtering usually, then carries out down-sampled processing.But down-sampled processing has been sacrificed synchronization accuracy when reducing system complexity.In order to address this problem, certain methods considers to use two stage detection, namely at first receives signal with low sampling rate and carries out slightly synchronous the detection, and then receive signal and carry out synchronously detection of essence with high sampling rate.

In the prior art, it is to carry out for all sampled signals that receive that above-mentioned low pass filtered involves down-sampled processing, and according to frame structure shown in Figure 1 as can be known, master sync signal only is arranged in the specific OFDM symbol of a subframe of each 5ms field.Go forward side by side line synchronizing signal when following the tracks of detecting master sync signal, if still all carry out above-mentioned processing for all sampled signals, then can have a large amount of unnecessary computations, especially for the calculating of the data-signal away from from the master sync signal position.

Summary of the invention

In view of this, frame synchronization and symbol timing synchronization method in a kind of wireless communication system are provided among the present invention on the one hand, frame synchronization and sign synchronization device in a kind of wireless communication system are provided on the other hand, in order to reduce unnecessary calculating, reduce the complexity of calculating synchronously.

Frame synchronization in the wireless communication system provided by the present invention and symbol timing synchronization method comprise:

A, setting comprise the state machine of initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode;

B, according to the current state of state machine, determine position and the length of master sync signal detection window; Wherein, gapped between the master sync signal detection window of when the state of state machine is the synchronizing signal tracking mode, determining;

C, according to determined master sync signal detection window, the sampled signal that being used for of receiving calculated the correlation in the described master sync signal detection window slide relevant and Check processing obtain current main sync bit;

D, state machine are determined the current state of state machine, and are returned execution in step B according to described current main sync bit and sync bit detection case before; Wherein, if state machine is initial condition, then enter the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold.

In an embodiment of the invention, described step C comprises:

C1, receive current sampled signal, and record the position of described current sampled signal;

C2, judge that whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, if so, execution in step C3 then; Otherwise, return execution in step C1;

C3, described current sampled signal is carried out low-pass filtering, obtain signal after the filtering;

C4, signal after the described filtering is carried out down-sampled, obtain down-sampled signal;

C5, calculate the correlation of described down-sampled signal and local master sync signal, and the mould value of described correlation is put into described master sync signal detection window;

C6, judge whether described master sync signal detection window is full, if so, execution in step C7 then; Otherwise, wait for that the mould value of new correlation is put into described master sync signal detection window;

C7, with the position of the corresponding down-sampled signal of maximum norm value in the described master sync signal detection window as current main sync bit.

In another execution mode of the present invention, further comprise after the described step C3:

C8, described filtered signal is carried out buffer memory, obtain buffered signal;

Further comprise between described step C7 and the step D:

C9, with before the described current main sync bit and calculate afterwards R _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current main sync bit and extracts; Wherein, R _DsBe reduce sampling frequency;

C10, calculate the correlation of each buffered signal and local master sync signal, obtain the mould value of the correlation of corresponding each buffered signal;

C11, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, the position of the sampled signal that described maximum norm value is corresponding is as current main sync bit.

In an embodiment of the invention, described when continuous N does not trace into synchronizing signal by expection 2 times, enter initial condition or the synchronizing signal acknowledgement state comprises:

When continuous N does not trace into synchronizing signal by expection 2 times, judge whether the detection quality of the master sync signal that current main sync bit is corresponding satisfies the setting requirement, in this way, then enter the synchronizing signal acknowledgement state; Otherwise, enter initial condition;

Perhaps, according to setting in advance, when continuous N does not trace into synchronizing signal by expection 2 times, enter initial condition;

Perhaps, according to setting in advance, when continuous N does not trace into synchronizing signal by expection 2 times, enter the synchronizing signal acknowledgement state.

In an embodiment of the invention, described step B comprises:

When the current state of state machine is initial condition or synchronizing signal acknowledgement state, the master sync signal detection window of the first length is set, and gapless between the described master sync signal detection window; When the current state of state machine is the synchronizing signal tracking mode, the master sync signal detection window of the second length is set, and gapped between the described master sync signal detection window; Described the first length is greater than described the second length.

In an embodiment of the invention, described the first length is more than or equal to the master sync signal transmission cycle.

In an embodiment of the invention, described the first length is: the length at the first protection interval+master sync signal transmission cycle.

In an embodiment of the invention, described the second length is more than or equal to the length of an OFDM symbol, and less than the master sync signal transmission cycle.

In an embodiment of the invention, described the second length is: the length of the length at the second protection interval+OFDM symbol.

In an embodiment of the invention, described step B comprises: satisfy the position that described master sync signal detection window is set: make the desired location of master sync signal to be detected be positioned at the setting regions at the rear portion of described master sync signal detection window.

In an embodiment of the invention, the original position of the master sync signal detection window of described the first length is positioned at: the position of the length at current main sync bit+first protection interval.

In an embodiment of the invention, the original position of the master sync signal detection window of described the second length is positioned at:

In an embodiment of the invention, further comprise among the step B: when the current state of state machine is the synchronizing signal tracking mode, determine position and the length of the auxiliary synchronous signals detection window of at least a type, and gapped between the auxiliary synchronous signals detection window of same type;

Further comprise among the step C: according to determined auxiliary synchronous signals detection window, to the sampled signal that is positioned at described auxiliary synchronous signals detection window that receives slide relevant and Check processing, obtain current auxiliary sync bit;

When state machine is the synchronizing signal tracking mode among the step D, describedly judge whether that tracing into synchronizing signal by expection comprises: judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Describedly judge whether that continuous N does not trace into synchronizing signal by expection 2 times and comprises: judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

In another execution mode of the present invention, further comprise among the step B: when the current state of state machine is the synchronizing signal tracking mode, determine position and the length of the auxiliary synchronous signals detection window of at least a type, and gapped between the auxiliary synchronous signals detection window of same type;

Further comprise among the step C:

C2a, to the auxiliary synchronous signals detection window of each type, judge whether the position of described current sampled signal is positioned at described auxiliary synchronous signals detection window, if so, execution in step C3a then; Otherwise, return execution in step C1;

C3a, described current sampled signal is carried out low-pass filtering, obtain signal after the filtering;

C4a, signal after the described filtering is carried out down-sampled, obtain down-sampled signal;

C5a, calculate the correlation of described down-sampled signal and local auxiliary synchronous signals, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

C6a, judge whether described auxiliary synchronous signals detection window is full, if so, execution in step C7a then; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window;

C7a, with the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window as current auxiliary sync bit output;

When state machine is the synchronizing signal tracking mode among the step D, describedly judge whether that tracing into synchronizing signal by expection comprises: judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Describedly judge whether that continuous N does not trace into synchronizing signal by expection 2 times and comprises: judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

In another execution mode of the present invention, further comprise among the described step B: when the current state of state machine is the synchronizing signal tracking mode, determine position and the length of the auxiliary synchronous signals detection window of at least a type, and gapped between the auxiliary synchronous signals detection window of same type;

Further comprise among the step C:

C2a, to the auxiliary synchronous signals detection window of each type, judge that whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, execution in step C3a then; Otherwise, return execution in step C1;

C3a, described current sampled signal is carried out low-pass filtering, obtain signal after the filtering;

C8a, described filtered signal is carried out buffer memory, obtain buffered signal;

C4a, signal after the described filtering is carried out down-sampled, obtain down-sampled signal;

C5a, calculate the correlation of described down-sampled signal and local auxiliary synchronous signals, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

C6a, judge whether described auxiliary synchronous signals detection window is full, if so, execution in step C7a then; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window;

C7a, with the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window as current auxiliary sync bit output;

C9a, with before the described current auxiliary sync bit and calculate afterwards R _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current auxiliary sync bit and extracts; Wherein, R _DsBe reduce sampling frequency;

C10a, calculate the correlation of each buffered signal and local auxiliary synchronous signals, obtain the mould value of the correlation of corresponding each buffered signal;

C11a, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, the position of the sampled signal that described maximum norm value is corresponding is as current auxiliary sync bit;

When state machine is the synchronizing signal tracking mode among the step D, describedly judge whether that tracing into synchronizing signal by expection comprises: judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Describedly judge whether that continuous N does not trace into synchronizing signal by expection 2 times and comprises: judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

Frame synchronization in the wireless communication system provided by the present invention and sign synchronization device comprise:

State machine, this state machine comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode, be used for the current state according to state machine, determine position and the length of master sync signal detection window, and generate main synchronous detection window, position and the length information of described master sync signal detection window are notified to window detection module group; Wherein, gapped between the master sync signal detection window that state machine is determined when the state of state machine is the synchronizing signal tracking mode; According to the current main sync bit that receives and sync bit detection case before, determine the current state of state machine, wherein, if state machine is initial condition, then enter the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold;

Signal receiving module is used for receiving current sampled signal, and records the position of described current sampled signal;

Window detection module group, be used for according to determined master sync signal detection window, the sampled signal that being used for of receiving calculated the correlation in the described master sync signal detection window slide relevant and Check processing, obtain current main sync bit, and described main sync bit is offered described state machine.

In an embodiment of the invention, described window detection module group comprises:

Described window position comparison module, be used for position and length according to the master sync signal detection window of state machine indication, judge whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, if so, then described current sampled signal is exported to low pass filter blocks;

Described low pass filter blocks is used for described current sampled signal is carried out low-pass filtering, obtains signal after the filtering;

Down-sampled module, down-sampled for signal after the described filtering is carried out, obtain down-sampled signal;

The first correlator is used for calculating the correlation of described down-sampled signal and the master sync signal of local master sync signal generator generation, and the mould value of described correlation is put into described master sync signal detection window;

Described master sync signal detection window is used for judging whether the master sync signal detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the master sync signal detection window is exported as current main sync bit; Otherwise, wait for that the mould value of new correlation is put into described master sync signal detection window.

In an embodiment of the invention, this window detection module group further comprises: signal cache module, the second correlator and the first smart synchronously detection window; Wherein,

Described signal cache module is used for the filtered signal of described low pass filter blocks is carried out buffer memory;

Described the second correlator is used for the current main sync bit of described master sync signal detection window output is calculated R before and afterwards _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current main sync bit and extracts; Calculate the correlation of each buffered signal and local master sync signal, the mould value of the correlation of corresponding each buffered signal is put into the described first smart synchronously detection window; Wherein, R _DsBe reduce sampling frequency;

The described first smart synchronously detection window is used for when the first smart synchronously detection window has expired, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, state machine is exported to as current main sync bit in the position of the sampled signal that described maximum norm value is corresponding.

In an embodiment of the invention, described down-sampled module, the first correlator, master sync signal detection window, signal cache module, the second correlator, the first smart synchronously detection window and state machine consist of a master sync signal test set;

Comprise a master sync signal test set in the described device, be used for successively three kinds of master sync signals being detected, when successfully detecting any master sync signal, export this master sync signal; Perhaps,

Comprise three master sync signal test set in the described device, be used for respectively three kinds of master sync signals being detected; This moment, this device further comprised a genlocing module, was used for locking and exported at first the master sync signal test set of master sync signal until restart next simultaneous operation.

In an embodiment of the invention, when described state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to window detection module group; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time;

Described window detection module group is further used for according to determined auxiliary synchronous signals detection window, the sampled signal that being used for of receiving calculated the correlation in the described auxiliary synchronous signals detection window slide relevant and Check processing, obtain current auxiliary sync bit, and described auxiliary sync bit is offered described state machine.

In another execution mode of the present invention, when described state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to the window position comparison module; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time

Described window position comparison module is further used for judging whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, then described current sampled signal is exported to low pass filter blocks;

This device further comprises: third phase closes device, be used for being positioned at the down-sampled signal of auxiliary synchronous signals detection window, calculate the correlation of the auxiliary synchronous signals of described down-sampled signal and local auxiliary synchronous signals generator generation, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

Described auxiliary synchronous signals detection window is used for judging whether described auxiliary synchronous signals detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window is exported as current auxiliary sync bit; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window.

In another execution mode of the present invention, this device further comprises: third phase closes device, the 4th correlator and the second smart synchronously detection window;

When described state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to the window position comparison module; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

Described window position comparison module is further used for judging whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, then described current sampled signal is exported to low pass filter blocks;

Described third phase closes device and is used for being positioned at the down-sampled signal of auxiliary synchronous signals detection window, calculate the correlation of the auxiliary synchronous signals of described down-sampled signal and local auxiliary synchronous signals generator generation, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

Described auxiliary synchronous signals detection window is used for judging whether described auxiliary synchronous signals detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window is exported as current auxiliary sync bit; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window;

Described the 4th correlator is used for the current auxiliary sync bit of described auxiliary synchronous signals detection window output is calculated R before and afterwards _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current auxiliary sync bit and extracts; Calculate the correlation of each buffered signal and local auxiliary synchronous signals, the mould value of the correlation of corresponding each buffered signal is put into the described second smart synchronously detection window; Wherein, R _DsBe reduce sampling frequency;

The described second smart synchronously detection window is used for when the second smart synchronously detection window has expired, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, state machine is exported to as current auxiliary sync bit in the position of the sampled signal that described maximum norm value is corresponding.

In an embodiment of the invention, described down-sampled module, the first correlator, master sync signal detection window, third phase pass device, auxiliary synchronous signals detection window, signal cache module, the second correlator, the first smart synchronously detection window, the 4th correlator, the second smart synchronously detection window and synchronization signal detection group of state machine formation;

Comprise a synchronization signal detection group in the described device, be used for successively three kinds of master sync signals being detected, when successfully detecting any master sync signal, export this master sync signal; Perhaps,

Comprise three synchronization signal detection groups in the described device, be used for respectively three kinds of master sync signals being detected; This moment, this device further comprised a genlocing module, was used for locking and exported at first the synchronization signal detection group of master sync signal until restart next simultaneous operation.

Can find out from such scheme, a state machine that comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode is set among the present invention, and according to the current state of state machine, determine position and the length of master sync signal detection window; Wherein, gapped between the master sync signal detection window of when the state of state machine is the synchronizing signal tracking mode, determining.Like this, when receiving sampled signal, can be only that the required sampled signal of calculating of the correlation that is positioned at described master sync signal detection window is carried out the slip of master sync signal is relevant and detect, other sampled signal can not processed, thereby can reduce unnecessary calculating, reduce the complexity of calculating synchronously.

In addition, when in the embodiment of the invention sampled signal being carried out low pass and down-sampled processing, it is relevant and detect that buffer memory is used for carrying out two stage slip without the signal of down-sampled processing, do not sacrifice net synchronization capability when reducing computation complexity.In addition, this thick the detection synchronously with smart two stages of detecting synchronously in the embodiment of the invention detected and can be received signal with fixed sample rate, and so, radio frequency part only need be worked under bandwidth corresponding to fixed sample rate and be got final product, and realizes easily.

In addition, in the embodiment of the invention, open a plurality of detection window by the synchronizing signal tracking mode at state machine, when detecting master sync signal, other signal in the frame structure is detected, thereby can improve the reliability of detection.After opening a plurality of detection window, any one detection window detects effectively can keep synchronous tracking mode.

Description of drawings

Fig. 1 is the LTE system frame structure schematic diagram that is used for time division duplex of regulation among the 3GPP TS 36.211.

Fig. 2 is the exemplary process diagram of the frame synchronization in the wireless communication system and symbol timing synchronization method in the embodiment of the invention one.

Fig. 3 is the state transition diagram of state machine in the embodiment of the invention.

Fig. 4 be in the embodiment of the invention according to the current state of state machine, determine the position of master sync signal detection window and the schematic diagram of length.

Fig. 5 to Fig. 7 shows the schematic flow sheet under different current states of state machine in the embodiment of the invention one.Wherein, Fig. 5 is the handling process schematic diagram of state machine when initial condition; Fig. 6 is the handling process schematic diagram of state machine when the synchronizing signal acknowledgement state; Fig. 7 is the handling process schematic diagram of state machine when the synchronizing signal tracking mode.

Fig. 8 is the exemplary block diagram of the frame synchronization in the wireless communication system and sign synchronization device in the embodiment of the invention one.

Fig. 9 is the exemplary block diagram of the frame synchronization in the wireless communication system and sign synchronization device in the embodiment of the invention two.

Figure 10 and Figure 11 are respectively detection probability and the received signal to noise ratio curve when using the inventive method in different conditions machine parameter configuration under additive white gaussian noise channels and the fading channel model.

Figure 12 and Figure 13 are respectively false alarm rate and the received signal to noise ratio curve when using the inventive method in different conditions machine parameter configuration under additive white gaussian noise channels and the fading channel model.

Embodiment

In the embodiment of the invention, consider when carrying out frame synchronization and OFDM sign synchronization with master sync signal that the detection quality of master sync signal can produce larger impact to systematic function.For example, if master sync signal position probing mistake, then portable terminal correctly demodulation the total data in the corresponding frame, can produce a very large impact receptivity.This step scheme of will seeking common ground can reduce the impact of radio communication channel environment, exports one and stablizes correct synchronizing signal for receiver subsequent treatment module.

In order to reach this purpose, can design synchronous state machine and come master sync signal is followed the tracks of.In the prior art, synchronous state machine is independent of the signal processing operation usually, and only is used for affirmation and the tracking of synchronizing signal.Consider in the embodiment of the invention processing section of synchronous state machine and signal is combined, so that when being in different conditions in system, computing that can the control signal processing section, thereby the amount of calculation of control signal processing section reach the purpose that reduces computation complexity.In addition, when synchronous state machine is in different conditions, can provide different information in the control signal processing section, thereby reach the purpose that improves net synchronization capability and reduce complexity.

During specific implementation, a state machine that comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode can be set in the method for synchronous of the embodiment of the invention.Afterwards, can according to the current state of state machine, determine position and the length of master sync signal detection window; Wherein, the master sync signal detection window of determining when the state of state machine is the synchronizing signal tracking mode is gapped.And then can be according to determined master sync signal detection window, the sampled signal that being used for of receiving calculated the correlation in the described master sync signal detection window slide relevant and Check processing, obtain current main sync bit, other sampled signal that receives can not processed; State machine is determined the current state of state machine, and is returned the current state of executive basis state machine according to described current main sync bit and sync bit detection case before, determines the position of master sync signal detection window and the operation of length.

Wherein, the slide method of relevant and Check processing of the sampled signal of being used for of receiving being calculated the correlation in the described master sync signal detection window can have multiple.For example, can adopt low-pass filtering of the prior art and down-sampled processing; Also can adopt two stage detection method of the prior art, namely at first receive signal with low sampling rate and carry out thick synchronously detection, and then carry out essence with high sampling rate reception signal and detect synchronously.In addition, can also adopt the two stage detection method of introducing in the embodiment of the invention.Perhaps, can also adopt other detection method.

For example, during specific implementation, can receive current sampled signal, and the position of recording described current sampled signal, judge whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, if so, then current sampled signal is carried out low-pass filtering, down-sampled and correlation value calculation, and the mould value of the correlation that calculates is put into the master sync signal detection window.When the master sync signal window is expired, the position of the corresponding down-sampled signal of maximum norm value in the described master sync signal detection window is exported as current main sync bit.State machine is determined the current state of state machine, and is returned the current state of executive basis state machine according to described current main sync bit and sync bit detection case before, determines the position of master sync signal detection window and the operation of length.

During specific implementation, can adopt processing method of the prior art to carry out two stage detection in the said process, namely at first receive signal with low sampling rate and carry out thick synchronously detection, and then carry out essence with high sampling rate reception signal and detect synchronously.

In addition, consider that this method of the prior art needs the radio frequency part of system to work fast, has certain realization difficulty under bandwidth corresponding to plurality of sampling rates.

In the embodiment of the invention, can also receive signal with fixed sample rate, above-mentioned signal to this fixed sample rate be carried out the current main sync bit that down-sampled processing detects afterwards detect synchronously as thick.Simultaneously, further will carry out buffer memory to the signal that current sampled signal is carried out after the low-pass filtering, after obtaining the above-mentioned thick current main sync bit that detects synchronously, further will described current main sync bit from buffer memory before with calculate afterwards R _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current main sync bit and extracts.Wherein, R _DsBe reduce sampling frequency.Afterwards, calculate the correlation of each buffered signal and local master sync signal, obtain the mould value of the correlation of corresponding each buffered signal; Choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, the position of the sampled signal that described maximum norm value is corresponding is as current main sync bit, namely smartly detects synchronously.Sync bit detection case before state machine can reach according to the current main sync bit that described essence detects synchronously afterwards, determine the current state of state machine, and return the current state of executive basis state machine, determine the position of master sync signal detection window and the operation of length.

When after the mobile communication terminal device start or indication synchronizing function module carry out synchronous after, state machine enters initial condition.The sync bit detection case of state machine before reaching according to current main sync bit when determining the current state of state machine, if state machine is initial condition, then enters the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and preamble is worked as in output; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, work as preamble according to the synchronizing signal that traces into by the expection output of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold.

State machine is in the current state according to state machine, when determining the position of master sync signal detection window and length, when if the current state of state machine is initial condition or synchronizing signal acknowledgement state, the master sync signal detection window of the first length then can be set, and gapless between the described master sync signal detection window; When if the current state of state machine is the synchronizing signal tracking mode, the master sync signal detection window of the second length then can be set, and gapped between the described master sync signal detection window.Wherein, the first length is greater than described the second length.

Correspondingly, the synchronizer in the embodiment of the invention can comprise: state machine, signal receiving module and window detection module group.

Wherein, state machine comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode, be used for the current state according to state machine, determine position and the length of master sync signal detection window, and generate main synchronous detection window, position and the length information of described master sync signal detection window are notified to window detection module group; Wherein, gapped between the master sync signal detection window that state machine is determined when the state of state machine is the synchronizing signal tracking mode; According to the current main sync bit that receives and sync bit detection case before, determine the current state of state machine, wherein, if state machine is initial condition, then enter the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold;

Signal receiving module is used for receiving current sampled signal, and records the position of described current sampled signal;

Window detection module group, be used for according to determined master sync signal detection window, the sampled signal that being used for of receiving calculated the correlation in the described master sync signal detection window slide relevant and Check processing, obtain current main sync bit, and described current main sync bit is offered state machine; Other sampled signal that receives can not processed.

During specific implementation, window detection module group can adopt the method for low-pass filtering of the prior art and down-sampled processing to realize; Also can adopt two stage detection method of the prior art, namely at first receive signal with low sampling rate and carry out thick synchronously detection, and then carry out the smart method realization that detects synchronously with high sampling rate reception signal.In addition, can also adopt the two stage detection method of introducing in the embodiment of the invention to realize.Perhaps, can also adopt other detection method to realize.

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, the preferred embodiment among the present invention is elaborated.

Embodiment one

In the present embodiment one, the situation that receives signal take fixed sample rate is as example, and is provided with two stage synchronous detection, namely slightly detects synchronously and smartly detects synchronously.

Fig. 2 is the exemplary process diagram of the frame synchronization in the wireless communication system and symbol timing synchronization method in the embodiment of the invention one.As shown in Figure 2, the method comprises the steps:

Step 201 arranges the state machine that comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode.

Fig. 3 is the state transition diagram of state machine in the embodiment of the invention.As shown in Figure 3, when the initial condition of state machine, begin to detect master sync signal; After detecting master sync signal, state machine enters the synchronizing signal acknowledgement state; The master sync signal that affirmation detects when the synchronizing signal acknowledgement state, as be confirmed whether that continuous N detects master sync signal in desired location 1 time, in this way, then finish master sync signal and confirm; Otherwise, keep the synchronizing signal acknowledgement state; Confirming to enter the synchronizing signal tracking mode behind the master sync signal, master sync signal is being followed the tracks of frame synchronizing signal with stable output; If when the synchronizing signal tracking mode, continuous N 2 is lost the synchronizing signal of following the tracks of, then can enter initial condition; Otherwise, keep the synchronizing signal tracking mode.Some also can directly enter synchronizing signal acknowledgement state (as shown in phantom in FIG.) by the synchronizing signal tracking mode in using.Wherein, M1 is the first setting threshold, and M2 is the second setting threshold.

Step 202 according to the current state of state machine, is determined position and the length of master sync signal detection window.

In this step, when the position of described master sync signal detection window is set, should make the desired location of master sync signal to be detected be positioned at the afterbody of described master sync signal detection window as far as possible, as be positioned at the setting regions at master sync signal detection window rear portion, postpone to reduce to detect.

When after the mobile communication terminal device start or indication synchronizing function module carry out synchronous after, state machine enters initial condition.

In this step, when the current state of state machine was initial condition, state machine can use long master sync signal detection window, and gapless between the master sync signal detection window is undetected to avoid occurring master sync signal.For LTE frame structure shown in Figure 1; the length that the master sync signal detection window can be set is held the data of a master sync signal transmission cycle (being 5ms among Fig. 1) at least; the length that for example, the master sync signal detection window can be set is the length+5ms at the first protection interval.Wherein, the length at the first protection interval can be set to the length of LTE systemic circulation prefix, can certainly be other length, such as the length of an OFDM symbol.At this moment, the master sync signal detection window can be positioned at original position.

When the current state of state machine was the synchronizing signal acknowledgement state, state machine can use long master sync signal detection window, gapless between the master sync signal detection window.For LTE frame structure shown in Figure 1, the plan of establishment in the time of equally can be by initial condition namely arranges the length of master sync signal detection window: be the first protection interval length+one master sync signal transmission cycle (as, 5ms).The original position that the master sync signal detection window is set simultaneously is: the position of the length at current main sync bit+first protection interval.Wherein, the length at the first protection interval can be set to the length of LTE systemic circulation prefix, can certainly be other length, such as the length of an OFDM symbol.

When the current state of state machine was the synchronizing signal tracking mode, state machine uses short master sync signal detection window, and was gapped between the master sync signal detection window.For LTE frame structure shown in Figure 1, the length that the master sync signal detection window can be set is: the length of the length at the second protection interval+OFDM symbol.The original position that the master sync signal detection window is set simultaneously is:

Wherein, the length at the second protection interval can be set to 2 times of LTE systemic circulation prefix length.

Fig. 4 shows in the embodiment of the invention according to the current state of state machine, determines the position of master sync signal detection window and a schematic diagram of length.

As shown in Figure 4, when the initial condition (IS) of state machine, be provided with the master sync signal detection window of a 5ms length, and successfully detect a master sync signal, be the position shown in the dark-shaded solid rectangular line frame, state machine enters synchronizing signal acknowledgement state (CS).

Synchronizing signal acknowledgement state at state machine, the master sync signal detection window of a 5ms length can be set equally, its original position is set to the position of the length at current main sync bit+first protection interval, successfully detect a master sync signal (CS in the accompanying drawing (S) represents successfully to detect corresponding master sync signal) this moment, owing to also do not reach the number of times that continuous success detects, so state machine remains on the synchronizing signal acknowledgement state; Under this state, the original position of the master sync signal detection window of continuation 5ms length is set to the position of the length at current main sync bit+first protection interval, but this time successfully do not detect master sync signal (CS in the accompanying drawing (F) expression does not successfully detect corresponding master sync signal) by desired location (being the position of current main sync bit+5ms), but detect an interference signal, it is the position shown in the light shaded rectangle dotted line frame, owing to successfully do not detect master sync signal by desired location, be that positional fault appears in master sync signal, then synchronous state machine is thought and is confirmed unsuccessfully, reaffirm the master sync signal that newly detects, remain on the synchronizing signal acknowledgement state; And the original position of master sync signal detection window is set to the position of interference signal based on current detection, because it is interference signal, therefore not successfully detect master sync signal in desired location corresponding to this interference signal (i.e. the position of current main sync bit+5ms corresponding to this interference signal), but detecting again an interference signal, state machine remains on the synchronizing signal acknowledgement state; The original position of master sync signal detection window is set based on the position of current interference signal again, because it is interference signal, therefore successfully do not detect master sync signal in desired location corresponding to this interference signal, but arriving master sync signal in the another one position probing, state machine remains on the synchronizing signal acknowledgement state; Based on current detection to the position of master sync signal the original position of master sync signal detection window is set, this time detect master sync signal in desired location; Based on the position of the master sync signal of current detection the original position of master sync signal detection window is set, successfully detects again master sync signal in desired location.So far successfully detect master sync signal continuous three times, i.e. synchronous state machine affirmation master sync signal occurs with 5 milliseconds fixed intervals, and state machine enters synchronizing signal tracking mode (TS).

In the said process, for the master sync signal detection window that has cross section, in the rear master sync signal detection window of determining with the master sync signal detection window of determining before in cross section correlation the mould value directly the appropriate section from definite before master sync signal detection window obtain, to avoid double counting.

Synchronizing signal tracking mode at state machine, the master sync signal detection window of the length of OFDM symbol lengths+2 times LTE systemic circulation prefix is set, its original position is set to the position of the length of current main sync bit+5ms-LTE systemic circulation prefix, and successfully detect master sync signal, the current length that keeps afterwards the master sync signal detection window, the original position of master sync signal detection window is set based on the master sync signal that detects, be the position that original position is set to the length of current main sync bit+5ms-LTE systemic circulation prefix, master sync signal is followed the tracks of.

Step 203 receives current sampled signal, and records the position of described current sampled signal.

Step 204 judges whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, and if so, then execution in step 205; Otherwise, can current sampled signal not carried out subsequent treatment, and return and carry out this step 203.

In this step, if the correlation of calculating location n, required sampled signal can be for from position n to n+N _PssTherefore-1 sampled signal when judging whether current sampled signal is used for correlation in the calculating master sync signal detection window, can be judged the correlation of corresponding current location n, and whether the position of the sampled signal that receives is between n to n+N _PssBetween-1, the calculating of concrete correlation is referring to the formula in the step 208 (3).

Wherein, N _Pss=S _L* T _SymBe sampled point number, S _LBe sample rate, T _SymBe the defined OFDM symbol lengths of 3GPP LTE standard.

Step 205 is carried out low-pass filtering to described current sampled signal, obtains signal after the filtering; Distinguish afterwards execution in step 206 and step 207.

In this step, the sampled signal of establishing reception is r (n), and low-pass filter coefficients is f _Lp(n), 0≤n≤N _Fir, then can process the sampled signal that receives by following formula (1), obtain the signal r after the low-pass filtering _Lp(n).

$r_{\mathrm{lp}}\left(n\right)=r\left(n\right)\⊗f_{\mathrm{lp}}\left(n\right)---\left(1\right)$

N _FirBe the length of FIR low-pass filter coefficients,

The expression convolution algorithm.

For the LTE system, the design of low-pass filter coefficients should so that the passband of filter with end band according to 3GPP LTE wireless mobile communications Specification Design.For example, pass band width is the bandwidth of master sync signal, is 472.5kHz, is the total bandwidth frequency of the unloaded ripple of master sync signal and reservation with frequency only, is 547.5kHz.

Step 206 is carried out buffer memory to described filtered signal, and buffered signal is used in step 211.

In this step, can be with r _Lp(n) put into the signal buffer.

Step 207 is carried out down-sampledly to signal after the described filtering, obtain down-sampled signal.

In this step, can be to r _Lp(n) carry out down-sampledly, shown in (2), sample rate is down to S _L

$r_{\mathrm{lp}}^{\mathrm{ds}}\left(n\right)=r_{\mathrm{lp}}\left({\mathrm{nR}}_{\mathrm{ds}}\right)---\left(2\right)$

In the formula (2), R _DsBe reduce sampling frequency, by the presently used sample rate S of system _HDetermine, i.e. R _Ds=S _H/ S _LSample rate S _LLeast sampling rate for being determined by the master sync signal bandwidth is generally 960kHz.S _HBe the sample rate of LTE specification recommends, its value is S _LIntegral multiple, so R _DsBe generally positive integer.

Step 208 is calculated the correlation of described down-sampled signal and local master sync signal, and the mould value of described correlation is put into described master sync signal detection window.

Wherein, the magnitude calculation method of correlation can be suc as formula shown in (3):

$c_{\mathrm{coarse}}\left(n\right)=|\underset{i=0}{\overset{N_{\mathrm{pss}}-1}{\mathrm{\Σ}}}{r}_{\mathrm{lp}}^{\mathrm{ds}}(n+i)*{\mathrm{PSS}}_L\left(i\right)|---\left(3\right)$

In the formula (3), PSS _L(i) be the sampling of master sync signal on time domain, sample rate is S _L, amount to N _Pss=S _L* T _SymIndividual sampled point, T _SymBe the defined OFDM symbol lengths of 3GPP LTE standard.

Step 209 judges whether described master sync signal detection window is full, if so, and execution in step then, 210; Otherwise, wait for that the mould value of new correlation is put into described master sync signal detection window.

Step 210 is exported the position of the corresponding down-sampled signal of maximum norm value in the described master sync signal detection window as current main sync bit (being thick sync position detection).

Step 211 is calculated R before and afterwards with described current main sync bit _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current main sync bit and extracts.Wherein, R _DsBe reduce sampling frequency.

The position of calculating the required buffered signal of correlation in this step can obtain according to formula (4).

Step 212 is calculated the correlation of each buffered signal and local master sync signal, obtains the mould value of the correlation of corresponding each buffered signal.

Be calculated according to the following formula and amount to 2R _DsThe mould value of-1 correlation:

$c_{\mathrm{fine}}\left(n\right)=|\underset{i=0}{\overset{N_{\mathrm{pss}}{R}_{\mathrm{ds}}-1}{\mathrm{\Σ}}}{r}_{\mathrm{lp}}(n+i)*{\mathrm{PSS}}_L^{\mathrm{us}}\left(i\right)|,$ N _coarse-R _ds+1≤n≤N _coarse+R _ds-1(4)

N wherein _CoarseBe the current main sync bit that calculates in the step 210, i.e. thick sync bit.In the formula (4)

${\mathrm{PSS}}_L^{\mathrm{us}}\left(n\right)=\left\{\begin{array}{cc}{\mathrm{PSS}}_L(n/R_{\mathrm{ds}})& \mathrm{mod}(n,R_{\mathrm{ds}})=0\\ 0& \mathrm{mod}(n,R_{\mathrm{ds}})\≠0\end{array}\right.---\left(5\right)$

Step 213 is chosen the maximum norm value from the mould value of the correlation of corresponding each buffered signal, the position of the sampled signal that described maximum norm value is corresponding is as current main sync bit (being smart sync bit).

Step 214, state machine is determined the current state of state machine, and is returned execution in step 202 according to described current main sync bit (being smart sync bit) and sync bit detection case before.

According to the analysis in the step 202 as can be known, in this step, if state machine is initial condition, then enter the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N 1 time detects near synchronizing signal (namely detecting master sync signal desired location) by expection, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace near synchronizing signal (namely desired location, detecting master sync signal) by expection, in this way, then keep the synchronizing signal tracking mode, and preamble is worked as in output; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then state machine is thought synchronization loss, can enter initial condition or synchronizing signal acknowledgement state, otherwise, preamble worked as according to the synchronizing signal that traces into by the expection output of last time.

In this step, when continuous N does not trace into synchronizing signal by expection 2 times, then state machine can select to enter initial condition or synchronizing signal tracking mode according to the detection quality of the last master sync signal.That is, judge whether the detection quality of the master sync signal that current main sync bit is corresponding satisfies the setting requirement, in this way, then enter the synchronizing signal tracking mode; Otherwise, enter initial condition.For example, can judge the size of the mould value of the correlation that the last master sync signal detects, if it then enters the synchronizing signal acknowledgement state, otherwise enter initial condition greater than setting thresholding TH.

Perhaps, this moment, state machine also can enter synchronizing signal acknowledgement state or initial condition according to fixed solution.As, can be fixedly installed for: when continuous N does not trace into synchronizing signal by expection 2 times, change all the time initial condition over to, or change all the time the synchronizing signal acknowledgement state over to.

When terminal equipment shut down, above-mentioned flow process finished.When terminal equipment indication restarts then to re-execute above-mentioned flow process when synchronous.

In other embodiments of the invention, can omit above-mentioned steps 206 and step 211～213.And carry out two stage detection by processing method of the prior art, namely at first receiving signal with low sampling rate carries out thick synchronously detection, and then carries out essence with high sampling rate reception signal and detect synchronously.

Fig. 5 to Fig. 7 shows the schematic flow sheet under different current states of state machine in the embodiment of the invention one.Wherein, Fig. 5 is the handling process schematic diagram of state machine when initial condition; Fig. 6 is the handling process schematic diagram of state machine when the synchronizing signal acknowledgement state; Fig. 7 is the handling process schematic diagram of state machine when the synchronizing signal tracking mode.

During the state machine initialization, can enter initial condition, and confirmation of synchronization counter Tracked PSS is set is 0.Wherein, the quantity of the master sync signal that arrives of the value representation Continuous Tracking of confirmation of synchronization counter Tracked PSS.

As shown in Figure 5, the handling process of state machine when initial condition comprises the steps:

Step 501 records current main sync bit (being smart sync bit).

Step 502 makes confirmation of synchronization counter Tracked PSS+1, and enters the synchronizing signal acknowledgement state.

Step 503 is determined position and the length of the master sync signal detection window under the synchronizing signal acknowledgement state, and is finished.

In this step, the length that the master sync signal detection window can be set is the length+5ms at the first protection interval, and the original position of master sync signal detection window can be the position of the length at: current main sync bit+first protection interval.Wherein, the length at the first protection interval can be set to the length of LTE systemic circulation prefix, can certainly be other length, such as the length of an OFDM symbol.

As shown in Figure 6, the handling process of state machine when the synchronizing signal acknowledgement state comprises the steps:

Step 601 records current main sync bit (being smart sync position detection).

Step 602 judges that whether current main sync bit appears at desired location, namely judges whether to detect master sync signal by expection.If so, execution in step 603 then; Otherwise, execution in step 608.

In this step, for frame structure shown in Figure 1, when judging whether current main sync bit appears at desired location, can more current main sync bit and the upper main sync bit of record between time difference, if the time difference is 5 ± δ ms, think that then current main sync bit appears on the desired location, namely detects master sync signal by expection.Wherein δ is the assigned error tolerance limit, and its occurrence can design according to wireless channel environment.For example, the length that δ is LTE systemic circulation prefix can be set.

Step 603 makes confirmation of synchronization counter Tracked PSS+1.

Step 604 judges whether the value of confirmation of synchronization counter Tracked PSS reaches the first setting threshold M1, and if so, then execution in step 605; Otherwise, execution in step 609.

Step 605 arranges synchronization loss counter Lost PSS=0, and enters the synchronizing signal tracking mode.

Step 606 is determined position and the length of the master sync signal detection window under the synchronizing signal tracking mode.

In this step, the length that the master sync signal detection window can be set is: the length of the length at the second protection interval+OFDM symbol.The original position that the master sync signal detection window is set simultaneously is: Wherein, the length at the second protection interval can be set to 2 times of LTE systemic circulation prefix length; Can certainly be other length, such as the length of 2 times of OFDM symbols.

Step 607 is exported current main sync bit, and finishes.

Step 608 makes confirmation of synchronization counter Tracked PSS=1, and the synchronizing signal acknowledgement state of hold mode machine.

Step 609 is determined position and the length of the master sync signal detection window under the synchronizing signal acknowledgement state, and is finished.

In this step, the length that the master sync signal detection window can be set is the length+5ms at the first protection interval, and the original position of master sync signal detection window can be the position of the length at: current main sync bit+first protection interval.Wherein, the length at the first protection interval can be set to the length of LTE systemic circulation prefix, can certainly be other length, such as the length of an OFDM symbol.

As shown in Figure 7, the handling process of state machine when the synchronizing signal tracking mode comprises the steps:

Step 701 judges that whether current main sync bit (being smart sync position detection) appears at desired location, namely judges whether to detect master sync signal by expection.If so, execution in step 702 then; Otherwise, execution in step 705.

In this step, for frame structure shown in Figure 1, when judging whether current main sync bit appears at desired location, can more current main sync bit and the upper main sync bit of record between time difference, if the time difference is 5 ± δ ms, think that then current main sync bit appears on the desired location, namely detects master sync signal by expection.Wherein δ is the assigned error tolerance limit, and its occurrence can design according to wireless channel environment.For example, the length that δ is LTE systemic circulation prefix can be set.

Step 702 records and exports current main sync bit.

Step 703 makes synchronization loss counter Lost PSS=0, and the synchronizing signal tracking mode of hold mode machine.

Step 704 is determined position and the length of the master sync signal detection window under the synchronizing signal tracking mode, and is finished.

In this step, the length that the master sync signal detection window can be set is: the length of the length at the second protection interval+OFDM symbol.The original position that the master sync signal detection window is set simultaneously is:

Wherein, the length at the second protection interval can be set to 2 times of LTE systemic circulation prefix length; Can certainly be other length, such as the length of 2 times of OFDM symbols.

Step 705 adds 5ms with a upper main sync bit that records, and obtains new main sync bit, records and export described main sync bit.

Step 706 makes synchronization loss counter Lost PSS+1.

Step 707 judges whether the value of synchronization loss counter Lost PSS reaches the second setting threshold M2, and if so, then execution in step 708; Otherwise, the synchronizing signal tracking mode of hold mode machine, and execution in step 704.

Whether step 708 judges the mould value of the correlation that current main sync bit (being the smart sync position detection in the step 701) is corresponding greater than setting thresholding TH, and if so, then execution in step 709; Otherwise, execution in step 711.

In this step, mainly be to select to jump into which state according to the quality of correlation corresponding to current main sync bit.If the mould value of correlation is higher, then can jumps into the synchronizing signal acknowledgement state, otherwise can jump into initial condition.

Step 709 makes confirmation of synchronization counter Tracked PSS=1, and enters the synchronizing signal acknowledgement state of state machine.

Step 710 is determined position and the length of the master sync signal detection window under the synchronizing signal acknowledgement state, and is finished.

Specific implementation process in this step can be consistent with the description in the step 609.

Step 711 makes confirmation of synchronization counter Tracked PSS=0, and the initial condition that enters state machine.

Step 712 is determined position and the length of the master sync signal detection window under the initial condition, and is finished.

In this step, the length that the master sync signal detection window can be set is the length+5ms at the first protection interval, and the original position of master sync signal detection window can be the position of the length at: current main sync bit+first protection interval.Wherein, the length at the first protection interval can be set to the length of LTE systemic circulation prefix, can certainly be other length, such as the length of an OFDM symbol.

In the practical application, state machine can also be jumped into initial condition or synchronizing signal acknowledgement state according to fixed policy, for example state machine is fixedly jumped into initial condition when the value of synchronization loss counter Lost PSS reaches the second setting threshold M2, or fixedly jumps into the synchronizing signal acknowledgement state.

More than the frame synchronization in the wireless communication system in the embodiment of the invention one and symbol timing synchronization method are described in detail, the below is described in detail frame synchronization and sign synchronization device in a kind of wireless communication system that can realize frame synchronization in the described wireless communication system and symbol timing synchronization method in the embodiment of the invention one again.

Fig. 8 is the exemplary block diagram of the frame synchronization in the wireless communication system and sign synchronization device in the embodiment of the invention one.Shown in the part of the solid line among Fig. 8, this device can comprise: state machine, signal receiving module, window position comparison module, low pass filter blocks, down-sampled module, the first correlator, master sync signal detection window, signal cache module, the second correlator and the first smart synchronously detection window.

Wherein, state machine comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode, be used for the current state according to state machine, determine position and the length of master sync signal detection window, and generate main synchronous detection window, position and the length information of described master sync signal detection window are notified to the window position comparison module.Wherein, gapped between the master sync signal detection window that state machine is determined when the state of state machine is the synchronizing signal tracking mode.In addition, state machine also is used for determining the current state of state machine according to the current main sync bit that receives and sync bit detection case before, wherein, if state machine is initial condition, then enters the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold.

Signal receiving module is used for receiving current sampled signal, and records the position of described current sampled signal.During specific implementation, signal receiving module can comprise radio-frequency transmitter (RF) and D/A converter module (A/D).

The window position comparison module is used for judging whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, if so, then described current sampled signal is exported to low pass filter blocks; Otherwise, can current sampled signal not processed, as current sampled signal being abandoned etc.

Described low pass filter blocks is used for described current sampled signal is carried out low-pass filtering, obtains signal after the filtering.

Down-sampled module is used for signal after the described filtering is carried out down-sampled, obtains down-sampled signal.

The signal cache module is used for the filtered signal of described low pass filter blocks is carried out buffer memory, obtains buffered signal.

The first correlator is used for calculating the correlation of described down-sampled signal and the master sync signal of local master sync signal generator generation, and the mould value of described correlation is put into described master sync signal detection window.

The master sync signal detection window is used for judging whether the master sync signal detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the master sync signal detection window is exported as current main sync bit; Otherwise, wait for that the mould value of new correlation is put into described master sync signal detection window.

The second correlator is used for the current main sync bit of described master sync signal detection window output is calculated R before and afterwards _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current main sync bit and extracts; Calculate the correlation of each buffered signal and local master sync signal, the mould value of the correlation of corresponding each buffered signal is put into the described first smart synchronously detection window.Wherein, R _DsBe reduce sampling frequency.

The first smart synchronously detection window is used for when the first smart synchronously detection window has expired, chooses the maximum norm value from the mould value of the correlation of corresponding each buffered signal, and state machine is exported to as current main sync bit in the position of the sampled signal that described maximum norm value is corresponding.

In other embodiments of the invention, can omit above-mentioned signal cache module, the second correlator and the first smart synchronously detection window, and carry out two stage detection by processing mode of the prior art, namely at first receive signal with low sampling rate and carry out thick synchronously detection, and then carry out essence with high sampling rate reception signal and detect synchronously.

During specific implementation, the down-sampled module in the device shown in Figure 8, the first correlator, master sync signal detection window, signal cache module, the second correlator, the first smart synchronously detection window and state machine can consist of a master sync signal test set.

Then can shown in the part of the solid line among Fig. 8, comprise a master sync signal test set in the device in the embodiment of the invention one, be used for successively three kinds of master sync signals being detected, when successfully detecting any master sync signal, export this master sync signal.

Perhaps, also can shown in the dotted portion among Fig. 8, comprise three master sync signal test set in the device in the embodiment of the invention one, be used for respectively three kinds of master sync signals being detected; This moment, this device further comprised a genlocing module, was used for locking and exported at first the master sync signal test set of master sync signal until restart next simultaneous operation.

Embodiment two

Consider in the LTE system frame structure, also to comprise auxiliary synchronous signals equally definition in 3GPPTS 36.211 of signal format.For the frame structure that is used for tdd systems shown in Figure 1, auxiliary synchronous signals is positioned at the 14th OFDM symbol of the 1st and the 6th subframe.Auxiliary synchronous signals is generated by sector ID and residential quarter ID, after terminal equipment traces into master sync signal, auxiliary synchronous signals form and the required information of other reference signal forms can obtain, therefore these signals can be used for the assist in synchronization detection when the synchronizing signal tracking mode, improve and detect quality.

For further improving the performance of synchronization scenario when the tracking mode, improve and follow the tracks of stability, the synchronization scenario that also can use multiwindow to follow the tracks of in the embodiment of the invention.

During specific implementation, the method for synchronous that multiwindow is followed the tracks of only carries out when state machine enters or keep synchronous tracking mode.Take situation that two detection window are set as example, as a master sync signal detection window and an auxiliary synchronous signals detection window are set.

Wherein the master sync signal detection window is still carried out work according to the method described in the method for synchronous among the embodiment one.The auxiliary synchronous signals detection window is for detection of the synchronizing signal of other position in the frame structure, such as auxiliary synchronous signals.During specific implementation, identical with the detection method of master sync signal to the detection method of auxiliary synchronous signals, but need to be with local signal sequence PSS when calculating correlation _L(n) and Replace with the local signal sequence SSS of auxiliary synchronous signals _L(n) and

As long as any one detects the synchronizing signal of correct position in two detection window, then state machine keeps synchronous tracking mode.If two detection window all do not detect the synchronizing signal of correct position, then to lose coincidence counter and add 1, state machine operates according to the method among the embodiment one.

When synchronous state machine left from the synchronizing signal tracking mode, detection window reverted to 1, and as only keeping the master sync signal detection window, its length and location all gets final product according to embodiment one described method setting.

Namely for the implementation in this enforcement two, should be in the step 202 among the embodiment one: according to the current state of state machine, determine number, position and the length of detection window.Still take situation that two detection window are set as example, as under the synchronizing signal tracking mode of state machine, a master sync signal detection window and an auxiliary synchronous signals detection window are set.Wherein definite method of the position of master sync signal detection window and length still realizes according to the description in the step 202 among the embodiment one.Definite method of definite method of the position of auxiliary synchronous signals detection window and length and the position of master sync signal detection window and length is similar.If state machine has just entered the synchronizing signal tracking mode; then can according to current detection to main sync bit extrapolate current auxiliary sync bit; and and then with current auxiliary sync bit+5ms-the 3rd protection interval; obtain the original position of auxiliary synchronous signals detection window, and the length of auxiliary synchronous signals detection window also can be the 3rd protection interval of OFDM symbol+2 times.If state machine is in the maintenance stage of synchronizing signal tracking mode, the auxiliary sync bit that then can arrive according to current detection is determined its original position and length as stated above.

When using the method for synchronous of multiwindow tracking, comprise a plurality of correlators and detection window in the synchronizer, each detection window still is to detect in two stages.The sync bit of each detection window output is all delivered to synchronous state machine, and the synchronous state machine module is processed according to the method described above the sync bit of detection and carried out state transitions.

Fig. 9 shows frame synchronization in the wireless communication system in the embodiment of the invention two and the exemplary block diagram of sign synchronization device.

As shown in Figure 9, this device also comprises except comprising each part shown in Fig. 8: third phase closes device, the 4th correlator and the second smart synchronously detection window.

In the present embodiment two, when state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to the window position comparison module; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

The window position comparison module is further used for judging whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, then described current sampled signal is exported to low pass filter blocks.

Third phase closes device and is used for being positioned at the down-sampled signal of auxiliary synchronous signals detection window, calculate the correlation of the auxiliary synchronous signals of described down-sampled signal and local auxiliary synchronous signals generator generation, and the mould value of described correlation is put into described auxiliary synchronous signals detection window.

The auxiliary synchronous signals detection window is used for judging whether described auxiliary synchronous signals detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window is exported as current auxiliary sync bit; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window.

The 4th correlator is used for the current auxiliary sync bit of described auxiliary synchronous signals detection window output is calculated R before and afterwards _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current auxiliary sync bit and extracts; Calculate the correlation of each buffered signal and local auxiliary synchronous signals, the mould value of the correlation of corresponding each buffered signal is put into the described second smart synchronously detection window.Wherein, R _DsBe reduce sampling frequency.

The second smart synchronously detection window is used for when the second smart synchronously detection window has expired, chooses the maximum norm value from the mould value of the correlation of corresponding each buffered signal, and state machine is exported to as current auxiliary sync bit in the position of the sampled signal that described maximum norm value is corresponding.

In other embodiments of the invention, can omit signal cache module, the second correlator, the first smart synchronously detection window, the 4th correlator and the second smart synchronously detection window among Fig. 9, and carry out two stage detection by processing mode of the prior art, namely at first receive signal with low sampling rate and carry out thick synchronously detection, and then carry out essence with high sampling rate reception signal and detect synchronously.

During specific implementation, the down-sampled module in the device shown in Figure 9, the first correlator, master sync signal detection window, third phase close device, auxiliary synchronous signals detection window, signal cache module, the second correlator, the first smart synchronously detection window, the 4th correlator, the second smart synchronously detection window and state machine can consist of a master sync signal test set.

Then can shown in the part of the solid line among Fig. 9, comprise a master sync signal test set in the device in the embodiment of the invention one, be used for successively three kinds of master sync signals being detected, when successfully detecting any master sync signal, export this master sync signal.

Perhaps, also can shown in the dotted portion among Fig. 9, comprise three master sync signal test set in the device in the embodiment of the invention one, be used for respectively three kinds of master sync signals being detected; This moment, this device further comprised a genlocing module, was used for locking and exported at first the master sync signal test set of master sync signal until restart next simultaneous operation.

Any synchronizing signal of auxiliary synchronous signals general reference except master sync signal herein.

During specific implementation, part or all of part can also can be program code for hardware circuit in the embodiment of the invention one and the embodiment two devices, for the part of realizing by program code, this device can further comprise: processor (not shown) and computer-readable recording medium (not shown).

Wherein, the part of realizing by program code is the program code that is stored in the described computer-readable recording medium.

Described processor is used for carrying out the program code of described computer-readable recording medium.

Use method of the present invention can reduce the computation complexity that the LTE terminal equipment carries out frame synchronization and sign synchronization.By carrying out the detection window location comparison, if the slip correlation corresponding with sampled signal do not drop in any one detection window, then method for synchronous does not carry out any processing to signal, has effectively reduced complexity.The length, position and the quantity that control detection window by state machine is set can reduce the duty ratio of detection window valid interval, especially use the short and nonoverlapping detection window of length when the master sync signal tracking mode, can greatly reduce computation complexity.Following table 1 has provided the computation complexity of the inventive method for one embodiment of the present invention, and with the comparison of control methods, visible method of the present invention can effectively reduce computation complexity.

Table 1

Figure 10 and detection probability (Pd) and the received signal to noise ratio curve that is respectively when using the inventive method in different conditions machine parameter configuration under additive white Gaussian noise (AWGN) channel and the fading channel model shown in Figure 11.Abscissa is the communication signal to noise ratio among the figure, and ordinate is detection probability.M1 and M2 are respectively the first setting threshold and the second setting threshold of describing in the embodiment of the invention.Provided the inventive method detection probability curve under the various state machine configuring conditions among the figure.When M1=1 and M2=1, can be considered without synchronous state machine.Curve among Figure 11 obtains under the suburb macrocell model (SM, Suburban Macro) of 3GPP standard TR25.996 definition and two kinds of fading channel environment of urban macro cell pattern (UM, Urban Macro) respectively.As seen, because the position that the inventive method adopts synchronous state machine to follow the tracks of master sync signal, and in the situation that the master sync signal error detection occurs, utilize the master sync signal positional information of record to produce synchronizing signal, improved synchronous detection probability.

Figure 12 and false alarm rate (Pf) and the received signal to noise ratio curve that is respectively when using the inventive method in different conditions machine parameter configuration under awgn channel and the fading channel model shown in Figure 13.Abscissa is the communication signal to noise ratio among the figure, and ordinate is detection probability.M1 and M2 are respectively the first setting threshold and the second setting threshold of describing in the embodiment of the invention.Provided the inventive method detection probability curve under the various state machine configuring conditions among the figure.When M1=1 and M2=1, can be considered without synchronous state machine.Curve among Figure 13 obtains under the suburb macrocell model (SM, Suburban Macro) of 3GPP standard TR25.996 definition and two kinds of fading channel environment of urban macro cell pattern (UM, Urban Macro) respectively.As seen, the inventive method adopts synchronous state machine to confirm the position of master sync signal, has reduced the false alarm rate of master sync signal.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is preferred embodiment of the present invention; be not for limiting protection scope of the present invention; within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (23)

1. frame synchronization and the symbol timing synchronization method in the wireless communication system is characterized in that the method comprises:

A, setting comprise the state machine of initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode;

B, according to the current state of state machine, determine position and the length of master sync signal detection window; Wherein, gapped between the master sync signal detection window of when the state of state machine is the synchronizing signal tracking mode, determining;

C, according to determined master sync signal detection window, the sampled signal that being used for of receiving calculated the correlation in the described master sync signal detection window slide relevant and Check processing obtain current main sync bit;

D, state machine are determined the current state of state machine, and are returned execution in step B according to described current main sync bit and sync bit detection case before; Wherein, if state machine is initial condition, then enter the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold.

2. method according to claim 1 is characterized in that, described step C comprises:

C1, receive current sampled signal, and record the position of described current sampled signal;

C2, judge that whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, if so, execution in step C3 then; Otherwise, return execution in step C1;

C3, described current sampled signal is carried out low-pass filtering, obtain signal after the filtering;

C4, signal after the described filtering is carried out down-sampled, obtain down-sampled signal;

C5, calculate the correlation of described down-sampled signal and local master sync signal, and the mould value of described correlation is put into described master sync signal detection window;

C6, judge whether described master sync signal detection window is full, if so, execution in step C7 then; Otherwise, wait for that the mould value of new correlation is put into described master sync signal detection window;

C7, with the position of the corresponding down-sampled signal of maximum norm value in the described master sync signal detection window as current main sync bit.

3. method according to claim 2 is characterized in that, further comprises after the described step C3:

C8, described filtered signal is carried out buffer memory, obtain buffered signal;

Further comprise between described step C7 and the step D:

C9, with before the described current main sync bit and calculate afterwards R _DsOne 1 required buffered signal of correlation reach for the buffered signal of calculating the corresponding correlation of current main sync bit and extract; Wherein, R _DsBe reduce sampling frequency;

C10, calculate the correlation of each buffered signal and local master sync signal, obtain the mould value of the correlation of corresponding each buffered signal;

C11, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, the position of the sampled signal that described maximum norm value is corresponding is as current main sync bit.

4. each described method in 3 according to claim 1 is characterized in that, and is described when continuous N does not trace into synchronizing signal by expection 2 times, enters initial condition or the synchronizing signal acknowledgement state comprises:

When continuous N does not trace into synchronizing signal by expection 2 times, judge whether the detection quality of the master sync signal that current main sync bit is corresponding satisfies the setting requirement, in this way, then enter the synchronizing signal acknowledgement state; Otherwise, enter initial condition;

Perhaps, according to setting in advance, when continuous N does not trace into synchronizing signal by expection 2 times, enter initial condition;

Perhaps, according to setting in advance, when continuous N does not trace into synchronizing signal by expection 2 times, enter the synchronizing signal acknowledgement state.

5. each described method in 3 according to claim 1 is characterized in that described step B comprises:

When the current state of state machine is initial condition or synchronizing signal acknowledgement state, the master sync signal detection window of the first length is set, and gapless between the described master sync signal detection window; When the current state of state machine is the synchronizing signal tracking mode, the master sync signal detection window of the second length is set, and gapped between the described master sync signal detection window; Described the first length is greater than described the second length.

6. method according to claim 5 is characterized in that, described the first length is more than or equal to the master sync signal transmission cycle.

7. method according to claim 6 is characterized in that, described the first length is: the length at the first protection interval+master sync signal transmission cycle.

8. method according to claim 5 is characterized in that, described the second length is more than or equal to the length of an OFDM symbol, and less than the master sync signal transmission cycle.

9. method according to claim 8 is characterized in that, described the second length is: the length of the length at the second protection interval+OFDM symbol.

10. method according to claim 5, it is characterized in that described step B comprises: satisfy the position that described master sync signal detection window is set: make the desired location of master sync signal to be detected be positioned at the setting regions at the rear portion of described master sync signal detection window.

11. method according to claim 10 is characterized in that, the original position of the master sync signal detection window of described the first length is positioned at: the position of the length at current main sync bit+first protection interval.

12. method according to claim 10 is characterized in that, the original position of the master sync signal detection window of described the second length is positioned at:

13. method according to claim 1, it is characterized in that, further comprise among the step B: when the current state of state machine is the synchronizing signal tracking mode, determine position and the length of the auxiliary synchronous signals detection window of at least a type, and gapped between the auxiliary synchronous signals detection window of same type;

Further comprise among the step C: according to determined auxiliary synchronous signals detection window, to the sampled signal that is positioned at described auxiliary synchronous signals detection window that receives slide relevant and Check processing, obtain current auxiliary sync bit;

When state machine is the synchronizing signal tracking mode among the step D, describedly judge whether that tracing into synchronizing signal by expection comprises: judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Describedly judge whether that continuous N does not trace into synchronizing signal by expection 2 times and comprises: judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

14. method according to claim 2, it is characterized in that, further comprise among the described step B: when the current state of state machine is the synchronizing signal tracking mode, determine position and the length of the auxiliary synchronous signals detection window of at least a type, and gapped between the auxiliary synchronous signals detection window of same type;

Further comprise among the step C:

C2a, to the auxiliary synchronous signals detection window of each type, judge whether the position of described current sampled signal is positioned at described auxiliary synchronous signals detection window, if so, execution in step C3a then; Otherwise, return execution in step C1;

C3a, described current sampled signal is carried out low-pass filtering, obtain signal after the filtering;

C4a, signal after the described filtering is carried out down-sampled, obtain down-sampled signal;

C5a, calculate the correlation of described down-sampled signal and local auxiliary synchronous signals, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

C6a, judge whether described auxiliary synchronous signals detection window is full, if so, execution in step C7a then; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window;

C7a, with the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window as current auxiliary sync bit output;

When state machine is the synchronizing signal tracking mode among the step D, describedly judge whether that tracing into synchronizing signal by expection comprises: judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Describedly judge whether that continuous N does not trace into synchronizing signal by expection 2 times and comprises: judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

15. method according to claim 3, it is characterized in that, further comprise among the described step B: when the current state of state machine is the synchronizing signal tracking mode, determine position and the length of the auxiliary synchronous signals detection window of at least a type, and gapped between the auxiliary synchronous signals detection window of same type;

Further comprise among the step C:

C2a, to the auxiliary synchronous signals detection window of each type, judge that whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, execution in step C3a then; Otherwise, return execution in step C1;

C3a, described current sampled signal is carried out low-pass filtering, obtain signal after the filtering;

C8a, described filtered signal is carried out buffer memory, obtain buffered signal;

C4a, signal after the described filtering is carried out down-sampled, obtain down-sampled signal;

C5a, calculate the correlation of described down-sampled signal and local auxiliary synchronous signals, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

C6a, judge whether described auxiliary synchronous signals detection window is full, if so, execution in step C7a then; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window;

C7a, with the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window as current auxiliary sync bit output;

C9a, with before the described current auxiliary sync bit and calculate afterwards R _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current auxiliary sync bit and extracts; Wherein, R _DsBe reduce sampling frequency;

C10a, calculate the correlation of each buffered signal and local auxiliary synchronous signals, obtain the mould value of the correlation of corresponding each buffered signal;

C11a, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, the position of the sampled signal that described maximum norm value is corresponding is as current auxiliary sync bit;

When state machine is the synchronizing signal tracking mode among the step D, describedly judge whether that tracing into synchronizing signal by expection comprises: judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Describedly judge whether that continuous N does not trace into synchronizing signal by expection 2 times and comprises: judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

16. frame synchronization and sign synchronization device in the wireless communication system is characterized in that this device comprises:

State machine, this state machine comprises initial condition, synchronizing signal acknowledgement state and synchronizing signal tracking mode, be used for the current state according to state machine, determine position and the length of master sync signal detection window, and generate main synchronous detection window, position and the length information of described master sync signal detection window are notified to window detection module group;

Wherein, gapped between the master sync signal detection window that state machine is determined when the state of state machine is the synchronizing signal tracking mode; According to the current main sync bit that receives and sync bit detection case before, determine the current state of state machine, wherein, if state machine is initial condition, then enter the synchronizing signal acknowledgement state; If state machine is the synchronizing signal acknowledgement state, judge whether that then continuous N detects synchronizing signal by expection 1 time, in this way, then enters the synchronizing signal tracking mode; Otherwise, keep the synchronizing signal acknowledgement state; If state machine is the synchronizing signal tracking mode, then judge whether to trace into synchronizing signal by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into synchronizing signal by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time; Wherein, M1 is the first setting threshold, and M2 is the second setting threshold;

Signal receiving module is used for receiving current sampled signal, and records the position of described current sampled signal;

Window detection module group, be used for according to determined master sync signal detection window, the sampled signal that being used for of receiving calculated the correlation in the described master sync signal detection window slide relevant and Check processing, obtain current main sync bit, and described main sync bit is offered described state machine.

17. device according to claim 16 is characterized in that, described window detection module group comprises:

Described window position comparison module, be used for position and length according to the master sync signal detection window of state machine indication, judge whether described current sampled signal is used for calculating the correlation in the described master sync signal detection window, if so, then described current sampled signal is exported to low pass filter blocks;

Described low pass filter blocks is used for described current sampled signal is carried out low-pass filtering, obtains signal after the filtering;

Down-sampled module, down-sampled for signal after the described filtering is carried out, obtain down-sampled signal;

The first correlator is used for calculating the correlation of described down-sampled signal and the master sync signal of local master sync signal generator generation, and the mould value of described correlation is put into described master sync signal detection window;

Described master sync signal detection window is used for judging whether the master sync signal detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the master sync signal detection window is exported as current main sync bit; Otherwise, wait for that the mould value of new correlation is put into described master sync signal detection window.

18. device according to claim 17 is characterized in that, this window detection module group further comprises: signal cache module, the second correlator and the first smart synchronously detection window; Wherein,

Described signal cache module is used for the filtered signal of described low pass filter blocks is carried out buffer memory;

Described the second correlator is used for the current main sync bit of described master sync signal detection window output is calculated R before and afterwards _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current main sync bit and extracts; Calculate the correlation of each buffered signal and local master sync signal, the mould value of the correlation of corresponding each buffered signal is put into the described first smart synchronously detection window; Wherein, R _DsBe reduce sampling frequency;

The described first smart synchronously detection window is used for when the first smart synchronously detection window has expired, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, state machine is exported to as current main sync bit in the position of the sampled signal that described maximum norm value is corresponding.

19., it is characterized in that described down-sampled module, the first correlator, master sync signal detection window, signal cache module, the second correlator, the first smart synchronously detection window and state machine consist of a master sync signal test set according to right 18 described devices;

Comprise a master sync signal test set in the described device, be used for successively three kinds of master sync signals being detected, when successfully detecting any master sync signal, export this master sync signal; Perhaps,

Comprise three master sync signal test set in the described device, be used for respectively three kinds of master sync signals being detected; This moment, this device further comprised a genlocing module, was used for locking and exported at first the master sync signal test set of master sync signal until restart next simultaneous operation.

20. device according to claim 16, it is characterized in that, when described state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to window detection module group; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time;

Described window detection module group is further used for according to determined auxiliary synchronous signals detection window, the sampled signal that being used for of receiving calculated the correlation in the described auxiliary synchronous signals detection window slide relevant and Check processing, obtain current auxiliary sync bit, and described auxiliary sync bit is offered described state machine.

21. device according to claim 17, it is characterized in that, when described state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to the window position comparison module; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time

Described window position comparison module is further used for judging whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, then described current sampled signal is exported to low pass filter blocks;

This device further comprises: third phase closes device, be used for being positioned at the down-sampled signal of auxiliary synchronous signals detection window, calculate the correlation of the auxiliary synchronous signals of described down-sampled signal and local auxiliary synchronous signals generator generation, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

Described auxiliary synchronous signals detection window is used for judging whether described auxiliary synchronous signals detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window is exported as current auxiliary sync bit; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window.

22. device according to claim 18 is characterized in that, this device further comprises: third phase closes device, the 4th correlator and the second smart synchronously detection window;

When described state machine is the synchronizing signal tracking mode in current state, further determine position and the length of auxiliary synchronous signals detection window, and generate corresponding auxiliary synchronous detection window, position and the length information of described auxiliary synchronous signals detection window are notified to the window position comparison module; Wherein, gapped between the described auxiliary synchronous signals detection window; When described state machine is the synchronizing signal tracking mode in current state, judge whether to trace in master sync signal or the auxiliary synchronous signals any by expection, in this way, then keep the synchronizing signal tracking mode, and export current main sync bit; Otherwise, judge whether that continuous N does not trace into master sync signal and auxiliary synchronous signals by expection 2 times, in this way, then enter initial condition or synchronizing signal acknowledgement state, otherwise, export current main sync bit according to the synchronizing signal that traces into by expection of last time.

Described window position comparison module is further used for judging whether described current sampled signal is used for calculating the correlation in the described auxiliary synchronous signals detection window, if so, then described current sampled signal is exported to low pass filter blocks;

Described third phase closes device and is used for being positioned at the down-sampled signal of auxiliary synchronous signals detection window, calculate the correlation of the auxiliary synchronous signals of described down-sampled signal and local auxiliary synchronous signals generator generation, and the mould value of described correlation is put into described auxiliary synchronous signals detection window;

Described auxiliary synchronous signals detection window is used for judging whether described auxiliary synchronous signals detection window is full, if so, then the position of the corresponding down-sampled signal of maximum norm value in the described auxiliary synchronous signals detection window is exported as current auxiliary sync bit; Otherwise, wait for that the mould value of new correlation is put into described auxiliary synchronous signals detection window;

Described the 4th correlator is used for the current auxiliary sync bit of described auxiliary synchronous signals detection window output is calculated R before and afterwards _Ds-1 required buffered signal of correlation reaches for the buffered signal of calculating the corresponding correlation of current auxiliary sync bit and extracts; Calculate the correlation of each buffered signal and local auxiliary synchronous signals, the mould value of the correlation of corresponding each buffered signal is put into the described second smart synchronously detection window; Wherein, R _DsBe reduce sampling frequency;

The described second smart synchronously detection window is used for when the second smart synchronously detection window has expired, choose the maximum norm value from the mould value of the correlation of corresponding each buffered signal, state machine is exported to as current auxiliary sync bit in the position of the sampled signal that described maximum norm value is corresponding.

23. according to right 22 described devices, it is characterized in that described down-sampled module, the first correlator, master sync signal detection window, third phase close device, auxiliary synchronous signals detection window, signal cache module, the second correlator, the first smart synchronously detection window, the 4th correlator, the second smart synchronously detection window and state machine and consist of a synchronization signal detection group;

Comprise a synchronization signal detection group in the described device, be used for successively three kinds of master sync signals being detected, when successfully detecting any master sync signal, export this master sync signal; Perhaps,

Comprise three synchronization signal detection groups in the described device, be used for respectively three kinds of master sync signals being detected; This moment, this device further comprised a genlocing module, was used for locking and exported at first the synchronization signal detection group of master sync signal until restart next simultaneous operation.

Images