CN103378089A - High-voltage electrostatic protection structure - Google Patents
High-voltage electrostatic protection structure Download PDFInfo
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- CN103378089A CN103378089A CN201210133339XA CN201210133339A CN103378089A CN 103378089 A CN103378089 A CN 103378089A CN 201210133339X A CN201210133339X A CN 201210133339XA CN 201210133339 A CN201210133339 A CN 201210133339A CN 103378089 A CN103378089 A CN 103378089A
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Abstract
The invention discloses high-voltage electrostatic protection structure which comprises a first low-voltage PMOS and a high-voltage silicon control rectifier. The first low-voltage PMOS is formed in an N type buried layer on a P type epitaxy part of a silicon substrate, the high-voltage silicon control rectifier is formed on the P type epitaxy part of the silicon substrate and is composed of a N+ diffusion area and a P+ diffusion area which are formed in a first high-voltage P trap and a N+ diffusion area and a P+ diffusion area which are formed in a first high-voltage N trap. A second high-voltage P trap is formed between the first low-voltage PMOS and the high-voltage silicon control rectifier, and a P+ diffusion area in the second high-voltage P trap is grounded. A gate source of the first low-voltage PMOS is in a short circuit state and connected with a N+ diffusion area of a low-voltage N trap of the first low-voltage PMOS and a static electricity entering end, a drain electrode of the first low-voltage PMOS is connected with the static electricity entering end through a first resistor, the N+ diffusion area and the P+ diffusion area in the first high-voltage P trap are in a short circuit state and connected with the ground, and the N+ diffusion area and the P+ diffusion area in the first high-voltage N trap are in a short circuit state and connected with the drain electrode of the first low-voltage PMOS. The high-voltage electrostatic protection structure can be applied to a BCD technology and can effectively reduce occurrence of the triggered latch-up effect.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of high-pressure electrostatic protection structure.
Background technology
As electrostatic protection device, thyristor (SCR) has stronger electrostatic leakage ability than Metal-oxide-semicondutor field effect transistor (MOSFET), and the electrostatic leakage ability of general SCR structure is 5～7 times of MOSFET.As shown in Figure 1, a kind of cross-sectional view of high trigger voltage SCR structure.In Fig. 1, the collector electrode of the parasitic PNP pipe that P+/high pressure N trap/high pressure P trap forms also is simultaneously the base stage of the parasitic NPN pipe of N+/high pressure P trap/high pressure N trap formation; Equally, the collector electrode of the parasitic NPN pipe of N+/high pressure P trap/high pressure N trap formation also is the base stage of the parasitic PNP pipe of P+/high pressure N trap/high pressure P trap formation.The equivalent circuit diagram that parasitic NPN among Fig. 1 and PNP pipe form as shown in Figure 2.Can find out that from Fig. 1 and Fig. 2 the trigger voltage of the SCR structure that the parasitic NPN pipe that parasitic PNP manages and N+/high pressure P trap/high pressure N trap forms that is formed by P+/high pressure N trap/high pressure P trap forms jointly is the reverse breakdown voltage of high pressure N trap/high pressure P trap.Usually the reverse breakdown voltage of high pressure N trap/high pressure P trap knot is higher, and therefore, the application of this structure is limited by very large.In addition, because the rear parasitic NPN of SCR unlatching itself and PNP realize the positive feedback that electric current amplifies mutually, cause its conducting resistance very low, multiplication factor is very large, and the voltage of keeping that occurs after rapid time will be very low, generally between 2～5V.And therefore the normal working voltage of high-tension circuit uses SCR to do electrostatic discharge protective circuit far away on this, also easily causes latch-up, and is difficult for recovering.
Summary of the invention
The technical problem to be solved in the present invention provides and a kind ofly can be applied to BCD technique, can effectively reduce and trigger the high-pressure electrostatic protection structure that latch-up occurs.
For solving the problems of the technologies described above, high-pressure electrostatic protection structure of the present invention comprises:
The first low pressure PMOS is formed in the n type buried layer on the silicon substrate P type extension;
One high pressure thyristor is formed on the P type extension of silicon substrate, and by the N+ diffusion region and the P+ diffusion region that are formed in the first high pressure P trap, and the N+ diffusion region and the P+ diffusion region that are formed in the first high pressure N trap form;
Be formed with the second high pressure P trap between the first low pressure PMOS and the high pressure thyristor, the P+ diffusion region ground connection in the second high pressure P trap; The source grid short circuit of the first low pressure PMOS also links to each other with the static upstream end with N+ diffusion region in its low pressure N trap; The drain electrode of the first low pressure PMOS links to each other with the static upstream end by the first resistance;
N+ diffusion region in the first high pressure P trap and P+ diffusion region short circuit also are connected to the ground, and the N+ diffusion region in the first high pressure N trap links to each other with P+ diffusion region short circuit and with the drain electrode of the first low pressure PMOS.
Wherein, also comprise: third high is pressed the P trap, is formed at the second high pressure P trap one side, and third high presses the P+ diffusion region in the P trap to connect ground;
The second low pressure PMOS is formed in the n type buried layer on the silicon substrate P type extension, between second, third P trap, its grid, source electrode link to each other with the drain electrode of the first low pressure PMOS, its drain electrode links to each other with the P+ diffusion region with N+ diffusion region in the first high pressure N trap, and its drain electrode is passed through the second resistance and linked to each other with the static upstream end.
Wherein, the first low pressure PMOS can adopt the first low pressure PNP triode to replace, and the first low pressure PNP triode is formed in the n type buried layer on the silicon substrate P type extension; It connects the N+ diffusion region of end as base stage and links to each other with the P+ diffusion region short circuit that connects end as emitter and with the static upstream end, it connects the P+ diffusion region of end and links to each other with the P+ diffusion region with N+ in the first high pressure N trap as collector electrode, its collector electrode links to each other with the static upstream end by the 3rd resistance.
Wherein, first, second, third resistance is 10 ohm～10000 ohm.
The present invention uses by low pressure PMOS and high pressure SCR combination of devices, reaches solution high-pressure electrostatic protection structure and suddenly returns the problem that brownout causes easily triggering latch-up;
Low pressure PMOS is positioned in the n type buried layer, main consideration is that the low pressure N trap in the low pressure PMOS has high pressure, but the puncture voltage of itself and P type extension is on the low side, and n type buried layer and low pressure N trap are homotype, and n type buried layer surrounds low pressure N trap, current potential is identical during application, but because n type buried layer concentration is lighter, and inject very dark, with the puncture voltage of P type extension than low pressure N well depth, therefore the puncture voltage of N-type deep trap and P type extension is high, is difficult for puncturing.
Because the drain electrode of low pressure PMOS links to each other by resistance with the static end, therefore come interim at static, can directly enter N+ and P+ diffusion region in the high pressure N trap of high pressure SCR by resistance, high pressure SCR is opened in puncture by high pressure N trap and P trap, but because resistance current limliting, it is very slow to cause electric current to increase, and the potential difference fast rise of resistance both sides, reach rapidly the puncture voltage of low pressure PMOS, open and triggered parasitic PNP, this moment, electric current was no longer via the SCR of resistance to unlatching, but through low pressure PMOS, this moment, the minimum voltage of keeping for rapid time can be by low pressure PMOS and the decision of high pressure SCR device sum, low pressure PMOS pipe than high pressure SCR device height many, generally more than 10V, and minimum rapid time of high pressure SCR device itself kept voltage about 3V, therefore whole rapid telegram in reply is pressed in more than the 10V, and like this with respect to single high pressure SCR device, the rapid pressure of wiring back has improved many.
According to product practice situation, when rapid telegram in reply is pressed in 10V when above, the possibility and the risk that trigger latch-up are much lower with respect to the risk of using single high pressure SCR device.Therefore, high-pressure electrostatic protection structure of the present invention can effectively reduce the generation that triggers latch-up.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is a kind of existing high pressure SCR structural representation.
Fig. 2 is the equivalent circuit diagram of SCR structure among Fig. 1.
Fig. 3 is structural representation of the present invention.
Fig. 4 is the equivalent circuit diagram of structure shown in Figure 3.
Fig. 5 is the structural representation of first embodiment of the invention.
Fig. 6 is the equivalent circuit diagram of structure shown in Figure 5.
Fig. 7 is the structural representation of second embodiment of the invention.
Fig. 8 is the equivalent circuit diagram of structure shown in Figure 7.
Description of reference numerals
1 is the first high pressure P trap
2 is first high pressure N traps
3 is second high pressure P traps
The 4th, n type buried layer
5 is low pressure N traps of a PMOS
The 6th, P+ diffusion region
The 7th, N+ diffusion region
8 is the first resistance
9 is the second resistance
10 is the 3rd resistance
The 11st, third high is pressed the P trap
12 is grids of a PMOS
13 is source electrodes of a PMOS
14 is drain electrodes of a PMOS
15 is low pressure N traps of the 2nd PMOS
16 is grids of the 2nd PMOS
17 is source electrodes of the 2nd PMOS
18 is drain electrodes of the 2nd PMOS
Vbp, Vbn are voltage
Rpw, Rnw, Rnw1 are resistance
Embodiment
As shown in Figure 5, first embodiment of the invention comprises: first, second low pressure PMOS is formed in the n type buried layer 4 on the silicon substrate P type extension;
One high pressure thyristor (SCR) is formed on the P type extension of silicon substrate, and by the N+ diffusion region 7 and the P+ diffusion region 6 that are formed in the first high pressure P trap 1, and the N+ diffusion region 7 and the P+ diffusion region 6 that are formed in the first high pressure N trap 2 form;
N+ diffusion region 7 in the first high pressure P trap 1 and P+ diffusion region 6 short circuits also are connected to the ground, and the N+ diffusion region 7 in the first high pressure N trap links to each other with P+ diffusion region 6 short circuits and with the drain electrode of the first low pressure PMOS;
The second high pressure P trap 3, the second low pressure PMOS and third high press P trap 11 orders to be formed between the first low pressure PMOS and the high pressure thyristor, and the second high pressure P trap 3, third high are pressed P+ diffusion region 6 ground connection in the P trap 11; The second high pressure P trap 3 and high pressure high pressure thyristor, the second low pressure PMOS are adjacent, and third high presses P trap 11 adjacent with first, second low pressure PMOS;
The source electrode 12 of the first low pressure PMOS (the P+ diffusion region 7 in the low pressure N trap 5 is as source electrode) and grid 13 short circuits also link to each other with the static upstream end with N+ diffusion region 7 in its low pressure N trap 5;
The second low pressure PMOS is formed in the n type buried layer on the silicon substrate P type extension equally, its grid 16, source electrode 17 link to each other with the drain electrode 14 of the first low pressure PMOS pipe, its drain electrode 18 links to each other with P+ diffusion region 6 with N+ diffusion region 7 in the first high pressure N trap 2, and its drain electrode is passed through the second resistance 9 and linked to each other with the static upstream end; The second resistance 9 resistances are 10 ohm～10000 ohm.
The equivalent circuit diagram of present embodiment, as shown in Figure 6.
As shown in Figure 7, the second embodiment of the present invention comprises:
One high pressure thyristor (SCR) is formed on the P type extension of silicon substrate, and by the N+ diffusion region 7 and the P+ diffusion region 6 that are formed in the first high pressure P trap 1, and the N+ diffusion region 7 and the P+ diffusion region 6 that are formed in the first high pressure N trap 2 form;
The first low pressure PNP triode is formed in the n type buried layer 4 on the silicon substrate P type extension; It connects the N+ diffusion region 7 of end as base stage and links to each other with P+ diffusion region 6 short circuits that connect end as emitter and with the static upstream end, it connects the P+ diffusion region 6 of end and links to each other with P+ diffusion region 6 with N+ diffusion region 7 in the first high pressure N trap as collector electrode, its collector electrode links to each other with the static upstream end by the 3rd resistance 10, and the 3rd resistance 10 resistances are 10 ohm～10000 ohm.The equivalent circuit diagram of present embodiment, as shown in Figure 8.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. a high-pressure electrostatic protection structure is characterized in that comprise: the first low pressure PMOS is formed in the n type buried layer on the silicon substrate P type extension;
One high pressure thyristor is formed on the P type extension of silicon substrate, and by the N+ diffusion region and the P+ diffusion region that are formed in the first high pressure P trap, and the N+ diffusion region and the P+ diffusion region that are formed in the first high pressure N trap form;
Be formed with the second high pressure P trap between the first low pressure PMOS and the high pressure thyristor, the P+ diffusion region ground connection in the second high pressure P trap; The source grid short circuit of the first low pressure PMOS also links to each other with the static upstream end with N+ diffusion region in its low pressure N trap; The drain electrode of the first low pressure PMOS links to each other with the static upstream end by the first resistance;
N+ diffusion region in the first high pressure P trap and P+ diffusion region short circuit also are connected to the ground, and the N+ diffusion region in the first high pressure N trap links to each other with P+ diffusion region short circuit and with the drain electrode of the first low pressure PMOS.
2. high-pressure electrostatic as claimed in claim 1 is protected structure, and it is characterized in that: the first resistance is 10 ohm～10000 ohm.
3. high-pressure electrostatic protection structure as claimed in claim 1 is characterized in that also comprise: third high is pressed the P trap, is formed at the second high pressure P trap one side, and third high presses the P+ diffusion region in the P trap to connect ground;
The second low pressure PMOS is formed in the n type buried layer on the silicon substrate P type extension, between second, third P trap, its grid, source electrode link to each other with the drain electrode of the first low pressure PMOS pipe, its drain electrode links to each other with the P+ diffusion region with N+ diffusion region in the first high pressure N trap, and its drain electrode is passed through the second resistance and linked to each other with the static upstream end.
4. high-pressure electrostatic as claimed in claim 3 is protected structure, and it is characterized in that: the second resistance is 10 ohm～10000 ohm.
5. high-pressure electrostatic as claimed in claim 1 protection structure is characterized in that: the first low pressure PNP triode is formed in the n type buried layer on the silicon substrate P type extension; It connects the N+ diffusion region of end as base stage and links to each other with the P+ diffusion region short circuit that connects end as emitter and with the static upstream end, it connects the P+ diffusion region of end and links to each other with the P+ diffusion region with N+ diffusion region in the described high pressure thyristor high pressure N trap as collector electrode, its collector electrode links to each other with the static upstream end by the 3rd resistance.
6. high-pressure electrostatic as claimed in claim 5 is protected structure, and it is characterized in that: the 3rd resistance is 10 ohm～10000 ohm.
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| CN201210133339XA CN103378089A (en) | 2012-04-28 | 2012-04-28 | High-voltage electrostatic protection structure |
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| CN201210133339XA CN103378089A (en) | 2012-04-28 | 2012-04-28 | High-voltage electrostatic protection structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104099A (en) * | 2016-02-23 | 2017-08-29 | 精工爱普生株式会社 | Electrostatic discharge protective circuit, conductor integrated circuit device and electronic equipment |
| CN107564905A (en) * | 2017-07-28 | 2018-01-09 | 中航（重庆）微电子有限公司 | A kind of preparation method, structure and its application circuit of high pressure ESD device structure |
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| US20030214773A1 (en) * | 2002-04-19 | 2003-11-20 | Nobutaka Kitagawa | Protection circuit section for semiconductor circuit system |
| CN101217234A (en) * | 2007-01-04 | 2008-07-09 | 盛群半导体股份有限公司 | An electrostatic protection structure of high voltage drive integrated circuit |
| CN102064173A (en) * | 2009-11-17 | 2011-05-18 | 无锡华润矽科微电子有限公司 | Electrostatic protective device for silicon controlled rectifier |
| US20120091503A1 (en) * | 2010-10-19 | 2012-04-19 | Qing Su | High-voltage esd protection device |
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2012
- 2012-04-28 CN CN201210133339XA patent/CN103378089A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030214773A1 (en) * | 2002-04-19 | 2003-11-20 | Nobutaka Kitagawa | Protection circuit section for semiconductor circuit system |
| CN101217234A (en) * | 2007-01-04 | 2008-07-09 | 盛群半导体股份有限公司 | An electrostatic protection structure of high voltage drive integrated circuit |
| CN102064173A (en) * | 2009-11-17 | 2011-05-18 | 无锡华润矽科微电子有限公司 | Electrostatic protective device for silicon controlled rectifier |
| US20120091503A1 (en) * | 2010-10-19 | 2012-04-19 | Qing Su | High-voltage esd protection device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104099A (en) * | 2016-02-23 | 2017-08-29 | 精工爱普生株式会社 | Electrostatic discharge protective circuit, conductor integrated circuit device and electronic equipment |
| CN107104099B (en) * | 2016-02-23 | 2023-08-25 | 精工爱普生株式会社 | Electrostatic protection circuit, semiconductor integrated circuit device, and electronic apparatus |
| CN107564905A (en) * | 2017-07-28 | 2018-01-09 | 中航（重庆）微电子有限公司 | A kind of preparation method, structure and its application circuit of high pressure ESD device structure |
| CN107564905B (en) * | 2017-07-28 | 2020-04-03 | 华润微电子（重庆）有限公司 | Preparation method and structure of high-voltage ESD device structure and application circuit thereof |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140110 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140110 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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