CN103378067B - Wafer assembly with carrying wafer - Google Patents
Wafer assembly with carrying wafer Download PDFInfo
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- CN103378067B CN103378067B CN201210350992.1A CN201210350992A CN103378067B CN 103378067 B CN103378067 B CN 103378067B CN 201210350992 A CN201210350992 A CN 201210350992A CN 103378067 B CN103378067 B CN 103378067B
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses a kind of wafer assembly with carrying wafer, including technique wafer and carrying wafer.Integrated circuit is formed on technique wafer.Carrying wafer is bound to technique wafer.Carrying wafer has at least one alignment mark.
Description
The cross reference of related application
This application claims the U.S. Provisional Patent Application of the Serial No. 61/638.209 submitted on April 25th, 2012
Priority, its content are hereby expressly incorporated by reference.
Technical field
Present invention relates in general to semiconductor subassembly, more particularly, to the wafer assembly with carrying wafer.
Background technology
With the increase of wafer size, sagging as caused by wafer weight (sagging) and as caused by film growth technique
Silicon wafer warpage is the presence of the problem of challenge.When the part as device fabrication grows various films on the wafer surface,
Generation silicon wafer warpage.In an example, 450mm wafers need the thickness with 1,800 μm (1.8mm) to keep and have
The identical sagging level of wafer of the 300mm wafers of 775 μ m thicks.In another example, have what is grown or deposit on it
The 450mm wafers of 100nm nitride films may need with least 1,180 μm thickness by silicon wafer warpage be limited to substantially with
With the identical level of the 300mm wafers of 775 μ m thicks.
The content of the invention
According to an aspect of the invention, there is provided a kind of wafer assembly, including：Technique wafer, the shape on technique wafer
Into integrated circuit；And carrying wafer, technique wafer is bound to, carrying wafer has at least one alignment mark.
Preferably, which further comprises：The combination adhesive phase of combined process wafer and carrying wafer.
Preferably, which further comprises：The epitaxial layer of combined process wafer and carrying wafer.
Preferably, the thickness of epitaxial layer is in the range of 100 angstroms to 1000 angstroms.
Preferably, technique wafer does not have alignment mark.
Preferably, carrying wafer has multiple alignment marks, and multiple alignment marks are equidistant along the circumference of carrying wafer
Distribution.
Preferably, multiple alignment marks are of different sizes.
Preferably, the first thickness of technique wafer is less than the second thickness of carrying wafer.
According to another aspect of the present invention, there is provided a kind of method, including：With reference to the technique wafer with integrated circuit and
Carrying wafer with least one alignment mark, to form wafer assembly；And at least one alignment using carrying wafer
Mark alignment wafer assembly.
Preferably, combination is performed by using the combination adhesive phase between technique wafer and carrying wafer.
Preferably, with reference to including：In the lower section of technique wafer or the top grown epitaxial layer of carrying wafer；Using positioned at work
Epitaxial layer between skill wafer and carrying wafer, technique wafer and carrying wafer are put together；And annealing.
Preferably, the thickness of epitaxial layer is in the range of 100 angstroms to 1000 angstroms.
Preferably, in the range of 300 DEG C to 500 DEG C at a temperature of perform annealing.
Preferably, this method further comprises：Separating technology wafer and carrying wafer.
Preferably, carrying wafer has multiple alignment marks, and multiple alignment marks are equidistant along the circumference of carrying wafer
Distribution.
Preferably, multiple alignment marks are of different sizes.
Preferably, the first thickness of technique wafer is less than the second thickness of carrying wafer.
According to another aspect of the invention, there is provided a kind of wafer assembly, including：Technique wafer, have first thickness and
It is not aligned with marking, wherein, integrated circuit is formed on technique wafer；And carrying wafer, there is second thickness and be bound to
Technique wafer, wherein, carrying wafer has multiple alignment marks, circumference equidistant point of multiple alignment marks along carrying wafer
Cloth, and first thickness is less than second thickness.
Preferably, which further comprises：The combination adhesive phase of combined process wafer and carrying wafer.
Preferably, which further comprises：The epitaxial layer of combined process wafer and carrying wafer, wherein, extension
Layer has the 3rd thickness in the range of 100 angstroms to 1000 angstroms.
Brief description of the drawings
Presently in connection with attached drawing as a reference to carrying out following description, wherein：
Figure 1A is the schematic diagram of the exemplary wafer component with carrying wafer in accordance with some embodiments；
Figure 1B is the top view of the technique wafer of the wafer assembly in Figure 1A in accordance with some embodiments；
Fig. 1 C are the top views of the carrying wafer of the wafer assembly in Figure 1A in accordance with some embodiments；And
Fig. 2 is the exemplary of the integrated circuit that the exemplary wafer component in accordance with some embodiments using in Fig. 1 manufactures
The flow chart of method.
Embodiment
The manufacture and use of various embodiments is discussed further below.It should be appreciated, however, that can be with present disclose provides many
What is embodied in various specific environments can application invention concept.The specific embodiment discussed simply manufactures and using specific side
Formula is illustrative without limiting the scope of the present disclosure.
In addition, the disclosure can in various examples repeat reference numerals and/or letter.Such repetition is in order to simple
With clear purpose, and itself be not intended that discussed various embodiments and/or configuration between relation.In addition, the disclosure
In a component be formed on another component, connection and/or can be formed coupled to another component including component
The embodiment directly contacted, and can also include being formed the additional component being inserted between these components so that component is not direct
The embodiment of contact.In addition, spatially relative term, for example, " lower section ", " top ", " level ", " vertical ", " on ", " it
Under ", " on ", " under ", " top ", " bottom " etc. and its derivative words are (for example, " flatly ", " down ", " upward " etc. are at this
It is used to represent the relation between a component and another component in invention.Spatially relative term is used to cover the device for including component
Be differently directed.
Figure 1A is the exemplary wafer component 100 in accordance with some embodiments with technique wafer 102 and carrying wafer 104
Schematic diagram.Wafer assembly 100 includes the technique wafer 102 combined and carrying wafer 104.In certain embodiments,
(for example, with reference to adhesive phase or epitaxial layer) the combined process wafer 102 of binder course 103 and carrying wafer 104.Carry wafer 104
With at least one alignment mark 106 so that alignment mark detection device 108 (it is not a part for wafer assembly 100) can be with
Alignment mark 106 is detected to be used for wafer alignment.Technique wafer 102 and carrying wafer 104 may include any suitable material, example
Such as silicon.
In certain embodiments, for 450mm wafers, the thickness of technique wafer 102 is less than 95 μm.In some implementations
In example, for 450mm wafers, the thickness of carrying wafer 104 is more than 2000 μm.Compared with technique wafer 102, wafer is carried
It is sagging caused by larger wafer size and/or film depositing operation that 104 larger thickness can reduce wafer assembly 100
And warpage.
Alignment mark 106 can be formed in one or more notches on carrying 104 side wall of wafer.In an example
In, three notches as alignment mark 106 are equidistantly distributed along the circumference of carrying wafer 104, and three notches have
Different sizes is to distinguish each single notch.It is used as three notches of alignment mark 106, sets of wafers by equidistantly distributing
Part 100 rotates 120 ° and is used to be aligned to find at least one notch.In this example, it is used as alignment mark 106 with only having
A notch and need to be rotated by 360 ° and compared come the wafer assembly 100 for alignment, improve productivity.In some embodiments
In, alignment mark detection device 108 includes laser diode and photodetector to position the position of alignment mark 106.
Figure 1B is the top view of the technique wafer 102 of the wafer assembly in Figure 1A in accordance with some embodiments.In some realities
Apply in example, the thickness of technique wafer 102 is less than 925 μm.By making technique wafer 102 that there is relatively thin thickness (in some examples
In be as thin as 100 μm), wafer cost can be reduced.In addition, because carrying wafer 104 there is alignment mark 106, for
Mark 106 is need not be aligned on the technique wafer 102 of wafer assembly 100.By not forming alignment mark on technique wafer 102
106, it can be used for alignment mark 106 without retaining any region with surface by using all of technique wafer 102, can
To improve the tube core yield of technique wafer 102.
Fig. 1 C are the top views of the carrying wafer 104 of the wafer assembly in Figure 1A in accordance with some embodiments.In some realities
Apply in example, for 450mm wafers, the thickness of carrying wafer 104 is more than 2000 μm.Notch 106a, 106b, 106c is formed to make
For alignment mark 106, equidistantly distributed along the circumference of carrying wafer 104.Three notches are of different sizes to distinguish that
This.
Carrying wafer 104 with multiple notches can strengthen wafer alignment productivity.For example, by making to be used as to fiducial mark
Three notches 106a, 106b, 106c of note 106 are equidistant, and wafer assembly 100 is next to find at least one notch by 120 ° of rotation
For being aligned.In this example, with only need to be rotated by 360 ° 100 phase of wafer assembly for alignment with a notch
Than improving productivity.
In other embodiments, notch 106a, 106b, 106c has different shape (such as circular), has different numbers
Measure (for example, four notches rather than three or less than three), and multiple notches can be included a position (for example, 0 °
Locate a notch, two notches at 120 °, three notches at 240 °).In addition, in other embodiments, it can use different
Alignment mark 106 (for example, carrying wafer 104 side or bottom on round dot or recess) come replace notch 106a, 106b and
106c.In at least one embodiment, one or more notch 106a, 106b and 106c or alignment mark 106 are omitted.
In certain embodiments, carrying wafer 104 can be separated with the technique wafer 102 in Figure 1A and made again
With.For example, carrying wafer 104 separated with technique wafer 102 can be sharp again after chemical-mechanical planarization (CMP) polishes
With.
Fig. 2 is the example that the exemplary wafer component 100 in accordance with some embodiments using in Figure 1A manufactures integrated circuit
The flow chart of property method.In step 202, front-end process is performed to technique wafer 102 to form integrated circuit.In some implementations
In example, front-end process may include to form shallow trench isolation (STI), form trap, form device (for example, transistor, capacitor or electricity
Hinder device), form interconnection piece and/or any other suitable technique.It can be held by any method known in the art or technique
Row front-end process.
In step 204, technique wafer 102 and carrying wafer 104 are bonded to form wafer assembly 100.In some realities
Apply in example, technique wafer 102 and carrying wafer 104 are bonded by using the combination between technique wafer 102 and carrying wafer 104
Bond material in oxidant layer 103 and combine.Bond material may include any suitable material known in the art.Example
Such as, in the market is soldThe temporary transient bond material of HT series is designed to exist at various temperatures
Further necessary machinery is provided during processing (for example, thinned, TSV techniques etc.) to support.
In some other embodiments, technique wafer 102 and carrying wafer 104 pass through in technique wafer 102 and carrying crystalline substance
Circle 104 between grown epitaxial layer 103 (for example, Si extensions or silicon epitaxy layer) and annealing and combine.For example, silicon epitaxy layer can give birth to
Grow in the lower section of technique wafer 102.In certain embodiments, by performing the chemical vapor deposition for depositing monocrystalline silicon thin film
(CVD) technique forms silicon epitaxy layer.In certain embodiments, then annealing has technique at a temperature of 300 DEG C -500 DEG C
The wafer assembly 100 of silicon epitaxy layer 103 between wafer 102 and carrying wafer 104 is with combined process wafer 102 and carrying wafer
104。
In step 206, using the alignment mark 106 on carrying wafer 104 (for example, notch 106a, 106b in Fig. 1 C
And 106c) alignment wafer assembly 100.Can be by using alignment mark detection device 108 (including laser diode and photodetection
Device) alignment is performed, to position the position of alignment mark 106.
In a step 208, backend process is performed to wafer assembly 100.Backend process may include wafer test, wafer back part
Grinding, tube core separation and/or die testing.Backend process can be performed by any suitable technique known in the art.
In the step 212, in certain embodiments, wafer assembly 100 carries out further backend process, such as encapsulates.
In some other embodiments, in step 210 before step 212, carrying wafer 104 and technique wafer 102 disengage (or point
From).Carrying wafer 104 can be reused.In order to make carrying wafer 104 disengage (or separation), wafer assembly with technique wafer 102
100, which are fixed on both sides, is respectively provided with the appropriate disengageding mould of compliance grasping system (for example, vacuum chuck), is then evenly heated
(for example, 300 DEG C -400 DEG C) extremely disengage temperature.When reaching disengagement temperature, technique wafer 102 and carrying wafer 104 are slided and divided
From.During technique is disengaged, technique wafer 102 is supported in whole region and keeps unstressed completely.
In certain embodiments, for the wafer assembly 100 using bond material (adhesive), depending on reference to material
Material, it can be less than 200 DEG C to disengage temperature.In certain embodiments, it is clear in single wafer cleaning room after wafer separate
Technique wafer 102 is washed, remaining bond material (adhesive) is removed using appropriate solvent.
According to some embodiments, a kind of wafer assembly includes technique wafer and carrying wafer.Collection is formed on technique wafer
Into circuit.Carrying wafer is bound to technique wafer.Carrying wafer has at least one alignment mark.
According to some embodiments, a kind of method includes：With reference to the technique wafer with integrated circuit and with least one
The carrying wafer of alignment mark is to form wafer assembly.Use at least one alignment mark wafer assembly of carrying wafer.
It should be appreciated by those skilled in the art the disclosure can have the change of many embodiments.Although it is described in detail
Embodiment and its feature, it is to be understood that can carry out it is various change, replace and change without departing from the present embodiment spirit and
Scope.In addition, scope of the present application is not limited to technique, machine, manufacture and material composition described in this specification, device, side
Method and step.Those skilled in the art can will be readily understood that from the disclosed embodiments, can be according to the disclosure come sharp
With it is existing or develop later, perform the function essentially identical with corresponding embodiment described herein or realize essentially identical result
Technique, machine, manufacture and material composition, device, method and steps.
Above method is implemented to be illustrated illustrative steps, but they need not be performed with shown order.According to this
Disclosed spirit and scope, can as needed increase, replace, change order and/or removal process.Upon reading this disclosure,
The embodiment of different claims and/or different embodiment is combined in the scope of the present disclosure and for people in the art
It is apparent for member.
Claims (17)
1. a kind of wafer assembly, including：
Technique wafer, forms integrated circuit on the technique wafer, and the technique wafer does not have alignment mark；And
Wafer is carried, is bound to the technique wafer, the carrying wafer has multiple alignment marks so that alignment mark detection
Device detects the alignment mark for being directed at the wafer assembly,
The multiple alignment mark is equidistantly distributed along the circumference of the carrying wafer.
2. wafer assembly according to claim 1, further comprises：With reference to the technique wafer and the carrying wafer
With reference to adhesive phase.
3. wafer assembly according to claim 1, further comprises：With reference to the technique wafer and the carrying wafer
Epitaxial layer.
4. wafer assembly according to claim 3, wherein, the scope of the thickness of the epitaxial layer at 100 angstroms to 1000 angstroms
It is interior.
5. wafer assembly according to claim 1, wherein, the multiple alignment mark is of different sizes.
6. wafer assembly according to claim 1, wherein, the first thickness of the technique wafer is less than the carrying wafer
Second thickness.
7. a kind of method for manufacturing semiconductor subassembly, including：
With reference to the technique wafer with integrated circuit and the carrying wafer with multiple alignment marks, to form wafer assembly, institute
State technique wafer and do not have alignment mark；And
Using wafer assembly described in multiple alignment marks of the carrying wafer, wherein, examined using alignment mark detection device
The alignment mark is surveyed for being directed at the wafer assembly；
Wherein, the multiple alignment mark is equidistantly distributed along the circumference of the carrying wafer.
8. the method according to claim 7 for manufacturing semiconductor subassembly, wherein, by using positioned at the artwork
Combination adhesive phase between round and described carrying wafer performs combination.
9. the method according to claim 7 for manufacturing semiconductor subassembly, wherein, with reference to including：
In the lower section of the technique wafer or the top grown epitaxial layer of the carrying wafer；
Using the epitaxial layer between the technique wafer and the carrying wafer, by the technique wafer and described hold
Wafer is carried to put together；And
Annealing.
10. the method according to claim 9 for manufacturing semiconductor subassembly, wherein, the thickness of the epitaxial layer is 100
Angstrom in the range of 1000 angstroms.
11. the method according to claim 9 for manufacturing semiconductor subassembly, wherein, in 300 DEG C to 500 DEG C of scope
The annealing is performed at interior temperature.
12. the method according to claim 7 for manufacturing semiconductor subassembly, further comprises：Separate the artwork
Circle and the carrying wafer.
13. the method according to claim 7 for manufacturing semiconductor subassembly, wherein, the multiple alignment mark has
Different sizes.
14. the method according to claim 7 for manufacturing semiconductor subassembly, wherein, the first of the technique wafer is thick
Degree is less than the second thickness of the carrying wafer.
15. a kind of wafer assembly, including：
Technique wafer, has first thickness and is not aligned with marking, wherein, integrated circuit is formed on the technique wafer；With
And
Wafer is carried, there is second thickness and be bound to the technique wafer,
Wherein, the carrying wafer has multiple alignment marks, circumference of the multiple alignment mark along the carrying wafer
Equidistantly distribute so that alignment mark detection device detects the alignment mark for being directed at the wafer assembly, and described
First thickness is less than the second thickness.
16. wafer assembly according to claim 15, further comprises：With reference to the technique wafer and the carrying wafer
Combination adhesive phase.
17. wafer assembly according to claim 15, further comprises：With reference to the technique wafer and the carrying wafer
Epitaxial layer, wherein, the epitaxial layer have 100 angstroms to 1000 angstroms in the range of the 3rd thickness.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261638209P | 2012-04-25 | 2012-04-25 | |
| US61/638,209 | 2012-04-25 | ||
| US13/539,243 | 2012-06-29 | ||
| US13/539,243 US9111982B2 (en) | 2012-04-25 | 2012-06-29 | Wafer assembly with carrier wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103378067A CN103378067A (en) | 2013-10-30 |
| CN103378067B true CN103378067B (en) | 2018-04-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210350992.1A Active CN103378067B (en) | 2012-04-25 | 2012-09-19 | Wafer assembly with carrying wafer |
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| Country | Link |
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| CN (1) | CN103378067B (en) |
| DE (1) | DE102012107899B4 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104952810B (en) * | 2014-03-26 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of bonded wafers and preparation method thereof |
| CN105762092B (en) * | 2014-12-16 | 2019-02-19 | 北京北方华创微电子装备有限公司 | A kind of semiconductor processing equipment |
| JP6864529B2 (en) * | 2017-04-12 | 2021-04-28 | 日立Astemo株式会社 | Rotary control valve |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202094109U (en) * | 2011-01-30 | 2011-12-28 | 南通富士通微电子股份有限公司 | Carrying device for wafer level packaging |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5236118A (en) * | 1992-05-12 | 1993-08-17 | The Regents Of The University Of California | Aligned wafer bonding |
| US6441504B1 (en) * | 2000-04-25 | 2002-08-27 | Amkor Technology, Inc. | Precision aligned and marked structure |
| JP3991300B2 (en) * | 2000-04-28 | 2007-10-17 | 株式会社Ｓｕｍｃｏ | Manufacturing method of bonded dielectric isolation wafer |
| DE10029035C1 (en) * | 2000-06-13 | 2002-02-28 | Infineon Technologies Ag | Process for processing a wafer |
| JP2002252157A (en) * | 2001-02-22 | 2002-09-06 | Sony Corp | Member for preparing mask and method for preparing the same, mask and method for preparing the same, exposure method and method for preparing semiconductor device |
| DE102006054311B4 (en) * | 2006-11-17 | 2012-05-24 | Infineon Technologies Ag | A method of manufacturing a semiconductor device and semiconductor device manufacturable therewith |
| US8017451B2 (en) * | 2008-04-04 | 2011-09-13 | The Charles Stark Draper Laboratory, Inc. | Electronic modules and methods for forming the same |
| US8487354B2 (en) * | 2009-08-21 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving selectivity of epi process |
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2012
- 2012-08-28 DE DE102012107899.8A patent/DE102012107899B4/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202094109U (en) * | 2011-01-30 | 2011-12-28 | 南通富士通微电子股份有限公司 | Carrying device for wafer level packaging |
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| Publication number | Publication date |
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| CN103378067A (en) | 2013-10-30 |
| DE102012107899A1 (en) | 2013-10-31 |
| DE102012107899B4 (en) | 2014-07-17 |
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