CN103377953A - Method for forming single sided buried strap - Google Patents
Method for forming single sided buried strap Download PDFInfo
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- CN103377953A CN103377953A CN2012101286971A CN201210128697A CN103377953A CN 103377953 A CN103377953 A CN 103377953A CN 2012101286971 A CN2012101286971 A CN 2012101286971A CN 201210128697 A CN201210128697 A CN 201210128697A CN 103377953 A CN103377953 A CN 103377953A
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- sided buried
- conductive strips
- trench
- buried conductive
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Abstract
The invention discloses a method for forming a single sided buried strap. The method for forming the single sided buried strap includes the following steps that firstly, a substrate is provided, the substrate comprises a deep trench, a trench capacitor is arranged in the deep trench, a conducting layer is formed in the deep trench, and the conducting layer covers the trench capacitor; secondly, a lining layer is formed on the conducting layer, and a sacrificial layer is formed on the lining layer; thirdly, a part of the sacrificial layer is removed so that a part of the lining layer can be exposed, the rest of the sacrificial layer forms an oxidized mask layer, the oxidized mask layer serves as a mask so that a shallow trench can be formed in the deep trench, and a side trench is formed in one side, close to the substrate, of the shallow trench; finally, an isolating layer is formed in the shallow trench and the side trench, and therefore the conducting layer forms the single sided buried strap.
Description
Technical field
The present invention relates to a kind of method that forms single-sided buried conductive strips, special, related to a kind of formation method that can promote single-sided buried conductive strips reliability, to improve the quality of ditching type capacitor dynamic random access storage.
Background technology
In order to improve the service speed of integrated circuit, and meet the consumer for the demand of miniaturization electronic installation, the transistor size in the semiconductor device has the trend that continues to dwindle.Yet, along with dwindling of transistor size, passage (channel) section length also can and then shorten, the problem that so causes transistor descended by serious short-channel effect (short channel effect) and On current (on current).For this problem, existing a kind of solution is the dopant concentration that improves in the channel region, but this kind practice can cause the increase of leakage current (1eakage current) on the contrary, and affects the reliability of element.This situation has also limited the development of present dynamic random access memory (dynamic random access memory, DRAM).
In order to solve the above problems, industry proposes a kind of framework that is called ditching type capacitor dynamic random access storage (trench DRAM) at present.The ditching type dynamic random access memory is to etch first deep trenches (deep trench) in semiconductor substrate, in deep trenches, make again channel capacitor, then utilize and imbed conductive strips electrical connection channel capacitor and metal-oxide semiconductor (metal-oxide semiconductor, MOS) transistor, significantly reducing the horizontal unit are of memory cell (memory cell), and then increase the integrated level of semiconductor element.And for fear of the phase mutual interference between adjacent memory cell (memory cell), imbedding conductive strips also develops into gradually and only has monolateral conductive strips (the single sided buried strap that imbeds, SSBS), but because the degree of difficulty of manufacture craft is high, often cause single-sided buried conductive strips width variability large, and then affect electrical performance so that resistance value is unstable.
Therefore, also need the manufacture craft of the high single-sided buried conductive strips of a kind of reliability, to improve the reliability of memory.
Summary of the invention
Therefore the present invention provides a kind of method that forms single-sided buried conductive strips, can be applied in the ditching type capacitor dynamic random access storage, and can increase the quality of single-sided buried conductive strips, to improve the yield of product.
According to an embodiment of the invention, the invention provides a kind of method that forms single-sided buried conductive strips.At first, provide a substrate, include deep trenches in the substrate, and be provided with channel capacitor in the deep trenches.Form conductive layer in deep trenches, conductive layer covers on the channel capacitor.Then form laying at conductive layer, and form sacrifice layer at laying.Then remove the sacrifice layer of part, to expose the laying of part, residual sacrifice layer becomes the oxidation mask layer.Take the oxidation mask layer as mask, in deep trenches, to form shallow trench.At the side formation lateral sulcus canal of shallow trench near substrate.At last, in shallow trench and lateral sulcus canal, form separator, so that conductive layer forms single-sided buried conductive strips.
One of them is characterised in that the present invention after having formed shallow trench, also further at the side formation lateral sulcus canal of shallow trench near substrate, and carries out a reduction technique to enlarge the opening of deep trenches.By above-mentioned step, can guarantee that single-sided buried conductive strips can be formed on a side of deep trenches smoothly, opposite side is then inserted separator, to improve the yield of product.
Description of drawings
Fig. 1 is to Figure 9 shows that the present invention forms the step schematic diagram of single-sided buried conductive strips.
Wherein, description of reference numerals is as follows:
300 substrates, 318 sacrifice layers
302 deep trenches, 319 doped layers
304 irrigation canals and ditches bottoms, 320 angled ion injection technologies
306 irrigation canals and ditches tops, 322 breach
308 dielectric layers, 324 oxidation mask layers
310 conductive layers, 325 shallow trench
312 layings, 326 lateral sulcus canals
314 cushioning surface layers, 328 separator
316 trench liner layers, 330 single-sided buried conductive strips
Embodiment
For making those skilled in the art further understand the present invention, the following description has been enumerated the preferred embodiment for the present invention, and cooperates accompanying drawing and explanation, with the effect that describes content of the present invention in detail and wish to realize.
Please refer to Fig. 1 to Fig. 9, be depicted as the manufacturing process steps schematic diagram that the present invention forms single-sided buried conductive strips.As shown in Figure 1, one substrate 300 at first is provided, for example be silicon base (silicon substrate), epitaxial silicon substrate (epitaxial silicon substrate), SiGe semiconductor base (silicon germanium substrate), silicon carbide substrate (silicon carbide substrate) or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc., but not as limit.Then form a deep trenches 302 by photoetching and etch process in substrate 300, deep trenches 302 has an irrigation canals and ditches bottom 304 and an irrigation canals and ditches top 306.Then, by for example depositing operation, arsenic silex glass (arsenic silicate glass, ASG) steps such as diffusion technology, etch process, depositing operation, 304 form a channel capacitor (not shown) in the irrigation canals and ditches bottom, and one dielectric layer 308 between channel capacitor and substrate 300, and 310 of conductive layers are on dielectric layer 308 and fill up deep trenches 302.In one embodiment of the invention, dielectric layer 308 for example is silicon dioxide layer, and conductive layer 310 for example is doped polysilicon layer.Then, forming a laying 312 in substrate 300, for example is a silicon nitride (silicon nitride) layer.In an embodiment of the invention, laying 312 comprises a cushioning surface layer 314 and a trench liner layer 316.314 on cushioning surface layer is on the surface of substrate 300, trench liner layer 316 then the position above conductive layer 310.Preferred, cushioning surface layer 314 is to form by different depositing operations with trench liner layer 316, and the thickness of the Thickness Ratio trench liner layer 316 of cushioning surface layer 314 is thicker, and for example the Thickness Ratio of the Thickness Ratio trench liner layer 316 of cushioning surface layer 314 is 3 to 1.In an embodiment, the thickness of cushioning surface layer 312 is 10 to 50 nanometers (nanometer, nm), and the thickness of trench liner layer 316 is 5 to 10 nanometers.
As shown in Figure 2, form a sacrifice layer 318 on substrate 300 surfaces.The conformal surface that covers cushioning surface layer 314 and trench liner layer 316 of sacrifice layer 318 meetings (conformally), but can't fill up deep trenches 302.In one embodiment of the invention, sacrifice layer 318 can be amorphous silicon layer (amorphous silicon) or polysilicon layer (poly-silicon).
As shown in Figure 3, carry out an angled ion injection technology 320, for example with arsenic (arsenic, As) ion, boron fluoride ion (boron fluoride ion, BF
2 +), argon (argon, Ar), phosphorus (phosphorous, P) plasma inject the surface of sacrifice layer 318.In an embodiment of the present invention, be to be injected to the boron fluoride ion for preferred, but still can adjust according to the different process demand.In addition, in a preferred embodiment of the invention, angled ion injection technology 320 is to inject sacrifice layer 320 with an inclined angle alpha of comparing substrate 300 normals, and the angle of inclined angle alpha is minimum, for example be 20 degree or less angles, therefore the sacrifice layer 318 in deep trenches 302 only has part can be injected into ion, and for instance, the sacrifice layer 318 of position on cushioning surface layer 314 left side sidewall and part bottom trench liner layer 316 can not be injected into ion.
As shown in Figure 4, formed doped layer 319 by the sacrifice layer 318 of Implantation.Then use etchants such as containing ammonia, carry out a wet etching process, remove the sacrifice layer 318 that does not form doped layer 319, and form a breach 322, and expose the cushioning surface layer 314 of part trench liner layer 316 and part.
As shown in Figure 5, carrying out an oxidation technology, for example is a thermal oxidation technology, so that doped layer 319 is formed an oxidation mask layer 324.
As shown in Figure 6, take oxidation mask layer 324 as etching mask, carry out an etch process, the trench liner layer 316 and the conductive layer 310 partly that are covered to remove not oxidized mask layer 324, and in deep trenches 302, form a shallow trench 325.It should be noted that because the restriction of existing technique, oxidation mask layer 324 may protrude from the cushioning surface layer 314 and not and cushioning surface layer 312 vertically trim.It is residual that the left side of the shallow trench 325 that therefore forms also can have conductive layer 310.
As shown in Figure 7, in order to remove the residual conductive layer 310 in shallow trench 325 left sides, a follow-up isotropic etching (isotropic etching) technique of carrying out again is enlarging shallow trench 325, until the conductive layer 310 in the left side of shallow trench 324 is removed fully.Preferred, can further be etched to substrate 300, to form a lateral sulcus canal 326 in shallow trench 325 left sides.Then, remove oxidation mask layer 324.
As shown in Figure 8, laying 312 is carried out a reduction technique (pull back), so that laying 312 reduces toward two outsides of deep trenches 302 equably.In a preferred embodiment of the invention, the trench liner layer 316 in the laying 312 can be removed fully, and only stays cushioning surface layer 314.The opening that can have thus, more space at the A place of Fig. 8.
As shown in Figure 9, with separator 328, for example be a silicon dioxide layer, be filled in shallow trench 324 and the lateral sulcus canal 326.The method that forms separator 328 for example is that known shallow trench isolation (shallow trench isolation, STI) forms technique.Because shallow trench 325 has larger opening A, therefore separator 328 can successfully be inserted, and the conductive layer 310 in the deep trenches 302 can form single-sided buried conductive strips smoothly, and for example directly contact substrate of right side of a side of conductive layer 310, and an other side for example the left side, then be isolated the layer 328 completely cut off.
In sum, the invention provides a kind of method that forms single-sided buried conductive strips, one of them feature is after having formed shallow trench, also further at the side formation lateral sulcus canal of shallow trench near substrate, removing conductive layer herein fully, follow-up and carry out a reduction technique to enlarge the opening of shallow trench.By above-mentioned step, can guarantee that single-sided buried conductive strips can be formed on a side of deep trenches smoothly, opposite side is then inserted separator, guarantees the electrical performance that channel capacitor is connected with the metal-oxide semiconductor transistor.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a method that forms single-sided buried conductive strips is characterized in that, comprising:
Substrate is provided, includes deep trenches in the described substrate;
In described deep trenches, form conductive layer;
On described conductive layer, form successively laying and sacrifice layer;
Remove the described sacrifice layer of part, to expose the described laying of part;
Remove the described conductive layer of part, in described deep trenches, to form shallow trench;
At the side formation lateral sulcus canal of described shallow trench near described substrate, comprise the described conductive layer and the described substrate of part that remove part; And
In described shallow trench and described lateral sulcus canal, form separator, so that described conductive layer forms single-sided buried conductive strips.
2. the method for the single-sided buried conductive strips of formation according to claim 1 is characterized in that, described laying comprises:
The cushioning surface layer is arranged on the surface of described substrate; And
The trench liner layer is arranged on the described conductive layer of described deep trenches.
3. the method for the single-sided buried conductive strips of formation according to claim 2 is characterized in that, the thickness of described cushioning surface layer is greater than the thickness of described trench liner layer.
4. the method for the single-sided buried conductive strips of formation according to claim 2 is characterized in that, the Thickness Ratio of the thickness of described cushioning surface layer and described trench liner layer is 3: 1.
5. the method for the single-sided buried conductive strips of formation according to claim 2 is characterized in that, after forming described lateral sulcus canal, also comprises and reduces technique.
6. the method for the single-sided buried conductive strips of formation according to claim 5 is characterized in that, described reduction technique can remove described trench liner layer fully.
7. the method for the single-sided buried conductive strips of formation according to claim 1 is characterized in that, the step that removes the described sacrifice layer of part comprises:
Carry out the angled ion injection technology, with ion the part described sacrifice layer in; And
Remove not by the part sacrifice layer of Implantation, to form doped layer.
8. the method for the single-sided buried conductive strips of formation according to claim 7 is characterized in that, the step that forms described shallow trench comprises:
Carry out oxidation technology, so that described doped layer forms the oxidation mask layer; And
Carry out etch process take described oxidation mask layer as mask, to remove the described conductive layer of part.
9. the method for the single-sided buried conductive strips of formation according to claim 7 is characterized in that, described angled ion injection technology is to carry out with the predetermined angular compared to described substrate normal, and described predetermined angular is in fact less than 20 degree.
10. the method for the single-sided buried conductive strips of formation according to claim 8 is characterized in that, after forming described lateral sulcus canal, also comprises removing described oxidation mask layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101286971A CN103377953A (en) | 2012-04-27 | 2012-04-27 | Method for forming single sided buried strap |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101286971A CN103377953A (en) | 2012-04-27 | 2012-04-27 | Method for forming single sided buried strap |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230352549A1 (en) * | 2021-07-21 | 2023-11-02 | Nanya Technology Corporation | Manufacturing method of semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1272688A (en) * | 1999-03-24 | 2000-11-08 | 因芬尼昂技术北美公司 | Dynamic random access stoarge |
| CN1567570A (en) * | 2003-06-11 | 2005-01-19 | 南亚科技股份有限公司 | Method for making memory cell having single side bury band |
| US20070235833A1 (en) * | 2006-03-30 | 2007-10-11 | International Business Machines Corporation | Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures |
| US20100090348A1 (en) * | 2008-10-10 | 2010-04-15 | Inho Park | Single-Sided Trench Contact Window |
-
2012
- 2012-04-27 CN CN2012101286971A patent/CN103377953A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1272688A (en) * | 1999-03-24 | 2000-11-08 | 因芬尼昂技术北美公司 | Dynamic random access stoarge |
| CN1567570A (en) * | 2003-06-11 | 2005-01-19 | 南亚科技股份有限公司 | Method for making memory cell having single side bury band |
| US20070235833A1 (en) * | 2006-03-30 | 2007-10-11 | International Business Machines Corporation | Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures |
| US20100090348A1 (en) * | 2008-10-10 | 2010-04-15 | Inho Park | Single-Sided Trench Contact Window |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230352549A1 (en) * | 2021-07-21 | 2023-11-02 | Nanya Technology Corporation | Manufacturing method of semiconductor structure |
| US11967628B2 (en) * | 2021-07-21 | 2024-04-23 | Nanya Technology Corporation | Manufacturing method of semiconductor structure |
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