CN103377889B - The formation method of doping profile - Google Patents
The formation method of doping profile Download PDFInfo
- Publication number
- CN103377889B CN103377889B CN201210107778.3A CN201210107778A CN103377889B CN 103377889 B CN103377889 B CN 103377889B CN 201210107778 A CN201210107778 A CN 201210107778A CN 103377889 B CN103377889 B CN 103377889B
- Authority
- CN
- China
- Prior art keywords
- formation method
- doping profile
- doped region
- subpulse
- semiconductor base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Physical Vapour Deposition (AREA)
Abstract
The invention discloses a kind of formation method of doping profile, its step comprises: provide semiconductor base, and carries out ion implantation technology to semiconductor base.When carrying out ion implantation technology, apply to float pulsed bias at semiconductor base, in order to form multiple doped region with different depth or variable concentrations in the semiconductor substrate.
Description
Technical field
The present invention relates to a kind of formation method of doping profile, particularly relate to and a kind ofly form multiple formation method with the doping profile of the doped region of different depth/concentration by primary ions injection technology.
Background technology
Common semiconductor device is such as: mos field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistors; MOSFET) be employed widely in semiconductor processing.General MOS transistor includes a MOS capacitor, and two positions are in capacitor both sides and electrically contrary with semiconductor base doped region, are called source electrode (source) and drain (drain).When adding suitable bias voltage, MOS transistor can be considered as a kind of solid-state switch (switch) in circuit, is used for controlling the conducting of electric current, and then framework goes out a complete integrated circuit.
In order to more accurately control the technological quality of MOS transistor, commonly in semiconductor base below MOS transistor be provided with multiple doped region and comprise: adjustment grid threshold values (thresholdvoltage, Vt) doped region, prevent source electrode (source) from wearing (anti-punch-through) doped region with the resistance of drain electrode (drain) abnormal conducting, channel stop (channelstop) doped region, and well doped region etc.Because above-mentioned doped region has different depth, prior art need by repeatedly ion implantation technology is to form above-mentioned doped region respectively in the semiconductor substrate, and processing step is loaded down with trivial details, is unfavorable for the lifting of production capacity.
Therefore, as how simple step forms multiple doped region with different depth, by simplified manufacturing technique with reduce semiconductor device production cost be semiconductor industry important topic.
Summary of the invention
In view of this, the present invention discloses a kind of formation method of doping profile, can form multiple doped region with different depth/concentration by simple step.
According to a preferred embodiment of the invention, the invention provides a kind of formation method of doping profile, comprising: semiconductor base is provided, and ion implantation technology is carried out to semiconductor base.When carrying out ion implantation technology, apply to float pulsed bias at semiconductor base, in order to form multiple doped region with different depth or variable concentrations in the semiconductor substrate.
The present invention is applied to the pulsed bias of semiconductor base by changing, comprise the voltage of adjustment pulsed bias, action time, duty ratio or acting frequency or combinations thereof, form multiple doped region with different depth with primary ions injection technology simultaneously, can simplified manufacturing technique, effectively reduce semiconductor device production time and cost.
Accompanying drawing explanation
Figure 1 shows that the schematic diagram of parallel electroplax plasma board illustrated according to a preferred embodiment of the invention.
Figure 2 shows that the sequence of operation of floating pulsed bias illustrated according to a preferred embodiment of the invention and the schematic diagram of action time.
Figure 3 shows that the sequence of operation of floating pulsed bias illustrated according to another preferred embodiment of the invention and the schematic diagram of action time.
Figure 4 shows that the sequence of operation of floating pulsed bias illustrated according to another preferred embodiment of the invention and the schematic diagram of action time.
Fig. 5 is to the schematic diagram of formation method that Figure 6 shows that doping profile illustrated according to a preferred embodiment of the invention.
Wherein, description of reference numerals is as follows:
10 plasma board 12 airtight reaction chamber
Electroplax 16 times electroplaxs on 14
18 semiconductor base 20 power supplys
22 process gas 24 plasmas
26 source electrodes 28 drain
30 shallow trench isolations are from the T1 cycle
D1, D2, D3, D4 doped region
L, M, N float pulsed bias
L1, L2, L3, M1, M2, M3, N1, subpulse bias voltage
N2，N3
T2, T3, T4, T5, T6 action time
V, V1, V2, V3, V4, V5 voltage
Embodiment
The present invention can be applied in the various board providing radio frequency plasma (RFplasma), is next, for parallel electroplax plasma board (parallelplateplasmaprocessingapparatus), the present invention is described.Please refer to Fig. 1, Figure 1 shows that the schematic diagram of parallel electroplax plasma board illustrated according to a preferred embodiment of the invention.As shown in Figure 1, parallel electroplax plasma board 10 includes airtight (airtight) reative cell 12, has the upper electroplax 14 parallel up and down of specific range and lower electroplax 16 for a pair, in addition, the semiconductor base 18 that pending plasma injects is placed on lower electroplax 16.Upper electroplax 14 is applied in a voltage V, lower electroplax 16 is applied a floating pulsed bias by power supply 20, and the process gas 22 importing a suitable flow is in the airtight reaction chamber 12 of applicable generation plasma, under the frequency of applicable process gas 22, by coupled RF power (RFpower), process gas 22 is burnt to form the surface of plasma 24 at semiconductor base 18.Floating pulsed bias also can be applied to the semiconductor base 18 on lower electroplax 16, therefore, the floating pulsed bias that the plasma 24 formed in semiconductor base 18 surface can be subject to semiconductor base 18 affects and the surface of bombarding semiconductor substrate 18, the pulsed bias that wherein floats the dopant of accelerate plasma 24 can inject semiconductor base 18, reaches ion implantation and forms the object of doped region.
It should be noted that, the present invention is applied to the fixed waveform of floating pulsed bias not repetition on the sequential chart of pulsed bias of semiconductor base 18, that is, floating pulsed bias of the present invention is made up of jointly multiple multiple subpulse bias voltages with different wave.
Please refer to Fig. 2, Figure 2 shows that the sequence of operation of floating pulsed bias illustrated according to a preferred embodiment of the invention and the schematic diagram of action time.As shown in Figure 2, abscissa is time t, ordinate is voltage U, solid line L represents the floating pulsed bias that the downward electroplax of power supply exports, that is is applied to the floating pulsed bias L of semiconductor base 18, comprises multiple subpulse bias voltage L1/L2/L3, wherein V1/V2/V3 is voltage, T1 is the cycle, and T2 is the action time of pulsed bias, and T2: T1 is duty ratio.In the present embodiment, subpulse bias voltage L1/L2/L3 has same duty cycle, in addition, the voltage V1 of subpulse bias voltage L1 is greater than in fact the voltage V2 of subpulse bias voltage L2, the size of the voltage V2 of subpulse bias voltage L2 is greater than in fact the voltage V3 of subpulse bias voltage L3, size due to voltage V1/V2/V3 is just corresponding to the intensity of the plasma 24 formed, that is, the size of voltage V1/V2/V3 just corresponds to the degree of depth of doped region and the quantity of dopant, therefore, floating pulsed bias L is applied to semiconductor base 18, multiple doped region with different depth/concentration can be formed in semiconductor base 18, in more detail, the degree of depth/concentration corresponding to the doped region of subpulse bias voltage L1 formation is greater than in fact the degree of depth/concentration of the doped region formed corresponding to subpulse bias voltage L2, and the degree of depth/concentration corresponding to the doped region that subpulse bias voltage L2 is formed is greater than in fact the degree of depth/concentration of the doped region formed corresponding to subpulse bias voltage L3, in brief, the present invention can form multiple doped region with different depth/concentration in primary ions injection technology simultaneously.
Please refer to Fig. 3, Figure 3 shows that the sequence of operation of floating pulsed bias illustrated according to another preferred embodiment of the invention and the schematic diagram of action time.As shown in Figure 3, solid line M represents the floating pulsed bias that the downward electroplax of power supply exports, that is be applied to the floating pulsed bias M of semiconductor base, comprise multiple subpulse bias voltage M1/M2/M3, wherein V4 is voltage, T1 is the cycle, and T3/T4/T5 is the action time of pulsed bias, T3: T1/T4: T1/T5: the T1 duty ratio being respectively subpulse bias voltage M1/M2/M3.In the present embodiment, subpulse bias voltage M1/M2/M3 has identical voltage V4, in addition, T3 action time of subpulse bias voltage M1 is greater than in fact T4 action time of subpulse bias voltage M2, and T4 action time of subpulse bias voltage M2 is greater than in fact T5 action time of subpulse bias voltage M3.Due to varying in size of T3/T4/T5 action time, subpulse bias voltage M1/M2/M3 also has different duty ratios, and action time T3/T4/T5 and duty ratio all just corresponding to and injecting the dopant quantity of semiconductor base 18 and the degree of depth, therefore, floating pulsed bias M is applied to semiconductor base 18, the degree of depth/concentration corresponding to the doped region of subpulse bias voltage M1 formation is greater than in fact the degree of depth/concentration of the doped region formed corresponding to subpulse bias voltage M2, and the degree of depth/concentration corresponding to the doped region that subpulse bias voltage M2 is formed is greater than in fact the degree of depth/concentration of the doped region formed corresponding to subpulse bias voltage M3.
Similarly, for forming multiple doped region with different depth/concentration, also the acting frequency of adjustable subpulse bias voltage, please refer to Fig. 4, Figure 4 shows that the sequence of operation of floating pulsed bias illustrated according to another preferred embodiment of the invention and the schematic diagram of action time.As shown in Figure 4, solid line N represents the floating pulsed bias being applied to semiconductor base 18, and comprise multiple subpulse bias voltage N1/N2/N3, wherein V5 is voltage, and T1 is the cycle, and T6 is the action time of pulsed bias.In the present embodiment, subpulse bias voltage N1/N2/N3 has identical voltage V5, in addition, the acting frequency of subpulse bias voltage N1 is greater than in fact the acting frequency of subpulse bias voltage N2, and the acting frequency of subpulse bias voltage N2 is greater than in fact the acting frequency of subpulse bias voltage N3.The size of acting frequency is just corresponding to the dopant quantity and the degree of depth that inject semiconductor base, therefore, the degree of depth/concentration corresponding to the doped region of subpulse bias voltage N1 formation is greater than in fact the degree of depth/concentration of the doped region formed corresponding to subpulse bias voltage N2, and the degree of depth/concentration corresponding to the doped region that subpulse bias voltage N2 is formed is greater than in fact the degree of depth/concentration of the doped region formed corresponding to subpulse bias voltage N3.
Please refer to Fig. 5 to Fig. 6, Fig. 5 is to the schematic diagram of formation method that Figure 6 shows that doping profile illustrated according to a preferred embodiment of the invention.As shown in Figure 5, first, provide semiconductor base 18, and semiconductor base 18 can comprise the substrate be such as made up of silicon, GaAs, silicon-coated insulated (SOI) layer, epitaxial loayer, germanium-silicon layer or other semiconductor base materials.Then, semiconductor base 18 is carried out to the ion implantation technology P1 of above-mentioned explanation, that is, when carrying out ion implantation technology P1, apply to float pulsed bias at semiconductor base 18, floating pulsed bias comprises the subpulse bias voltage of combination in any with different voltage, different duty ratios, different acting frequency or above-mentioned explanation, in semiconductor base 18, multiple doped region D1/D2/D3/D4 with different depth/concentration is formed, jointly to form required doping profile with primary ions injection technology P1.In addition, the present invention does not limit the order of subpulse bias voltage yet, before the doped region that namely limited depth/concentration is not larger is formed in the less doped region of the degree of depth/concentration.In addition, annealing process can be carried out further again, to become into (drive-in) and to activate the dopant of each doped region D1/D2/D3/D4.
As shown in Figure 6, after carrying out follow-up semiconductor technology, adjustment grid threshold values (thresholdvoltage is can be used as near the doped region D1 on semiconductor base 18 surface, Vt) doped region, the doped region D2 of position between source electrode 26 and drain electrode 28 and below the D1 of doped region can be used as and prevent source electrode 26 from wearing (anti-punch-through) doped region with the resistance of drain electrode 28 abnormal conductings, and position at shallow trench isolation from (shallowtrenchisolation, STI) the doped region D3 below the D2 of between 30 and doped region can be used as channel stop (channelstop) doped region, and the doped region D4 of position below the D3 of doped region can be used as well doped region.The present invention does not need by repeatedly ion implantation technology, and namely available primary ions injection technology forms required doping profile.
In sum, the present invention is applied to the pulsed bias of semiconductor base by changing, comprise the voltage of adjustment pulsed bias, action time, duty ratio or acting frequency or combinations thereof, form multiple doped region with different depth with primary ions injection technology simultaneously, can simplified manufacturing technique, effectively reduce semiconductor device production time and cost.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a formation method for doping profile, is characterized in that, comprising:
Semiconductor base is provided; And
By carrying out ion implantation technology to described semiconductor base, and apply to float pulsed bias at described semiconductor base, in order to form multiple doped region with different depth or variable concentrations in described semiconductor base, wherein said floating pulsed bias comprises multiple subpulse bias voltage.
2. the formation method of doping profile according to claim 1, is characterized in that, described multiple subpulse bias voltage comprises multiple voltage.
3. the formation method of doping profile according to claim 2, is characterized in that, the size of described multiple voltage is just corresponding to the degree of depth/concentration of described doped region.
4. the formation method of doping profile according to claim 1, is characterized in that, described multiple subpulse bias voltage comprises multiple action time.
5. the formation method of doping profile according to claim 1, is characterized in that, described multiple subpulse bias voltage comprises multiple frequency.
6. the formation method of doping profile according to claim 1, is characterized in that, described multiple subpulse bias voltage comprises multiple duty ratio.
7. the formation method of doping profile according to claim 1, is characterized in that, carries out ion implantation technology and also comprises:
There is provided plasma above described semiconductor substrate surface;
With semiconductor substrate surface described in described plasma bombardment.
8. the formation method of doping profile according to claim 7, is characterized in that, the dopant that described floating pulsed bias can accelerate described plasma injects described semiconductor base, to form described doped region.
9. the formation method of doping profile according to claim 1, is characterized in that, also comprise:
Carry out annealing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210107778.3A CN103377889B (en) | 2012-04-13 | 2012-04-13 | The formation method of doping profile |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210107778.3A CN103377889B (en) | 2012-04-13 | 2012-04-13 | The formation method of doping profile |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103377889A CN103377889A (en) | 2013-10-30 |
| CN103377889B true CN103377889B (en) | 2016-03-16 |
Family
ID=49462841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210107778.3A Active CN103377889B (en) | 2012-04-13 | 2012-04-13 | The formation method of doping profile |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103377889B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101203933A (en) * | 2005-03-15 | 2008-06-18 | 瓦里安半导体设备公司 | Profile adjustment in plasma ion implanter |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02144842A (en) * | 1988-11-28 | 1990-06-04 | Hitachi Ltd | Ion implantation device |
| JPH0822799A (en) * | 1994-07-08 | 1996-01-23 | Sony Corp | Ion implanting device and ion implanting method |
| US7888245B2 (en) * | 2006-05-11 | 2011-02-15 | Hynix Semiconductor Inc. | Plasma doping method and method for fabricating semiconductor device using the same |
| KR20100121981A (en) * | 2009-05-11 | 2010-11-19 | 엘아이지에이디피 주식회사 | Plasma doping method using frequency modulation |
| US20110201185A1 (en) * | 2010-02-17 | 2011-08-18 | Tech Semiconductor Singapore Pte Ltd | Method to improve transistor performance matching for plasma-assisted source/drain formation |
-
2012
- 2012-04-13 CN CN201210107778.3A patent/CN103377889B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101203933A (en) * | 2005-03-15 | 2008-06-18 | 瓦里安半导体设备公司 | Profile adjustment in plasma ion implanter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103377889A (en) | 2013-10-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105161539A (en) | Silicon carbide metal-oxide-semiconductor field-effect-transistor (MOSFET) device and fabrication method thereof | |
| CN105448983B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN101153383B (en) | Control method for ionic beam electric charge | |
| US20100041218A1 (en) | Usj techniques with helium-treated substrates | |
| CN102931093A (en) | N-channel depletion type power MOSFET device and manufacturing method thereof | |
| US20080146009A1 (en) | Method for Introducing Impurities | |
| CN103377889B (en) | The formation method of doping profile | |
| CN101764094B (en) | Method for regulating threshold voltage of complementary metal oxide semiconductor | |
| US8124506B2 (en) | USJ techniques with helium-treated substrates | |
| CN115458397A (en) | Method for manufacturing silicon oxynitride film | |
| Raj et al. | Plasma doping of high aspect ratio structures | |
| US20200119173A1 (en) | Advanced field stop thyristor structure and manufacture methods | |
| CN100560790C (en) | Control method for ionic beam electric charge | |
| CN102446700A (en) | Method for improving silicon substrate and obtained silicon substrate | |
| CN102623313A (en) | Ring ion injection method, semiconductor device and manufacture method thereof | |
| CN102867755A (en) | Method for forming NMOS (N-channel metal oxide semiconductor) device with low GIDL (gate induced drain leakage) current | |
| CN101770955B (en) | Method for manufacturing P-type metal oxide semiconductor | |
| CN104752499A (en) | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method | |
| WO2022205169A1 (en) | Field effect transistor and manufacturing method therefor, and switching circuit and circuit board | |
| CN101764095B (en) | Method for processing CMOS chip and instrument | |
| CN102738008A (en) | Method for fabricating groove field effect transistor | |
| CN103107094B (en) | A kind of depletion type power field effect transistor and preparation method thereof | |
| CN102082085A (en) | Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor | |
| CN101894748B (en) | Ion implant method | |
| CN102110652B (en) | Method for manufacturing embedded type semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |