CN103377154B - The memory access control device of storer and method, processor and north bridge chips - Google Patents
The memory access control device of storer and method, processor and north bridge chips Download PDFInfo
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Abstract
A kind of memory access control device of storer and method, processor and north bridge chips.The memory access control device of described storer, comprising: request analysis unit, and for access request is resolved to operational order sequence, described operational order sequence comprises some operational orders; Arbitration unit, for arbitrating the operational order in described operational order sequence by referee conditions, to be sent to described storer by operational order.Relative to prior art, technical solution of the present invention is by request analysis unit transmit operation command sequence concurrently, and utilize the first temporal constraint, the second temporal constraint and the 3rd temporal constraint to control to send time interval between current operation order in same operational order sequence and the last operational order adjacent with described current operation order, not only can the multiple memory bank of concurrent access, and can the multiple set of memory banks of concurrent access, achieve multidimensional to walk abreast memory access, the average handling time of remarkable shortening access request, improves entire system memory access performance.
Description
Technical field
The present invention relates to computer memory control field, particularly the memory access control device of storer and method, processor and north bridge chips.
Background technology
Storer is the key factor affecting computer system overall performance, and the lifting of its data transmission rate has positive role to raising processor performance.The speed of processor doubles for approximately every 18 months, and the speed of storer just doubles for approximately every 10 years, and therefore, the raising of processor and memory performance is also asynchronous.Along with the progress of technological level, the speed of processor, considerably beyond the speed of storer, causes the bottleneck occurring " storage wall ".
In order to alleviate the technical bottleneck that " storage wall " brings, memory manufacturer have employed many new memory architectures.With dynamic RAM (DynamicRandomAccessMemory, DRAM) be example, dynamic RAM manufacturer have employed such as many bodies (Multibanking) structure and multiple memory access affairs by concurrent processing, can be have employed two row bufferings (RowBuffer) and make hit continuously can be accelerated process with the memory access affairs of a line.
In order to make the architecture of storer actively play a role, the memory access performance of controller is most important.In the design of controller, arbitration and the scheduling of access request have vital effect to the raising utilization factor of storer and the performance of storage system, are the emphasis of Controller gain variations.Outstanding controller effectively can utilize the architecture of above-mentioned storer, improves memory bandwidth, reduces memory access latency.In prior art, although the processor technology such as employing is looked ahead, Out-of-order execution, prediction, multithreading are conducive to the memory access latency of concealing memory, but the proportion that memory access latency accounts for the processor dead time is still increasing, and the processor technology of many concealing memory access delay also proposes more and more higher requirement to memory bandwidth.
More technical schemes about computer memory control field can be the Chinese patent of CN1588552A with reference to publication number, which disclose a kind of the double speed dynamic random access memory control device and the method that have asynchronous buffer, device comprises moderator, control unit interface and controller.Said apparatus is arbitrated according to the reading and writing data request of requirement to Client Model of decode pipeline framework, the read/write access operation of control data, make use of comparatively greatly the data bandwidth of storer possibly, but, the memory access efficiency of system improves limited, does not still solve the problems of the technologies described above.
Summary of the invention
The problem that the present invention solves is that prior art memory access latency accounts for the proportion of processor dead time comparatively greatly, the problem that memory bandwidth is lower.
Technical solution of the present invention provides a kind of memory access control device, comprising: request analysis unit, and for access request is resolved to operational order sequence, described operational order sequence comprises some operational orders; Arbitration unit, for arbitrating the operational order in described operational order sequence by referee conditions, so that operational order is sent to described storer, described referee conditions comprises: the time interval that operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint; Described first temporal constraint refers to the time interval requirement between the operational order of accessing same memory bank; Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access; Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group.
Alternatively, described request resolution unit comprises the resolution unit that two are associated with described set of memory banks, and each resolution unit comprises some parsing modules being associated with described memory bank.
Alternatively, described arbitration unit comprises: the first temporal constraint register, and its quantity associates with the quantity m of the memory bank in set of memory banks with the quantity c of the type of operational order, the quantity n of set of memory banks; Second temporal constraint register, its quantity associates with the quantity n of set of memory banks with the quantity c of the type of operational order; 3rd temporal constraint register, its quantity associates with the quantity c of the type of operational order; Writing unit, for when after transmit operation order, to corresponding to the first temporal constraint register of the type of operational order sent, the second temporal constraint register and the 3rd temporal constraint register write numerical value, the time interval requirement of numerical associations between the clock period and operational order of described storer of said write; The numerical value of each temporal constraint register based on clock period of described storer from the numerical value of write from reducing to 0; Control module, for when corresponding to the type of operational order that do not send and specifying the numerical value of the first temporal constraint register of the memory bank in the set of memory banks of access, be 0 corresponding to the type of the described operational order do not sent and the numerical value of the 3rd temporal constraint register of type of specifying the numerical value of the second temporal constraint register of the set of memory banks of access and corresponding to the described operational order do not sent thereof, the operational order do not sent described in transmission is to described storer.
Alternatively, the quantity of described first temporal constraint register is
the quantity of described second temporal constraint register is n × c
2; The quantity of described 3rd temporal constraint register is c
2.
Alternatively, described arbitration unit comprises: the first temporal constraint judging unit, for judging whether the time interval of the transmitting time of current time and last operational order meets the first temporal constraint between current operational order and last operational order, and described current operational order and described last operational order belong to same operational order sequence; Second temporal constraint judging unit, whether the time interval for the transmitting time judging described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order; 3rd temporal constraint judging unit, whether the time interval for the transmitting time judging described current time and described last operational order meets the 3rd temporal constraint between described current operational order and described last operational order; Transmitting element, for when the judged result of the judged result of described first temporal constraint judging unit, the judged result of the second temporal constraint judging unit and the 3rd sequential judging unit is being, to the described current operational order of described storer transmission.
Alternatively, described access request is read request, write request or reads-amendment-write request.
Alternatively, described operational order is activation command, read command, write order or writes back order.
Alternatively, described access request is read request, and described operational order sequence is activation command _ read command _ write back order.
Alternatively, described access request is write request, and described operational order sequence is activation command _ write order _ write back order.
Optionally, described access request is for reading-amendment-write request, and described operational order sequence is activation command _ read command _ write order _ write back order; Or described operational order sequence comprises activation command _ read command _ write back order and activation command _ write order _ write back order.
Technical solution of the present invention also provides a kind of access control method of storer, comprising: access request is resolved to operational order sequence, and described operational order sequence comprises some operational orders; By referee conditions, the operational order in described operational order sequence is arbitrated, so that operational order is sent to storer, described referee conditions comprises: the time interval that described operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint; Described first temporal constraint refers to the time interval requirement between the operational order of accessing same memory bank; Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access; Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group.
Technical solution of the present invention also provides a kind of processor, comprises the memory access control device of above-mentioned storer.
Technical solution of the present invention also provides a kind of north bridge chips, comprises the memory access control device of above-mentioned storer.
Relative to prior art, technical solution of the present invention is by request analysis unit transmit operation command sequence concurrently, and utilize the first temporal constraint, the second temporal constraint and the 3rd temporal constraint to control to send time interval between current operation order in same operational order sequence and the last operational order adjacent with described current operation order, not only can the multiple memory bank of concurrent access (Bank), and can the multiple set of memory banks of concurrent access (Rank), achieve multidimensional and to walk abreast memory access.Experiment proves, technical solution of the present invention significantly can shorten the average handling time of access request, improves entire system memory access performance.In addition, relative to the traditional controller of existing employing " body walk abreast memory access strategy ", technical solution of the present invention does not also obviously increase realization price of hardware.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of controller access SDRAM;
Fig. 2 is the general structure schematic diagram of the memory access control device of the storer that embodiment of the present invention provides;
Fig. 3 is the schematic diagram of an embodiment of request analysis unit;
Fig. 4 is the schematic diagram of an embodiment of arbitration unit;
Fig. 5 is the schematic diagram of an embodiment of the memory access control device of storer provided by the invention;
Fig. 6 is the process flow diagram of the access control method of the storer that embodiment of the present invention provides.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
The synchronous DRAM (SynchronousDynamicRandomAccessMemory, SDRAM) that the embodiment of the present invention generally adopts for modem computer systems is described.Please refer to Fig. 1, Fig. 1 is the schematic diagram of controller access SDRAM.When internal storage access operates, generally send read request, write request by processor to controller 100 or read-amendment-write request, then by controller 100 from internal memory, such as, in SDRAM, carrying out corresponding data manipulation.In Fig. 1, SDRAM only comprises 2 set of memory banks (Rank), and those skilled in the art know, and in systems in practice, can comprise more Rank.
For SDRAM, comprise n and store particle (Chip) in each Rank, the numbering that said n stores particle (Chip) is followed successively by 0,1,2 ..., n-2, n-1.Memory bank (Bank) in each storage particle (Chip) is called physical memory banks (P-Bank).Comprise 8 physical memory banks (P-Bank) in each Chip, the numbering of above-mentioned 8 physical memory banks (P-Bank) is followed successively by 0,1,2 ..., 6,7.Being when reality uses, in order to increase data bit width, generally n Chip can being connected use side by side.Assuming that the bit wide of each Chip is 8bit, then the data bit width of 9 Chip is 8bits*9=72bits.Now, the Bank in each Chip also connects side by side, can regard the physical memory banks (P-Bank) of reference numeral in the above-mentioned Chip connected side by side as a logical memory bank be formed in parallel (L-Bank).As, store the P-Bank0 of particle Chip0, store the P-Bank0 of particle Chip2 ..., store the physics P-Bank0 of particle Chipn, they form logical memory bank (L-Bank0) jointly.That is, in order to increase bit wide, the physical memory banks (P-Bank) of reality being connected use side by side, namely they can be regarded as " Bank that same bit wide is larger ", being called logical memory bank (L-Bank).In present embodiment, unless otherwise indicated, described memory bank (Bank) all refers to logical memory bank (L-Bank).
In addition, for the storer comprising more than three or three Rank, when applying technical solution of the present invention, first the Rank in storer can be divided into two groups, also, all Rank be divided into two logic Rank (L-Rank).In present embodiment, unless otherwise indicated, described set of memory banks (Rank) all refers to logical memory bank group (L-Rank).
With reference to figure 2, the memory access control device 10 of the storer that embodiment of the present invention provides comprises request analysis unit 11 and arbitration unit 12.
Request analysis unit 11, for access request is resolved to operational order sequence, described operational order sequence comprises some operational orders.
Arbitration unit 12, for arbitrating the operational order in described operational order sequence by referee conditions, so that operational order is sent to described storer, described referee conditions comprises: the time interval that operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint.
Described first temporal constraint refers to the time interval requirement between the operational order of the same memory bank of access (Bank); Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access (Rank); Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group.
For SDRAM, the access request of user comprises following three classes:
(1) read request.User uses this request, can take out data from SDRAM.
(2) write request.User uses this request, can by data stored in SDRAM.
(3) " read-revise-write " request.User uses this request, can take out data from SDRAM; Then these data are modified after (as add certain number, deduct certain number etc.) and obtain a new data; Finally, restore this new data this SDRAM.
Operational order, refers to the order that storer can accept, identifies and process.Usually, what operational order comprised will have: order symbol, chip select signal and reference address.At present, for SDRAM, for realizing the various access requests that user sends, the basic operation command required for itself comprises activation command (ACT), read command (RD), write order (WE) and writes back order (PRE).Here, only represent operational order with order symbol for convenience of description, omit other key elements.
Operational order sequence is made up of some operational orders, particularly:
(1) read request, general treatment scheme is: first activate the data line that will access with activation command; Then, with read command access " activated row ", sense data; Finally, use writes back order and activated row is write back storage array.Correspondingly, read request can resolve to by activation command, read command and write back the operational order sequence A CT_RD_PRE that order forms by request analysis unit 11.
(2) write request, general treatment scheme is: first activate the data line that will access with activation command; Then, with write order, data are write " activated row "; Finally, use writes back order and activated row is write back storage array.Correspondingly, write request can resolve to by activation command, write order and write back the operational order sequence A CT_WE_PRE that order forms by request analysis unit 11.
(3) " read-revise-write " request, can regard as and be combined by read request and write request.Request analysis unit 11 can by reading-revise-write request resolves to ACT_RD_WE_PRE, also can by reading-revise-write request resolves to ACT_RD_PRE and ACT_WE_PRE.
About the read-write sequence of memory bank and other ins and outs can see " DDR3SDRAMSpecification ".It should be noted that the embodiment of the present invention only lists conventional operational order type, as ACT, RD, WE, PRE, for the operational order of unlisted other types, technical solution of the present invention is applicable equally.
Illustrate request analysis unit 11 below and how access request is resolved to operational order sequence.In the present embodiment, described storer (such as SDRAM) comprises 2 Rank.As shown in Figure 3, described request resolution unit 11 comprises the resolution unit that two are associated with described set of memory banks, i.e. the first resolution unit 111 and the second resolution unit 112.Each resolution unit is associated with a Rank, and such as, in the present embodiment, the first resolution unit 111 is associated with Rank0, and the second resolution unit 112 is associated with Rank1.Each described resolution unit comprises some parsing modules being associated with described memory bank.
In the present embodiment, the first resolution unit 111 comprises parsing module M00, M01, M02, M03 that 4 are associated with Bank.Because Rank0 comprises 8 Bank (Bank0 to Bank7), and the first resolution unit 111 associated with Rank0 comprises 4 parsing modules, therefore corresponding two Bank of each parsing module, namely can set parsing module M00 and be associated with Bank0 and Bank4, parsing module M01 is associated with Bank1 and Bank5, parsing module M02 is associated with Bank2 and Bank6, and parsing module M03 is associated with Bank3 and Bank7.
Correspondingly, continue with reference to figure 3, described second resolution unit 112 comprises parsing module M10, M11, M12, M13 that 4 are associated with Bank.Because Rank1 comprises 8 Bank (Bank0 to Bank7), and the second resolution unit 112 associated with Rank1 comprises 4 parsing modules, therefore corresponding two Bank of each parsing module, namely can set parsing module M10 and be associated with Bank0 and Bank4, parsing module M11 is associated with Bank1 and Bank5, parsing module M12 is associated with Bank2 and Bank6, and parsing module M13 is associated with Bank3 and Bank7.Namely each parsing module " is responsible for " two Bank.
Access request (such as " read request ", " write request " or " reading-amendment-write request ") all can be resolved to operational order sequence by each parsing module.For parsing module M00: after as parsing module M00, to have received a target be " read request " of the Bank4 of Rank0, first will send an act command, then a RD order is sent, finally send a PRE order, above-mentioned three operational orders form an ACT_RD_PRE operational order sequence, and the Action Target of this operational order sequence is the Bank that parsing module M00 is corresponding.
If send the operational order sequence A CT_RD_PRE of read request at parsing module M00 during, parsing module M01 receives an access request, such as target is the read request of the Bank1 of Rank0, so first parsing module M01 also can send act command, then RD order is sent, finally send PRE order, above-mentioned three operational orders also form an ACT_RD_PRE operational order sequence, the Action Target of the operational order sequence A CT_RD_PRE sent unlike, parsing module M01 with parsing module M00 is the Bank that parsing module M01 is corresponding.
From the general treatment scheme of aforementioned access request (comprise read request, write request or read-amendment-write request), request analysis unit 11 is to storer, such as SDRAM, when transmit operation command sequence, be not that the operational order in this operational order sequence is sent to SDRAM simultaneously.Specifically, for the operational order sequence A CT_RD_PRE resolved by read request, three operational order ACT, RD and PRE are sent to SDRAM simultaneously, need to follow certain constraint condition between operational order.This constraint condition is determined by the physical characteristics of storer.Such as, after memory access control device 11 sends an operational order ACT to SDRAM, can not the RD of transmit operation order at once, but first must wait for the regular hour, after device SDRAM to be stored is ready to, transmit operation order RD could be continued.
For this reason, also arbitration unit is comprised in the memory access control device of storer that the embodiment of the present invention provides.Refer to Fig. 4, described arbitration unit 12 comprises:
First temporal constraint register, its quantity associates with the quantity of the memory bank in set of memory banks with the quantity of the type of operational order, the quantity of set of memory banks.
Second temporal constraint register, its quantity associates with the quantity of set of memory banks with the quantity of the type of operational order.
3rd temporal constraint register, its quantity associates with the quantity of the type of operational order.
Writing unit 126, for when after transmit operation order, to corresponding to the first temporal constraint register of the type of operational order sent, the second temporal constraint register and the 3rd temporal constraint register write numerical value, the time interval requirement of numerical associations between the clock period and operational order of described storer of said write; The numerical value of each temporal constraint register based on clock period of described storer from the numerical value of write from reducing to 0.
Control module 125, for when corresponding to the type of operational order that do not send and specifying the numerical value of the first temporal constraint register of the memory bank in the set of memory banks of access, be 0 corresponding to the type of the described operational order do not sent and the numerical value of the 3rd temporal constraint register of type of specifying the numerical value of the second temporal constraint register of the set of memory banks of access and corresponding to the described operational order do not sent thereof, the operational order do not sent described in transmission is to described storer.
The time interval that the memory access control device of the storer of the embodiment of the present invention is sent by adjacent operator order in the value control operation command sequence that arranges temporal constraint register.Such as, if need wait 9 clock period could transmit operation order RD after transmit operation order ACT, then after have sent operational order ACT, the value of temporal constraint register can be set to 9, then often through a clock period, the value of this temporal constraint register is subtracted 1, also namely have passed through 9 clock period when the value of this temporal constraint register is 0 time, now just can transmit operation order RD.Therefore, utilize the temporal constraint that temporal constraint register can realize between operational order.
It should be noted that the time interval between operational order requires relevant with adopted storer.In the embodiment of the present invention, the memory access control device of storer adopts configurable mode, and it is periodic associated that each write timing retrains the numerical value of register and the physical characteristics of storer and clock.Such as, if require that the clock period is 1.5ns, then can write numerical value 15ns/1.5ns=10 in the temporal constraint register of correspondence for 15ns (depending on the physical characteristics of storer) from the time interval operational order ACT to operational order RD.
Specifically, refer to Fig. 4, arbitration unit 12 comprises several the first temporal constraint registers, several the second temporal constraint registers and several the 3rd temporal constraint registers.Suppose in the present embodiment that the quantity of the type of operational order is c, the quantity of set of memory banks (Rank) is n, and in each Rank, the quantity of memory bank (Bank) is m.
The quantity of described first temporal constraint register associates with the quantity of the memory bank in set of memory banks with the quantity of the type of operational order, the quantity of set of memory banks.
In the present embodiment, the quantity of described first temporal constraint register can be:
Namely described arbitration unit 12 comprises
individual first temporal constraint register, in table 1.
Table 1. first temporal constraint register
The quantity of described second temporal constraint register associates with the quantity of set of memory banks with the quantity of the type of operational order.
In the present embodiment, the quantity of described second temporal constraint register can be:
n×c
2，
Namely described arbitration unit 12 comprises n × c
2=2 × 4
2=32 the second temporal constraint registers, in table 2.
Table 2. second temporal constraint register
The quantity of described 3rd temporal constraint register associates with the quantity of the type of operational order.
In the present embodiment, the quantity of described 3rd temporal constraint register can be: c
2,
Namely described arbitration unit 12 comprises c
2=4
2=16 the 3rd temporal constraint registers, in table 3.
Table 3. the 3rd temporal constraint register
" X2Y " expression " operational order X is to the constraint of operational order Y " in above-mentioned first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.Such as, ACT2RD represents the constraint of operational order ACT to operational order RD, and the operational order ACT namely first sent is to the time interval requirement of the operational order RD of rear transmission.
The operational order sequence being the Bank3 of Rank0 for the target of a parsing module M03 transmission below describes the course of work of the memory access control device of described storer in detail.
When the parsing module M03 in request analysis unit receives the read request that user sends, as previously mentioned, parsing module M03 first can send an act command, then a RD order is sent, finally send a PRE order, above-mentioned three operational orders form an ACT_RD_PRE operational order sequence, and the Action Target of this operational order sequence is the Bank that parsing module M03 is corresponding.
First, for operational order ACT, it sends the Bank3 that target is Rank0, then the control module in arbitration unit 12 checks whether the value of following register is 0:
Rank0_SameBank37_ACT2ACT；Rank0_SameBank37_RD2ACT；
Rank0_SameBank37_WE2ACT；Rank0_SameBank37_PRE2ACT；
Above-mentioned four registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2ACT；Rank0_DiffBank_RD2ACT；
Rank0_DiffBank_WE2ACT；Rank0_DiffBank_PRE2ACT；
Above-mentioned four registers belong to the second temporal constraint register.
DiffRank_ACT2ACT；DiffRank_RD2ACT；
DiffRank_WE2ACT；DiffRank_PRE2ACT。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
When control module checks that the value of above-mentioned first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register is 0, described arbitration unit 12 is arbitrated by described operational order ACT, and the memory access control device of described storer sends described operational order ACT to described storer.If the value of above-mentioned register is not all 0, then above-mentioned register is simultaneously from subtracting, and such as each clock period is from subtracting 1; If the value of above-mentioned register is not that 0 (value of some register is 0 entirely, the value of some register is not 0), so, at following clock cycle, described request resolution unit 11 continues to send this operational order ACT, and described control module continues to check whether the value of above-mentioned register is 0, until the value of above-mentioned register is 0, described arbitration unit 12 is arbitrated by described operational order ACT, and the memory access control device of described storer sends described operational order ACT to described storer.
In the present embodiment, the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register each clock period are from subtracting 1.In other embodiments, also can design make the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register every two clock period or more clock period carries out from subtracting.Correspondingly, the numerical value of the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register write is also different.Such as, if require as 15ns (depending on the physical characteristics of storer) from the time interval operational order ACT to operational order RD, clock period is 1.5ns, first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register every 2 clock period from subtracting, then can write numerical value 15ns/ (1.5ns*2)=5 in the temporal constraint register of correspondence.
After operational order sends, writing unit upgrades the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.Particularly, writing unit according to the type of the operational order sent to the confinement time interval of described first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register write to subsequent operation order.
In the present embodiment, after operational order ACT is sent completely, said write unit upgrades the value of following register:
Rank0_SameBank37_ACT2ACT；Rank0_SameBank37_ACT2RD；
Rank0_SameBank37_ACT2WE；Rank0_SameBank37_ACT2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2ACT；Rank0_DiffBank_ACT2RD；
Rank0_DiffBank_ACT2WE；Rank0_DiffBank_ACT2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_ACT2ACT；DiffRank_ACT2RD；
DiffRank_ACT2WE；DiffRank_ACT2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
Then, for operational order RD, it sends the Bank3 that target is Rank0, then the control module in arbitration unit 12 checks whether the value of following register is 0:
Rank0_SameBank37_ACT2RD；Rank0_SameBank37_RD2RD；
Rank0_SameBank37_WE2RD；Rank0_SameBank37_PRE2RD；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2RD；Rank0_DiffBank_RD2RD；
Rank0_DiffBank_WE2RD；Rank0_DiffBank_PRE2RD；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_ACT2RD；DiffRank_RD2RD；
DiffRank_WE2RD；DiffRank_PRE2RD。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
Similar with transmit operation order ACT, when control module checks that the value of above-mentioned first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register is 0, described arbitration unit 12 is arbitrated by described operational order ACT, and the memory access control device of described storer sends described operational order RD to described storer.If the value of above-mentioned register is not all 0, then above-mentioned register is simultaneously from subtracting, and such as each clock period is from subtracting 1; If the value of above-mentioned register is not that 0 (value of some register is 0 entirely, the value of some register is not 0), so, at following clock cycle, described request resolution unit continues to send this operational order RD, and described control module continues to check whether the value of above-mentioned register is 0, until the value of above-mentioned register is 0, described arbitration unit 12 is arbitrated by described operational order ACT, and the memory access control device of described storer sends described operational order RD to described storer.
After operational order RD is sent completely, said write unit upgrades the value of following register:
Rank0_SameBank37_RD2ACT；Rank0_SameBank37_RD2RD；
Rank0_SameBank37_RD2WE；Rank0_SameBank37_RD2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_RD2ACT；Rank0_DiffBank_RD2RD；
Rank0_DiffBank_RD2WE；Rank0_DiffBank_RD2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_RD2ACT；DiffRank_RD2RD；
DiffRank_RD2WE；DiffRank_RD2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
Finally, for operational order PRE, it sends the Bank3 that target is Rank0, then the control module in arbitration unit 12 checks whether the value of following register is 0:
Rank0_SameBank37_ACT2PRE；Rank0_SameBank37_RD2PRE；
Rank0_SameBank37_WE2PRE；Rank0_SameBank37_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_ACT2PRE；Rank0_DiffBank_RD2PRE；
Rank0_DiffBank_WE2PRE；Rank0_DiffBank_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_ACT2PRE；DiffRank_RD2PRE；
DiffRank_WE2PRE；DiffRank_PRE2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
Similarly, when control module checks that the value of above-mentioned first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register is 0, described arbitration unit 12 is arbitrated by described operational order ACT, and the memory access control device of described storer sends described operational order PRE to described storer.
After operational order PRE is sent completely, said write unit upgrades the value of following register:
Rank0_SameBank37_PRE2ACT；Rank0_SameBank37_PRE2RD；
Rank0_SameBank37_PRE2WE；Rank0_SameBank37_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the first temporal constraint register.
Rank0_DiffBank_PRE2ACT；Rank0_DiffBank_PRE2RD；
Rank0_DiffBank_PRE2WE；Rank0_DiffBank_PRE2PRE；
Above-mentioned four temporal constraint registers belong to the second temporal constraint register.
DiffRank_PRE2ACT；DiffRank_PRE2RD；
DiffRank_PRE2WE；DiffRank_PRE2PRE。
Above-mentioned four temporal constraint registers belong to the 3rd temporal constraint register.
So far, the operational order sequence A CT_RD_PRE that parsing module M03 sends all is sent to storer.
It will be appreciated by those skilled in the art that the process only exemplarily giving parsing module M03 transmit operation command sequence above, said process is equally applicable to parsing module M00-M02, M10-M13.Further, in the process of parsing module M03 transmit operation command sequence, other parsing modules, such as parsing module M00-M02, M10-M13, also can send other operational order sequences concurrently.Therefore, utilize the memory access control device of the storer of technical solution of the present invention can the multiple operational order sequence of transmitted in parallel, improve the memory access efficiency of storer.
It should be noted that register is from subtracting period, if subsequent operation order arrives temporal constraint register, as long as then have operational order by arbitration unit, writing unit just revises the value of corresponding temporal constraint register.
Illustrate, if parsing module M11 sends the first operational order sequence A CT_RD_PRE, the target of described first operational order sequence is the Bank5 of Bank1 or Rank1 of Rank1.Parsing module M12 sends the second operational order sequence A CT_RD_PRE, and the target of described second operational order sequence is the Bank6 of Bank2 or Rank1 of Rank1.
Operational order RD in described first operational order sequence is by being sent to storer after arbitration unit, and the writing unit in arbitration unit will upgrade the value of corresponding first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.Assuming that for the second temporal constraint register, the value of Rank1_DiffBank_RD2RD is updated to 10 by writing unit, the value of Rank1_DiffBank_RD2WE is updated to 20.Above-mentioned temporal constraint register carries out from subtracting in each clock period, therefore after 10 clock period, and the value of Rank1_DiffBank_RD2RD is the value of 0, Rank1_DiffBank_RD2WE is 10.
If the operational order RD now in the second operational order sequence arrives and passes through arbitration unit, then the writing unit in arbitration unit also will upgrade corresponding first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register.I.e. above-mentioned temporal constraint register Rank1_DiffBank_RD2RD, the value of Rank1_DiffBank_RD2WE is also updated, and the value of Rank1_DiffBank_RD2RD is updated to 10 by writing unit, and the value of Rank1_DiffBank_RD2WE is updated to 20.
That is, register is from subtracting period, as long as have operational order by arbitration unit, writing unit just revises the value of corresponding temporal constraint register.
In the present embodiment, in request analysis unit, each resolution unit comprises four parsing modules, and corresponding two Bank of each parsing module, the operational order that arbitration unit is sent by three groups of above-mentioned parsing modules of temporal constraint register pair is arbitrated.
In other embodiments, in resolution unit, the quantity of parsing module also can be not limited to four, such as resolution unit can comprise two parsing modules, corresponding four Bank of each parsing module, in this case, the operational order that arbitration unit still can be sent by three groups of above-mentioned parsing modules of temporal constraint register pair is arbitrated.With above-described embodiment unlike, in arbitration unit, the quantity of the first temporal constraint register, the second temporal constraint register and/or the 3rd temporal constraint register can correspondingly change.Such as, if the resolution unit of corresponding Rank0 comprises two parsing modules, one of them parsing module corresponding Bank0, Bank1, Bank2, Bank3, another parsing module corresponding Bank4, Bank5, Bank6, Bank7.With reference to figure 4, for the first temporal constraint register, as long as change the first temporal constraint register corresponding to Rank0_SameBank04, Rank0_SameBank15, Rank0_SameBank26 and Rank0_SameBank37 into the first temporal constraint register corresponding to Rank0_SameBank0123 and Rank0_SameBank4567, each first temporal constraint register indoor design and principle of work constant, only change original four groups of temporal constraint registers into present two groups of temporal constraint registers.
It should be noted that, existing in specifying in the standard of SDRAM that each Rank comprises 8 Bank, but each Rank that the application of technical solution of the present invention is not limited to above-mentioned correlation standard comprises 8 Bank situations, such as, if each Rank comprises 16 Bank, then the incidence relation adjusting parsing module and Bank in resolution unit can also realize technique effect of the present invention.
With reference to figure 5, another embodiment of the memory access control device 10A of storer of the present invention comprises request analysis unit 11 and arbitration unit 12A.
Request analysis unit 11, for access request is resolved to operational order sequence, described operational order sequence comprises some operational orders.
Arbitration unit 12A, for arbitrating the operational order in described operational order sequence by referee conditions, so that operational order is sent to described storer, described referee conditions comprises: the time interval that operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint.
Described first temporal constraint refers to the time interval requirement between the operational order of the same memory bank of access (Bank); Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access (Rank); Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group.
In the present embodiment, arbitration unit 12A comprises:
First temporal constraint judging unit 121, for judging whether the time interval of the transmitting time of current time and last operational order meets the first temporal constraint between current operational order and last operational order, and described current operational order and described last operational order belong to same operational order sequence.
Second temporal constraint judging unit 122, whether the time interval for the transmitting time judging described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order.
3rd temporal constraint judging unit 123, whether the time interval for the transmitting time judging described current time and described last operational order meets the 3rd temporal constraint between described current operational order and described last operational order.
Transmitting element 124, for when the judged result of the judged result of described first temporal constraint judging unit, the judged result of the second temporal constraint judging unit and the 3rd sequential judging unit is being, to the described current operational order of described storer transmission.
It will be appreciated by those skilled in the art that, the all or part of of technique scheme is that the hardware that can carry out instruction relevant by program has come, described program can be stored in computer-readable recording medium, and described storage medium can be ROM, RAM, magnetic disc, CD etc.
Described access request comprises read request, write request or reads-amendment-write request.Described operational order is activation command (ACT), read command (RD), write order (WE) or write back order (PRE).
If described access request is read request, described access request is resolved to operational order sequence A CT_RD_PRE by described resolution unit.
If described access request is write request, described access request is resolved to operational order sequence A CT_WE_PRE by described resolution unit.
If described access request is for reading-amendment-write request, described access request can be resolved to operational order sequence A CT_RD_WE_PRE by described resolution unit, also described access request can be resolved to operational order sequence A CT_RD_PRE and ACT_WE_PRE.
The process that access request is resolved to operational order sequence by resolution unit 11 please refer to previous embodiment, and this does not repeat.
It should be noted that the control device of the storer of technical solution of the present invention can be integrated in north bridge chips, also can be integrated in processor (such as CPU).If the control device of this storer is integrated in north bridge chips, then can think that user's access request is sent in the control device of this storer by processor (such as CPU); If the control device of storer is integrated in processor (such as CPU), then can think that access request is sent to the control device of this storer by the module such as internet, transfer bus on the sheet of processor inside.
The memory access control device of corresponding above-mentioned storer, technical solution of the present invention also provides a kind of access control method of storer.Consult Fig. 6, the access control method of described storer comprises:
S1: access request is resolved to operational order sequence, described operational order sequence comprises some operational orders.
S2: the operational order in described operational order sequence is arbitrated by referee conditions, so that operational order is sent to storer, described referee conditions comprises: the time interval that described operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint.
Described first temporal constraint refers to the time interval requirement between the operational order of the same memory bank of access (Bank); Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access (Rank); Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group.
Described access request comprises read request, write request or reads-amendment-write request.Described operational order is activation command (ACT), read command (RD), write order (WE) or write back order (PRE).
If described access request is read request, described access request is resolved to operational order sequence A CT_RD_PRE by described resolution unit.
If described access request is write request, described access request is resolved to operational order sequence A CT_WE_PRE by described resolution unit.
If described access request is for reading-amendment-write request, described access request can be resolved to operational order sequence A CT_RD_WE_PRE by described resolution unit, also described access request can be resolved to operational order sequence A CT_RD_PRE and ACT_WE_PRE.
In one embodiment, by referee conditions, the operational order in described operational order sequence is arbitrated described in step S2, comprises so that operational order is sent to storer:
When after transmit operation order, to corresponding to the first temporal constraint register of the type of operational order sent, the second temporal constraint register and the 3rd temporal constraint register write numerical value, the time interval requirement of numerical associations between the clock period and operational order of described storer of said write; The numerical value of each temporal constraint register based on clock period of described storer from the numerical value of write from reducing to 0.
When corresponding to the type of operational order that do not send and specifying the numerical value of the first temporal constraint register of the memory bank in the set of memory banks of access, be 0 corresponding to the type of the described operational order do not sent and the numerical value of the 3rd temporal constraint register of type of specifying the numerical value of the second temporal constraint register of the set of memory banks of access and corresponding to the described operational order do not sent thereof, the operational order do not sent described in transmission is to described storer.
The quantity of described first temporal constraint register associates with the quantity m of the memory bank in set of memory banks with the quantity c of the type of operational order, the quantity n of set of memory banks.
The quantity of described second temporal constraint register associates with the quantity n of set of memory banks with the quantity c of the type of operational order.
The quantity of described 3rd temporal constraint register associates with the quantity c of the type of operational order.
In the present embodiment, the quantity of described first temporal constraint register can be
the quantity of described second temporal constraint register can be n × c
2; The quantity of described 3rd temporal constraint register can be c
2.
In another embodiment, by referee conditions, the operational order in described operational order sequence is arbitrated described in step S2, comprises so that operational order is sent to storer:
Judge whether the time interval of the transmitting time of current time and last operational order meets the first temporal constraint between current operational order and last operational order, and described current operational order and described last operational order belong to same operational order sequence.
Judge whether the time interval of the transmitting time of described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order.
Judge whether the time interval of the transmitting time of described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order.
When above-mentioned judged result be, send described current operational order to described storer.
Technical solution of the present invention also provides a kind of processor, comprises the memory access control device of above-mentioned storer.Access request is sent to the memory access control device of described storer by the module such as internet, transfer bus on the sheet of described processor inside.Access request is resolved to operational order sequence with the memory access control device of described storer and the process being sent to storer please refer to above-described embodiment, and this does not repeat.
Technical solution of the present invention also provides a kind of north bridge chips, comprises the memory access control device of above-mentioned storer.Access request is sent to the memory access control device of the described storer be integrated in described north bridge chips by processor (such as CPU).Access request is resolved to operational order sequence with the memory access control device of described storer and the process being sent to storer please refer to above-described embodiment, and this does not repeat.
The memory access control device of the storer that the embodiment of the present invention proposes substantially increases memory bandwidth when obviously not increasing hardware spending, decreases memory access latency.Specifically:
Adopt the commercial chip of " body walk abreast memory access strategy " to only considered temporal constraint situation between memory bank (Bank) in prior art, and do not consider the temporal constraint situation between memory set (Rank).Realizing existing " body walk abreast memory access strategy " needs the register number used to be: 128+16=144.
The memory access control device of the storer that the embodiment of the present invention proposes both had considered the temporal constraint situation between memory bank (Bank), consider again the temporal constraint situation between set of memory banks (Rank), achieve and the multidimensional of storer is walked abreast memory access.The register number that technical solution of the present invention uses is the quantity sum of the first temporal constraint register, the second temporal constraint register and the 3rd temporal constraint register, that is: 128+32+16=176.Therefore, the hardware costs of technical solution of the present invention increase only (176-144)/144=22.2%, but fully can excavate the parallel memory access ability between set of memory banks (Rank).
In sum, relative to prior art, technical solution of the present invention is by request analysis unit transmit operation command sequence concurrently, and utilize the first temporal constraint, the second temporal constraint and the 3rd temporal constraint to control to send time interval between current operation order in same operational order sequence and the last operational order adjacent with described current operation order, not only can the multiple memory bank of concurrent access (Bank), and can the multiple set of memory banks of concurrent access (Rank), achieve multidimensional and to walk abreast memory access.Experiment proves, technical solution of the present invention significantly can shorten the average handling time of access request, improves entire system memory access performance.In addition, relative to the traditional controller of existing employing " body walk abreast memory access strategy ", technical solution of the present invention does not also obviously increase realization price of hardware.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (19)
1. a memory access control device for storer, is characterized in that, comprising:
Request analysis unit, for access request is resolved to operational order sequence, described operational order sequence comprises some operational orders;
Arbitration unit, for arbitrating the operational order in described operational order sequence by referee conditions, so that operational order is sent to described storer, described referee conditions comprises: the time interval that operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint;
Described first temporal constraint refers to the time interval requirement between the operational order of accessing same memory bank; Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access; Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group;
Wherein, described arbitration unit comprises:
First temporal constraint register, its quantity associates with the quantity m of the memory bank in set of memory banks with the quantity c of the type of operational order, the quantity n of set of memory banks;
Second temporal constraint register, its quantity associates with the quantity n of set of memory banks with the quantity c of the type of operational order;
3rd temporal constraint register, its quantity associates with the quantity c of the type of operational order;
Writing unit, for when after transmit operation order, to corresponding to the first temporal constraint register of the type of operational order sent, the second temporal constraint register and the 3rd temporal constraint register write numerical value, the time interval requirement of numerical associations between the clock period and operational order of described storer of said write;
The numerical value of each temporal constraint register based on clock period of described storer from the numerical value of write from reducing to 0;
Control module, for when corresponding to the type of operational order that do not send and specifying the numerical value of the first temporal constraint register of the memory bank in the set of memory banks of access, be 0 corresponding to the type of the described operational order do not sent and the numerical value of the 3rd temporal constraint register of type of specifying the numerical value of the second temporal constraint register of the set of memory banks of access and corresponding to the described operational order do not sent thereof, the operational order do not sent described in transmission is to described storer.
2. the memory access control device of storer according to claim 1, is characterized in that, described request resolution unit comprises the resolution unit that two are associated with described set of memory banks, and each resolution unit comprises some parsing modules being associated with described memory bank.
3. the memory access control device of storer according to claim 1, is characterized in that,
The quantity of described first temporal constraint register is
The quantity of described second temporal constraint register is n × c
2;
The quantity of described 3rd temporal constraint register is c
2.
4. the memory access control device of storer according to claim 1, is characterized in that, described arbitration unit comprises:
First temporal constraint judging unit, for judging whether the time interval of the transmitting time of current time and last operational order meets the first temporal constraint between current operational order and last operational order, and described current operational order and described last operational order belong to same operational order sequence;
Second temporal constraint judging unit, whether the time interval for the transmitting time judging described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order;
3rd temporal constraint judging unit, whether the time interval for the transmitting time judging described current time and described last operational order meets the 3rd temporal constraint between described current operational order and described last operational order;
Transmitting element, for when the judged result of the judged result of described first temporal constraint judging unit, the judged result of the second temporal constraint judging unit and the 3rd sequential judging unit is being, to the described current operational order of described storer transmission.
5. the memory access control device of storer according to claim 1, is characterized in that,
Described access request is read request, write request or reads-amendment-write request.
6. the memory access control device of storer according to claim 1, is characterized in that, described operational order is activation command, read command, write order or writes back order.
7. the memory access control device of storer according to claim 1, is characterized in that, described access request is read request, and described operational order sequence is activation command _ read command _ write back order.
8. the memory access control device of storer according to claim 1, is characterized in that, described access request is write request, and described operational order sequence is activation command _ write order _ write back order.
9. the memory access control device of storer according to claim 1, is characterized in that, described access request is for reading-amendment-write request, and described operational order sequence is activation command _ read command _ write order _ write back order; Or described operational order sequence comprises activation command _ read command _ write back order and activation command _ write order _ write back order.
10. an access control method for storer, is characterized in that, comprising:
Access request is resolved to operational order sequence, described operational order sequence comprises some operational orders;
By referee conditions, the operational order in described operational order sequence is arbitrated, so that operational order is sent to storer, described referee conditions comprises: the time interval that described operational order is sent to described storer meets the first temporal constraint, the second temporal constraint and the 3rd temporal constraint;
Described first temporal constraint refers to the time interval requirement between the operational order of accessing same memory bank; Described second temporal constraint refers to the time interval requirement between the operational order of different bank in the same set of memory banks of access; Described 3rd temporal constraint refers to the time interval requirement between the operational order of access different bank group;
Wherein, describedly by referee conditions, the operational order in described operational order sequence to be arbitrated, comprises so that operational order is sent to storer:
When after transmit operation order, to corresponding to the first temporal constraint register of the type of operational order sent, the second temporal constraint register and the 3rd temporal constraint register write numerical value, the time interval requirement of numerical associations between the clock period and operational order of described storer of said write;
The numerical value of each temporal constraint register based on clock period of described storer from the numerical value of write from reducing to 0;
When corresponding to the type of operational order that do not send and specifying the numerical value of the first temporal constraint register of the memory bank in the set of memory banks of access, be 0 corresponding to the type of the described operational order do not sent and the numerical value of the 3rd temporal constraint register of type of specifying the numerical value of the second temporal constraint register of the set of memory banks of access and corresponding to the described operational order do not sent thereof, the operational order do not sent described in transmission is to described storer;
The quantity of described first temporal constraint register associates with the quantity m of the memory bank in set of memory banks with the quantity c of the type of operational order, the quantity n of set of memory banks;
The quantity of described second temporal constraint register associates with the quantity n of set of memory banks with the quantity c of the type of operational order;
The quantity of described 3rd temporal constraint register associates with the quantity c of the type of operational order.
The access control method of 11. storeies according to claim 10, is characterized in that,
The quantity of described first temporal constraint register is
The quantity of described second temporal constraint register is n × c
2;
The quantity of described 3rd temporal constraint register is c
2.
The access control method of 12. storeies according to claim 10, is characterized in that, describedly arbitrates the operational order in described operational order sequence by referee conditions, comprises so that operational order is sent to storer:
Judge whether the time interval of the transmitting time of current time and last operational order meets the first temporal constraint between current operational order and last operational order, and described current operational order and described last operational order belong to same operational order sequence;
Judge whether the time interval of the transmitting time of described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order;
Judge whether the time interval of the transmitting time of described current time and described last operational order meets the second temporal constraint between described current operational order and described last operational order;
When above-mentioned judged result be, send described current operational order to described storer.
The access control method of 13. storeies according to claim 10, is characterized in that, described access request is read request, write request or reads-amendment-write request.
The access control method of 14. storeies according to claim 10, is characterized in that, described operational order is activation command, read command, write order or writes back order.
The access control method of 15. storeies according to claim 10, is characterized in that, described access request is read request, and described operational order sequence is activation command _ read command _ write back order.
The access control method of 16. storeies according to claim 10, is characterized in that, described access request is write request, and described operational order sequence is activation command _ write order _ write back order.
The access control method of 17. storeies according to claim 10, is characterized in that, described access request is for reading-amendment-write request, and described operational order sequence is activation command _ read command _ write order _ write back order; Or described operational order sequence comprises activation command _ read command _ write back order and activation command _ write order _ write back order.
18. 1 kinds of processors, is characterized in that, comprise the memory access control device of the storer according to any one of claim 1 to 9.
19. 1 kinds of north bridge chips, is characterized in that, comprise the memory access control device of the storer according to any one of claim 1 to 9.
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| CN106168932B (en) * | 2016-06-29 | 2020-12-18 | 联想(北京)有限公司 | Flash control method and device |
| CN106547707B (en) * | 2016-09-21 | 2019-03-05 | 西安邮电大学 | Concurrent access Local Priority switched circuit is stored in array processor in cluster |
| CN107450862A (en) * | 2017-08-18 | 2017-12-08 | 郑州云海信息技术有限公司 | A kind of referee method of solid state hard disc read operation |
| CN108829348B (en) * | 2018-05-29 | 2022-03-04 | 上海兆芯集成电路有限公司 | Memory device and command reordering method |
| CN110727401B (en) * | 2019-09-09 | 2021-03-02 | 无锡江南计算技术研究所 | Memory access system |
| CN112466361B (en) * | 2020-11-25 | 2023-11-21 | 海光信息技术股份有限公司 | DIMM data initialization method, device, system and equipment |
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