CN103368663A - Debugging and test method and system for radio frequency remote base station - Google Patents
Debugging and test method and system for radio frequency remote base station Download PDFInfo
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Abstract
The invention provides a debugging and test method and system. An optical interface is used to transmit and receive debugging data between the optical interface and a board card which is to be debugged and tested; through a control of time of transmitting and receiving, a BBU (base band unit) function is simulated to provide a data source to a RRU (remote RF unit) and to collect data of the RRU, and a RRU function is simulated to provide the data source to the BBU and collects the data of the BBU; and the BBU and the RRU can be debugged under a condition of a single board, and can be debugged under a condition of a whole machine. The flexibility is good, the operationality is great; and the extra interface cooperation is not required under the condition of the whole machine.
Description
Technical Field
The present invention relates to the field of mobile communications, and in particular, to a method and a system for debugging and testing a radio remote base station.
Background
Base stations of an existing LTE (Long term Evolution) system and TD-SCDMA (time Division-Synchronous Code Division Multiple Access) system mostly adopt a distributed structure, and a distributed Base station refers to a Base Band Unit (BBU) and a Remote Radio Unit (RRU) of a Base station, which are separately placed as independent modules and connected by an optical fiber through an optical interface. The distributed base station system has the advantages of large capacity, high integration level, flexible networking, applicability to various coverage scenes, low power consumption, high reliability and low equipment cost, thereby greatly reducing the network sputtering and maintenance cost.
In a mobile communication system, under the influence of objective factors such as cost, power consumption and networking flexibility, the system has higher and higher requirements on the processing capability of a base station single board, and often the base station single board is required to complete data processing of multiple cells and multiple antennas, and also has high requirements on the resource utilization rate, the integration level and the like of the base station single board. Especially in the current TD and LTE systems, because of the radio remote technology, the BBU and the RRU are separated, and the BBU and the RRU are connected by optical fiber, the difficulty of testing the base station is increased. Therefore, how to perform a test to ensure the correctness of the functions of the BBU and the RRU under the condition that the resource utilization rate of the base station board is high has become one of the problems that need to be solved at present.
In the existing test method for the single board of the base station, on the premise of not increasing a peripheral test device, a certain test method is added in the BBU and the RRU by using an embedded application program through a software program to test and verify the correctness of the BBU and the RRU. Therefore, this method can be used only for simple tests, and cannot satisfy tests that require a large amount of data for analysis.
In the prior art, special equipment is also usually adopted to achieve certain RRU data acquisition and testing, for example, special test equipment simulating BBU is used to respectively test whether uplink and downlink physical channels of RRU are normal. The method for testing the uplink channel comprises the steps of inputting data of a signal source through an antenna port, transmitting the data to analog BBU equipment through optical fibers after passing through each submodule of the RRU, analyzing the data by the analog BBU, and judging whether the uplink channel is normal or not according to an analysis result; the method for testing the downlink access comprises the steps that downlink data are sent by the analog BBU and transmitted to the RRU after passing through the optical fiber, the RRU sends the data to the antenna port through the downlink access, the output of the antenna port is measured through an instrument, and whether the downlink access is normal or not is judged according to a test structure. However, although the dedicated device can test the uplink and downlink channels of the RRU at the same time, it cannot acquire uplink data of the RRU and cannot test the BBU, and furthermore, it is difficult to connect the RRU to be tested in the whole environment by using the dedicated BBU simulation test device due to the limitation of conditions such as hardware environment, and the like, and the test can be performed only in the single board environment, and if the test is performed in the whole environment, additional interface cooperation needs to be added, so that the existing test device and method are lack of flexibility.
Disclosure of Invention
In view of the defects of the prior art, the invention provides a testing method and a testing device for a radio remote base station, and solves the problems that in the prior art, additional interface matching is required for testing in a complete machine environment, RRU uplink data cannot be acquired, and BBU cannot be tested.
The technical means adopted by the invention are as follows: a test adjusting device for a radio remote base station comprises a test adjusting board card and a control PC; wherein,
the debugging and testing board card comprises a CPU, an FPGA, a memory module and an optical module;
the CPU is used for receiving debugging or testing instructions of the control PC and sending corresponding configuration information including the receiving and sending moments to the FPGA;
the FPGA comprises a configuration module, an Ethernet processing module, an optical interface processing module, a control module and other functional modules; the configuration module is used for receiving configuration information of the CPU and configuring the configuration information; the Ethernet processing module is used for receiving a debugging data packet sent by the control PC, extracting debugging data of the debugging data packet, or splitting and packaging acquired test data into test data packets and then sending the test data packets to the control PC; the optical interface processing module is used for receiving test data of the board card interface to be tested through the optical module at the transceiving time, or reading debugging data through the control module and sending the debugging data to the optical module; the control module is used for scheduling each module in the FPGA to work;
the optical module is connected with the BBU and the RRU through optical fibers and used for converting photoelectric signals and realizing data interaction between the debugging test board card and the to-be-debugged test board card;
the memory module is used for caching the debugging data or the test data;
the control PC is used for sending debugging or testing instructions to the CPU of the debugging and testing board card, controlling the reading operation of a local debugging data file, splitting the local debugging data file into a plurality of continuous debugging data packets, sending the multiple continuous debugging data packets to the debugging and testing board card, receiving the testing data packets which are collected and packaged by the debugging and testing board card and output, and storing the testing data packets in the local testing data file.
Further, the configuration information includes, in addition to the transmission and reception time, the MAC address, the IP address, the port number of the control PC, and the size of the transmission and reception data amount.
Further, the optical interface processing module is further configured to repeatedly read debug data according to the size of the transmission data volume; the optical interface processing module is also used for receiving the test data according to the size of the received data volume.
Further, the CPU is further configured to configure an RRU transceiving time of the FPGA when the BBU board is debugged, and configure a BBU transceiving time of the FPGA when the RRU board is debugged.
Further, the interface of the board card to be debugged is an IR interface, and the debug data packet and the test data packet are UDP data packets.
The invention also provides a debugging and testing method based on the debugging and testing device, which comprises a debugging step and a testing step, wherein,
the debugging step comprises the following steps:
the control PC sends a debugging instruction to a CPU of the debugging and testing board card, reads a local debugging data file at the same time, splits the debugging data file into a plurality of continuous debugging data packets and sends the debugging data packets to the FPGA;
the CPU sends corresponding configuration information containing sending time to the FPGA according to the debugging instruction;
the configuration module of the FPGA receives the configuration information of the CPU and performs configuration, and the Ethernet processing module of the FPGA receives the debugging data packet, extracts the debugging data of the debugging data packet and writes the debugging data into the memory module;
the optical interface processing module reads the debugging data at the sending time and sends the debugging data to the optical module;
the optical module performs photoelectric signal conversion on the debugging data and then sends the debugging data to a board card to be debugged;
the testing step comprises:
the control PC sends a test instruction to a CPU of the debugging test board card;
the CPU sends corresponding configuration information containing receiving time to the FPGA according to the test instruction;
the configuration module of the FPGA receives the configuration information of the CPU and configures the configuration information;
the optical interface processing module receives data of the board card interface to be tested through the optical module at the receiving moment to form test data, and stores the test data in the memory module;
the Ethernet processing module reads the test data, packs the test data to form a test data packet and sends the test data packet to the control PC;
and the control PC receives the test data packet and stores the test data packet in a local test data file.
Further, in the debugging step, the configuration information includes, in addition to the sending time, the MAC address, the IP address, the port number, and the size of the sending data amount of the control PC;
in the testing step, the configuration information includes, in addition to the receiving time, the MAC address, the IP address, the port number, and the size of the received data amount of the control PC.
Further, in the debugging step, the optical interface processing module repeatedly reads the debugging data according to the size of the transmission data volume at the transmission time and transmits the debugging data to the optical module;
in the testing step, the optical interface processing module receives test data according to the size of the received data volume.
Further, the RRU receiving and sending time of the FPGA is configured when the BBU board card is tested, and the BBU receiving and sending time of the FPGA is configured when the RRU board card is tested.
Further, the board card interface to be tested is an IR interface, and the debug data packet and the test data packet are UDP data packets.
The debugging and testing method and the debugging and testing device provided by the invention have the advantages that the optical interface is adopted to send and receive debugging data with the board card to be debugged, and the transceiving time is controlled, so that the simulation of the BBU function can be realized, a data source is provided for the RRU, the data of the RRU is acquired, the simulation of the RRU function can also be realized, the data source is provided for the BBU, and the data of the BBU is acquired, the BBU and the RRU can be debugged in a single board environment, the debugging can also be realized in a complete machine environment, the flexibility is good, the operability is strong, and no additional interface matching is needed in the complete.
Drawings
Fig. 1 is a schematic structural diagram of a test adjusting apparatus for a remote radio base station according to the present invention;
FIG. 2 is a flowchart illustrating debugging steps in a debugging and testing method according to the present invention;
FIG. 3 is a flowchart illustrating testing steps in a debugging and testing method according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples.
Fig. 1 illustrates a debugging and testing apparatus for a radio remote base station according to the present invention, which includes a debugging board card and a control PC; wherein,
the debugging and testing board card comprises a CPU, an FPGA, a memory module and an optical module;
the CPU is used for receiving a debugging or testing instruction of the control PC and sending corresponding configuration information including the sending and receiving time to the FPGA, and is also used for configuring the RRU sending and receiving time of the FPGA when the BBU board card is debugged and tested and configuring the BBU sending and receiving time of the FPGA when the RRU board card is debugged and tested; the configuration information comprises the receiving and sending time, the MAC address, the IP address and the port number of the control PC and the size of the sending and receiving data volume;
the FPGA comprises a configuration module, an Ethernet processing module, an optical interface processing module, a control module and other functional modules; the configuration module is used for receiving configuration information of the CPU and configuring the configuration information; the Ethernet processing module is used for receiving a debugging data packet sent by the control PC, extracting debugging data of the debugging data packet, or splitting and packaging acquired test data into a test data packet (such as UDP data) and then sending the test data packet to the control PC; the optical interface processing module is used for receiving test data of the board card interface to be tested, such as an IR interface, through the optical module at the transceiving moment, or reading debugging data through the control module and sending the debugging data to the optical module, and the optical interface processing module can repeatedly read the debugging data according to the size of the sending data volume, or receive the test data according to the size of the receiving data volume; the control module is used for scheduling each module in the FPGA to work;
the optical module is connected with the BBU and the RRU through optical fibers and used for converting photoelectric signals and realizing data interaction between the debugging test board card and the to-be-debugged test board card;
the memory module is used for caching the debugging data or the test data;
the control PC is used for sending debugging or testing instructions to the CPU of the debugging and testing board card, controlling the reading operation of a local debugging data file, splitting the local debugging data file into a plurality of continuous debugging data packets, such as UDP data packets, then sending the debugging and testing board card to the control and testing board card, receiving the testing data packets which are collected and packaged by the debugging and testing board card and then output, and storing the testing data packets in the local testing data file.
The invention also provides a debugging and testing method, which comprises a debugging step and a testing step, wherein the debugging step is shown in figure 2 and comprises the following steps:
the control PC sends a debugging instruction to a CPU of the debugging and testing board card, reads a local debugging data file at the same time, splits the debugging data file into a plurality of continuous debugging data packets and sends the debugging data packets to the FPGA;
the CPU sends corresponding configuration information containing sending time to the FPGA according to the debugging instruction, wherein the configuration information comprises the sending time, an MAC address, an IP address, a port number and the size of sending data volume of the control PC;
the configuration module of the FPGA receives the configuration information of the CPU and performs configuration, and the Ethernet processing module of the FPGA receives the debugging data packet, extracts the debugging data of the debugging data packet and writes the debugging data into the memory module;
the optical interface processing module repeatedly reads the debugging data according to the size of the transmitted data volume at the transmitting moment and transmits the debugging data to the optical module;
the optical module performs photoelectric signal conversion on the debugging data and then sends the debugging data to a board card to be debugged;
the testing steps are shown in fig. 3 and include:
the control PC sends a test instruction to a CPU of the debugging test board card;
the CPU sends corresponding configuration information containing receiving time to the FPGA according to the test instruction, wherein the configuration information comprises the receiving time, an MAC address, an IP address, a port number and the size of received data volume of the control PC;
the configuration module of the FPGA receives the configuration information of the CPU and configures;
the optical interface processing module receives data of a board card interface to be tested through an optical module at the receiving moment, receives test data according to the size of the received data volume to form test data, and stores the test data in the memory module;
the Ethernet processing module reads the test data, packs the test data to form a test data packet and sends the test data packet to the control PC;
and the control PC receives the test data packet and stores the test data packet in a local test data file.
In the debugging step and the testing step, the CPU configures RRU receiving and sending time of the FPGA, and configures BBU receiving and sending time of the FPGA when the RRU board card is debugged and tested.
In the invention, the optical interface is adopted to transmit and receive debugging data with the test board card to be debugged, and the transceiving time is controlled, so that the functions of simulating the BBU can be realized to provide a data source for the RRU and collect the data of the RRU, and the functions of simulating the RRU can be realized to provide the data source for the BBU and collect the data of the BBU.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A debugging and testing device for a radio remote base station is characterized by comprising a debugging and testing board card and a control PC; wherein,
the debugging and testing board card comprises a CPU, an FPGA, a memory module and an optical module;
the CPU is used for receiving debugging or testing instructions of the control PC and sending corresponding configuration information including the receiving and sending moments to the FPGA;
the FPGA comprises a configuration module, an Ethernet processing module, an optical interface processing module, a control module and other functional modules; the configuration module is used for receiving configuration information of the CPU and configuring the configuration information; the Ethernet processing module is used for receiving a debugging data packet sent by the control PC, extracting debugging data of the debugging data packet, or splitting and packaging acquired test data into test data packets and then sending the test data packets to the control PC; the optical interface processing module is used for receiving test data of the board card interface to be tested through the optical module at the transceiving time, or reading debugging data through the control module and sending the debugging data to the optical module; the control module is used for scheduling each module in the FPGA to work;
the optical module is connected with the BBU and the RRU through optical fibers and used for converting photoelectric signals and realizing data interaction between the debugging test board card and the to-be-debugged test board card;
the memory module is used for caching the debugging data or the test data;
the control PC is used for sending debugging or testing instructions to the CPU of the debugging and testing board card, controlling the reading operation of a local debugging data file, splitting the local debugging data file into a plurality of continuous debugging data packets, sending the multiple continuous debugging data packets to the debugging and testing board card, receiving the testing data packets which are collected and packaged by the debugging and testing board card and output, and storing the testing data packets in the local testing data file.
2. The commissioning apparatus of claim 1, wherein the configuration information includes, in addition to the transceiving time, a MAC address, an IP address, a port number of the control PC, and a size of a transmission and reception data amount.
3. The debug device of claim 2, wherein said optical interface processing module is further configured to repeatedly read debug data according to the size of said transmitted data amount; the optical interface processing module is also used for receiving the test data according to the size of the received data volume.
4. The debugging and testing device according to claim 3, wherein said CPU is further configured to configure the RRU transceiving time of the FPGA when debugging and testing the BBU board, and configure the BBU transceiving time of the FPGA when debugging and testing the RRU board.
5. The debug device of claim 1, wherein said board interface to be debugged is an IR interface, and said debug packets and said test packets are UDP packets.
6. A debug method based on the debug apparatus as claimed in claims 1 to 5, comprising a debug step and a test step, wherein,
the debugging step comprises the following steps:
the control PC sends a debugging instruction to a CPU of the debugging and testing board card, reads a local debugging data file at the same time, splits the debugging data file into a plurality of continuous debugging data packets and sends the debugging data packets to the FPGA;
the CPU sends corresponding configuration information containing sending time to the FPGA according to the debugging instruction;
the configuration module of the FPGA receives the configuration information of the CPU and performs configuration, and the Ethernet processing module of the FPGA receives the debugging data packet, extracts the debugging data of the debugging data packet and writes the debugging data into the memory module;
the optical interface processing module reads the debugging data at the sending time and sends the debugging data to the optical module;
the optical module performs photoelectric signal conversion on the debugging data and then sends the debugging data to a board card to be debugged;
the testing step comprises:
the control PC sends a test instruction to a CPU of the debugging test board card;
the CPU sends corresponding configuration information containing receiving time to the FPGA according to the test instruction;
the configuration module of the FPGA receives the configuration information of the CPU and configures the configuration information;
the optical interface processing module receives data of the board card interface to be tested through the optical module at the receiving moment to form test data, and stores the test data in the memory module;
the Ethernet processing module reads the test data, packs the test data to form a test data packet and sends the test data packet to the control PC;
and the control PC receives the test data packet and stores the test data packet in a local test data file.
7. The method according to claim 6, wherein in the debugging step, the configuration information includes, in addition to the transmission time, a MAC address, an IP address, a port number, and a size of transmission data amount of the control PC;
in the testing step, the configuration information includes, in addition to the receiving time, the MAC address, the IP address, the port number, and the size of the received data amount of the control PC.
8. The method according to claim 7, wherein in the debugging step, the optical interface processing module repeatedly reads the debugging data according to the size of the transmission data amount at the transmission time and transmits the debugging data to the optical module;
in the testing step, the optical interface processing module receives test data according to the size of the received data volume.
9. The method of claim 8, wherein the CPU configures RRU transceiving time of the FPGA when testing the BBU board, and configures BBU transceiving time of the FPGA when testing the RRU board.
10. The method of claim 1, wherein the board interface to be tested is an IR interface, and the debug data packets and the test data packets are UDP data packets.
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| CN107423027A (en) * | 2017-07-24 | 2017-12-01 | 杭州迪普科技股份有限公司 | A kind of information-reading method of optical module, device and system |
| CN107453823A (en) * | 2017-07-31 | 2017-12-08 | 武汉虹信通信技术有限责任公司 | The monomer test system and method for a kind of optical fiber distributed type repeater |
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| CN113726456B (en) * | 2020-05-26 | 2023-05-05 | 大唐移动通信设备有限公司 | Detection method of remote radio unit and remote radio unit |
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