CN103367339A - Chip-packaging method and chip-packaging structure - Google Patents
Chip-packaging method and chip-packaging structure Download PDFInfo
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- CN103367339A CN103367339A CN2012100812486A CN201210081248A CN103367339A CN 103367339 A CN103367339 A CN 103367339A CN 2012100812486 A CN2012100812486 A CN 2012100812486A CN 201210081248 A CN201210081248 A CN 201210081248A CN 103367339 A CN103367339 A CN 103367339A
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- film
- chip
- packaging
- conducting layer
- packing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Abstract
The invention provides a chip-packaging method which comprises the following steps of: sequentially overlaying a first film, a plurality of chips and a second film, and solidifying the first film and the second film in a manner of press fit to form a packaging body, and embedding the plurality of chips into the packaging body, wherein each of the plurality of chips is provided with a plurality of pins which are far from the first film; forming blind holes in one-to-one correspondence to the pins from the surface, which is far from the first film, of the second film to the interior of the second film, wherein each of the pins is exposed out from the corresponding blind hole; forming conductive layers electrically communicated with the corresponding pins on the inner walls of the blind holes; forming a metal block electrically communicated with the conductive layer of the corresponding blind hole on each blind hole and thereby forming a packaging substrate; cutting the packaging substrate to form a plurality of packaging structures, each of which comprises a chip. The invention also relates to a chip-packaging structure.
Description
Technical field
The present invention relates to a kind of chip encapsulation technology, particularly a kind of chip packaging method and the chip-packaging structure that adopts the method to obtain.
Background technology
Encapsulation also can be described as and refers to install the shell that semiconductor integrated circuit chip is used; it is not only served as placement, fixes, seals, protects the effect of chip and increased thermal conductivity energy; but also be link up the chip internal world and external circuit bridge--the contact on the chip is wired to the wire of package casing, these wires connect through wire and other part on the printed circuit board (PCB) again.Therefore, for a lot of integrated circuit (IC) products, encapsulation technology all is unusual the key link.
Summary of the invention
The invention provides a kind of method for packing and chip-packaging structure of chip, the method for packing technique of described chip is simple, easily operation.
A kind of method for packing of chip comprises step: a plurality of chips, the first film and the second film are provided, and each described chip all has relative first surface and second surface, all has a plurality of pins on the first surface of each described chip; Described a plurality of chips are fixed on described the first film so that the second surface of each chip contacts with the first film, and so that described a plurality of pin away from described the first film; Described the second film is positioned over formation one superimposed sheet on described a plurality of chip, and described the second film has the 3rd surface away from described the first film; The described superimposed sheet of pressing makes described the first film and described the second film solidify to form a packaging body, and described a plurality of chips are embedded in the described packaging body; Form and each pin blind hole one to one to the second film is inner from the 3rd surface of the second film, each pin all exposes from the blind hole of correspondence; Form metal conducting layer with corresponding pin electric connection at the inwall of each blind hole; At the metal derby of metal conducting layer formation with the metal conducting layer electric connection, thereby form base plate for packaging; And cut described base plate for packaging, to form a plurality of encapsulating structures that respectively include a chip.
A kind of chip-packaging structure, comprise a packaging body, described packaging body has relative first surface and second surface, be embedded with a chip in the described packaging body, be provided with a plurality of pins on the described chip, described a plurality of pin is away from described second surface, inside from from described first surface to described packaging body is formed with and described a plurality of pins blind hole one to one, the hole wall of described blind hole is provided with the metal conducting layer with corresponding pin electric connection, be formed with the metal derby with the metal conducting layer electric connection on the metal conducting layer, so that pin is by metal conducting layer and metal derby electric connection.
The method for packing of the chip of the technical program and encapsulating structure manufacture craft are simple, and production cost is lower, and can produce in enormous quantities, and then enhance productivity.
Description of drawings
Fig. 1 is the structural representation behind the stack release film that provides of the technical program execution mode.
Fig. 2 is the structural representation behind stack the second film of providing of the technical program execution mode.
Fig. 3 is the structure cutaway view of the pressing plate that provides of the technical program execution mode.
Fig. 4 is the pressure plate structure schematic diagram after the boring that provides of the technical program execution mode.
Fig. 5 is the structural representation after the pressing plate that provides of the technical program execution mode forms electroplating hole copper layer.
Fig. 6 is the structural representation after the pressing plate printing that provides of the technical program execution mode forms metal derby.
Fig. 7 is the structural representation after the pressing plate that provides of the technical program execution mode is removed loading plate and release film.
Fig. 8 is the structural representation of the pressing plate after the cutting that provides of the technical program execution mode.
The main element symbol description
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| Pressing plate | 30 |
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Following embodiment further specifies the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with drawings and Examples, chip packaging method and chip-packaging structure that the technical program is provided are described in further detail.
Described chip packaging method may further comprise the steps:
The first step: see also Fig. 1, a loading plate 110 be provided, and on described loading plate 110 a superimposed release film 100.
Described loading plate 110 can mainly play a supportive role for a thicker copper coin, and recommending thickness is the above copper coin of 35um.Described loading plate 110 also can be other metallic plates such as aluminium sheet, steel plate etc., can certainly be for glass fiber fabric base copper-clad plate commonly used in the circuit board making etc., do not cover substrate or other heat-resisting hard materials of Copper Foil, as long as can play a supporting role.
Described release film 100 can be for high temperature resistant separated type materials such as resistant to elevated temperatures PET release film or polytetrafluoroethylene films, so that it larger distortion and damage can not occur in follow-up high-temperature laminating processing procedure.Preferably, described release film 100 is the heat-releasable film, its two-sided glue-line that is provided with, and described glue-line is toughness under normal temperature condition, can be mutually bonding with other materials.When high temperature, lose viscosity, can be easy to peel off mutually with mutually bonding material.Glue-line of different nature, the temperature that loses viscosity is different, and the temperature that loses viscosity of used heat-releasable film has 80 degree, 100 degree, 120 degree and is higher than 120 degree etc. usually.In the present embodiment, the preferred temperature that loses viscosity of using is that 120 degree and above resin material are done described glue-line.
Second step: see also Fig. 2, successively superimposed one first film 210, a plurality of chip 240 on described release film 100, and described a plurality of chips 240 are fixed on described the first film 210, afterwards again at described a plurality of chips stack one second films 230.
In the present embodiment, described chip 240 quantity are two, each described chip 240 comprises a main part 241, and described main part 241 has relative first surface 243 and second surface 244, has a plurality of pins 242 at the first surface 243 of each described chip 240.When superimposed so that the second surface 244 of each chip 240 contacts with the first film, and so that described a plurality of pin 242 away from described the first film 210.
The fixed form of a plurality of chips 240 described in the present embodiment is that pre-pressing is fixed, after being about to described a plurality of chip 240 and forming an integral body with described the first film 210, and superimposed the second film 230 on described a plurality of chips 240 again.Wherein, pre-pressing refers to, with described a plurality of chips 240 and described the first film 210 by the short period as less than time of 10 minutes, and the temperature that is lower than described the first film 210 curing temperatures carries out pressing as being lower than 100 degrees centigrade, forms a process of the lower assembly of cohesive force.Certainly described a plurality of chips 240 also can be fixed with other modes, as with as described in form a plurality of by laser cutting etc. on the surface of the first film 210 and as described in the measure-alike limited impression of chip 240, described a plurality of chips 240 are placed respectively in the corresponding groove, thereby described a plurality of chips 240 are fixed on described the first film 210.Or after superimposed described a plurality of chips 240, the 3rd film (not shown) that directly is provided with pierced pattern with the corresponding position of one or more and described a plurality of chip 240 is blocked described a plurality of chips 240, afterwards superimposed described the second film 230 again.
Described the first film 210 can be prepreg.The material of described the first film 210 can contain for glass fiber fabric base, paper substrate, composite base, aramid fiber nonwoven fabric base or synthetic fibers base etc. the prepreg of reinforcing material, also can be the prepreg of the pure resinaes such as polyimides and epoxy resin.According to the needs of product thickness, described the first film 210 can be one deck prepreg or multilayer prepreg.
The material of described the second film 230 is identical with the material of the first film 210.Needs according to product thickness, described the second film 230 can be one deck prepreg or multilayer prepreg, wherein, the thickness of described the second film 230 must be greater than the thickness of described chip 240, so that can wrap up described chip 240 fully after 230 pressings of described the second film.If adopt the 3rd film that described a plurality of chips 240 are fixing, also the material with described the first film 210 is identical then to select the material of described the 3rd film.
If described release film 100 is the heat-releasable film, the curing temperature of described the first film 210, the second film 230 and the 3rd film should be lower than the temperature that glue-line on the described release film 100 loses viscosity.
The 3rd step: see also Fig. 3, described the first film 210 of pressing, a plurality of chip 240 and the second film 230 form a pressing plate 30 under the support of described loading plate 110 and described release film 100.
Described the first film 210 and described the second film 230 bond and are solidified into a packaging body 211, and described a plurality of chips 240 are embedded in the described packaging body 211, form a pressing plate 30.Described pressing plate 30 have the 3rd surface 301 that is affixed with described release film 100 and with 301 relative the 4th surfaces 302, described the 3rd surface.
The 4th step: see also Fig. 4, form to the inside of described pressing plate from the 4th surface 302 of described pressing plate 30 and described a plurality of pins 242 blind hole 221 one to one, each pin 242 exposes from the blind hole 221 of correspondence.
The degree of depth of wherein said a plurality of blind hole 221 described a plurality of pin 242 is come out, thereby the roof of described a plurality of pin 242 becomes respectively the part of the diapire of described a plurality of blind hole 221 for the end face to described pin 242 from described the 4th surface 302 ends.The aperture of described blind hole 221 be described pin 242 diameter 1.4-1.6 doubly, be preferably 1.5 times, the precision of the contraposition when needing with described pin 242 contraposition in the follow-up flow process to improve.
The generation type of described a plurality of blind hole 221 also can be other blind hole generation types such as machine drilling.
The 5th step: see also Fig. 5, at the hole wall formation coat of metal 222 of each described blind hole 221.
The described coat of metal 222 is combined closely to form with described pin 242 and is conducted.Wherein, also can adopt and spatter the mode such as cross and form the described coat of metal 222.Certainly, the material of the described coat of metal 222 can be copper or other conductive material such as other conducting metals or conducting resinl etc.
The 6th step: see also Fig. 6, the mode by paste solder printing on each described coat of metal 222 forms metal derby 223, the coat of metal 222 electric connections of described metal derby 223 and corresponding blind hole 221, formation base plate for packaging 40.
Before the printing, can carry out the surface treatments such as polish-brush or plasma cleaning to the described coat of metal 222, so that the described coat of metal 222 has certain roughness, thereby can combine closely with tin cream.
Certainly, the material of described metal derby 223 also can be other conductive metallic materials.
The 7th step: see also Fig. 7, remove described release film 100 and described loading plate 110.
If described release film 100 is the heat-releasable film, then described release film 100 is heated to its strippable temperature, afterwards, remove described release film 100 and described loading plate 110.
If described release film 100 is other release films except the heat-releasable film, then directly divest described release film 100 and described loading plate 110.
The 8th step: see also Fig. 8, cut described base plate for packaging 40, form a plurality of encapsulating structures 50 that include a chip 240.
Described encapsulating structure 50 comprises a packaging body 211, described packaging body 211 has relative the 301 and the 4th surface 302, the 3rd surface, be embedded with a chip 240 in the described packaging body 211, be provided with three pins 242 on the described chip 240, described three pins 242 are away from described the 4th surface 302, inside formation from from described the 3rd surface 301 to described packaging body 211 and described three pins 242 are blind hole 221 one to one, the hole wall of described blind hole 221 is provided with the coat of metal 222 with corresponding pin 242 electric connections, be formed with the metal derby 223 with coat of metal electric connection on the coat of metal 222, so that pin 242 is by the coat of metal 222 and metal derby 223 electric connections.The aperture of described blind hole 221 be described pin 242 diameter 1.4-1.6 doubly.Described packaging body 211 is for containing the resin of reinforcing material.
The chip packaging method of the technical program and encapsulating structure manufacture craft are simple, and production cost is lower, and can produce in enormous quantities, and then enhance productivity.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change the protection range that all should belong to claim of the present invention with distortion.
Claims (10)
1. the method for packing of a chip comprises step:
A plurality of chips, the first film and the second film are provided, and each described chip all has relative first surface and second surface, all has a plurality of pins on the first surface of each described chip;
Described a plurality of chips are fixed on described the first film so that the second surface of each chip contacts with the first film, and so that described a plurality of pin away from described the first film;
Described the second film is positioned over formation one superimposed sheet on described a plurality of chip, and described the second film has the 3rd surface away from described the first film;
The described superimposed sheet of pressing makes described the first film and described the second film solidify to form a packaging body, and described a plurality of chips are embedded in the described packaging body;
Form and each pin blind hole one to one to the second film is inner from the 3rd surface of the second film, each pin all exposes from the blind hole of correspondence;
Form metal conducting layer with corresponding pin electric connection at the inwall of each blind hole;
At the metal derby of metal conducting layer formation with the metal conducting layer electric connection, thereby form base plate for packaging; And
Cut described base plate for packaging, to form a plurality of encapsulating structures that respectively include a chip.
2. the method for packing of chip as claimed in claim 1, it is characterized in that, before described the second film being positioned over described a plurality of chip formation one superimposed sheet, the method for packing of described chip also comprises provides a supporting bracket and a release film, described release film is superimposed on the described supporting bracket, more described the first film is superimposed on the step on the described release film; Before the described base plate for packaging of cutting, the method for packing of described chip also comprises the step of removing described release film and described loading plate.
3. the method for packing of chip as claimed in claim 2 is characterized in that, described release film is the heat-releasable film, and the removal method of described release film and described loading plate divests after heating.
4. the method for packing of chip as claimed in claim 1, it is characterized in that, described a plurality of chips are positioned over after the step on described the first film, and the method for packing of described chip also comprises by pre-pressing described a plurality of chips and the fixing step that forms an integral body of described the first film.
5. the method for packing of chip as claimed in claim 1 is characterized in that, the aperture of described blind hole be described pin diameter 1.4-1.6 doubly.
6. the method for packing of chip as claimed in claim 1, it is characterized in that, before metal conducting layer forms metal derby with the metal conducting layer electric connection, also comprise described metal conducting layer is carried out surface treatment, so that the step that described metal conducting layer can be combined closely with described metal derby.
7. the method for packing of chip as claimed in claim 1 is characterized in that, the mode by paste solder printing forms described metal derby, and described metal derby is the tin cream piece.
8. chip-packaging structure, comprise a packaging body, described packaging body has relative first surface and second surface, be embedded with a chip in the described packaging body, be provided with a plurality of pins on the described chip, described a plurality of pin is away from described second surface, inside from from described first surface to described packaging body is formed with and described a plurality of pins blind hole one to one, the hole wall of described blind hole is provided with the metal conducting layer with corresponding pin electric connection, be formed with the metal derby with the metal conducting layer electric connection on the metal conducting layer, so that pin is by metal conducting layer and metal derby electric connection.
9. chip-packaging structure as claimed in claim 8 is characterized in that, the aperture of described blind hole be described pin diameter 1.4-1.6 doubly.
10. chip-packaging structure as claimed in claim 8 is characterized in that, described packaging body is the resin that contains reinforcing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100812486A CN103367339A (en) | 2012-03-26 | 2012-03-26 | Chip-packaging method and chip-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100812486A CN103367339A (en) | 2012-03-26 | 2012-03-26 | Chip-packaging method and chip-packaging structure |
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| Publication Number | Publication Date |
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| CN103367339A true CN103367339A (en) | 2013-10-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012100812486A Pending CN103367339A (en) | 2012-03-26 | 2012-03-26 | Chip-packaging method and chip-packaging structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103527A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level semiconductor chip package process |
| CN104103529A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Fan out type square piece level semiconductor three dimension chip packaging technology |
| CN104103526A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level three-dimensional semiconductor chip package process |
| CN108257875A (en) * | 2016-12-28 | 2018-07-06 | 碁鼎科技秦皇岛有限公司 | The production method of chip package base plate, chip-packaging structure and the two |
Citations (3)
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| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| US20060049530A1 (en) * | 2004-09-09 | 2006-03-09 | Phoenix Precision Technology Corporation | Method of embedding semiconductor chip in support plate and embedded structure thereof |
| CN1971865A (en) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | Chip electric connection structure and its manufacturing method |
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2012
- 2012-03-26 CN CN2012100812486A patent/CN103367339A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| US20060049530A1 (en) * | 2004-09-09 | 2006-03-09 | Phoenix Precision Technology Corporation | Method of embedding semiconductor chip in support plate and embedded structure thereof |
| CN1971865A (en) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | Chip electric connection structure and its manufacturing method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103527A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level semiconductor chip package process |
| CN104103529A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Fan out type square piece level semiconductor three dimension chip packaging technology |
| CN104103526A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Improved fanout panel level three-dimensional semiconductor chip package process |
| CN104103527B (en) * | 2014-07-22 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of improved fan-out square chip level semiconductor die package technique |
| CN104103526B (en) * | 2014-07-22 | 2017-10-24 | 华进半导体封装先导技术研发中心有限公司 | A kind of improved fan-out square chip level 3 D semiconductor chip package process |
| CN108257875A (en) * | 2016-12-28 | 2018-07-06 | 碁鼎科技秦皇岛有限公司 | The production method of chip package base plate, chip-packaging structure and the two |
| CN108257875B (en) * | 2016-12-28 | 2021-11-23 | 碁鼎科技秦皇岛有限公司 | Chip packaging substrate, chip packaging structure and manufacturing method of chip packaging substrate and chip packaging structure |
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Application publication date: 20131023 |