CN103366812B - The device of Flash online programming and implementation method on circuit board - Google Patents
The device of Flash online programming and implementation method on circuit board Download PDFInfo
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Abstract
The present invention relates to Embedded System Design field, be specifically related to Flash online programming device and implementation method on a kind of circuit board.Implementation method comprises: operational order and programming data are packed according to self-defined frame format by desktop application software, and its USB drives and resolves to usb data bag again and be sent to usb protocol converter by cable; Converter parses self-defined frame format packet and sends single-chip microcomputer; Single-chip microcomputer resolves into some Flash read and write access sequences after packet is parsed order and data by self-defined frame format and sends Target Board CPLD by custom programming interface after making parallel-serial conversion; Realize after CPLD circuit serioparallel exchange Flash read and write access and Flash accessed the path that comes to the same thing oppositely transmitting desktop application software.The present invention can on circuit boards to Flash online programming, and production process is few, simple to operate, and not only production cost is low, and work efficiency and production efficiency are all higher.
Description
Technical field
The present invention relates to Embedded System Design field, be specifically related to device and the implementation method of Flash online programming on a kind of circuit board.
Background technology
At present, the circuit board of embedded processor platform generally comprises two kinds to the method for Flash programming: 1, by Special programming and connector by burning program in Flash, then by Flash and welding circuit board; 2, buy Special debugging device, by Special debugging device, routine data is directly downloaded in the storer of circuit board.
But there is following defect respectively in above two kinds of methods:
(1) by burning program in Flash, Flash is all more loaded down with trivial details with the production process of welding circuit board, and once program corruption after welding, just the Flash be welded on circuit board takes off by needs, again again welds after burning program; For relatively more conventional BGA(BallGridArray, Ball Grid Array) encapsulate Flash, due to its welding process inherently more complicated, the operating process therefore repeating burning and welding is more complicated.In addition, the purchase cost of Special programming and connector is higher, and connector ratio is easier to damage, and needs often to change.Therefore, programmed to Flash by Special programming and connector, not only production cost is higher, and operating process more complicated, and work efficiency is lower.
(2) for the method being realized Flash online programming by Special debugging device, owing to using Special debugging device need have certain professional knowledge, therefore, the scope of application being realized Flash online programming by Special debugging device is more single; And Special debugging device needs to buy special configuration data according to the type of flush bonding processor, if processor is changed, Special debugging device also will buy new data thereupon again, and the processor after changing with correspondence, the purchase cost buying Special debugging device and configuration data is higher.In addition, lower by the download speed of download of data of Special debugging device, the routine data downloading 512k byte needs more than 15 seconds, and its production efficiency is lower.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide device and the implementation method of Flash online programming on a kind of circuit board, can on circuit boards to Flash online programming, its production process is few, operating process is fairly simple, not only production cost is lower, and work efficiency and production efficiency all higher.
For reaching above object, the device of Flash online programming on a kind of circuit board provided by the invention, comprise the computer, the USB that are provided with desktop application software to turn FIFO protocol converter, be provided with the single-chip microcomputer of Flash drive software, be positioned at complex programmable logic device (CPLD) on circuit board and Flash, described desktop application software design patterns has USB bottom layer driving; Described computer turns FIFO protocol converter by USB standard cable with USB and is connected, and described USB is turned FIFO protocol converter and is connected with single-chip microcomputer by fifo interface, and described single-chip microcomputer is connected with CPLD by custom programming device interface; Described custom programming device interface adopts parallel bus interface, and bus comprises 3 bit address lines, 8 position datawires, read-write, chip selection signal, reset signal, siding and signal ground; Described custom programming device interface adopts the parallel asynchronous interface of controller general, and the sequential of custom programming device interface is by the hardware implementing of single-chip microcomputer;
User imports the programming data needed for Flash on desktop application software, and described programming data comprises data file, the length of data file, the write start address of Flash and the length of Flash erase area; User is to desktop application software transmit operation instruction, operational order and corresponding programming data are packaged into self-defining data frame format packet according to self-defining data frame format by desktop application software, self-defining data frame format packet is packaged into usb data bag by the USB bottom layer driving of desktop application software, and usb data bag is sent to USB by USB cable and turns FIFO protocol converter by computer;
USB turns FIFO protocol converter and usb data Packet analyzing is become self-defined frame format packet, USB turn FIFO protocol converter by fifo interface by self-defined frame format Packet Generation to single-chip microcomputer, the Flash drive software of single-chip microcomputer is according to standard format indicating bit standard C FI, resolve self-defined frame format packet, the order parsed is become some Flash read and write access sequences by Flash drive software with data decomposition; The start address of the length of the data file needed for each Flash read and write access sequence, data file and write Flash is resolved by Flash drive software, by the Flash address that the Flash address spaces of 32 is 48, the Flash data of 16 is converted into the Flash data of 28;
Single-chip microcomputer carries out read and write access by CPLD to Flash, single-chip microcomputer writes Flash by CPLD, when single-chip microcomputer is to CPLD write access, read-write and the chip selection signal of custom programming device interface are low level, single-chip microcomputer, by the ADDR4 address register of custom programming device interface to the memory address 31 ~ 24 of CPLD, sends 31 ~ 24 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the ADDR3 address register of custom programming device interface to the memory address 23 ~ 16 of CPLD, sends 23 ~ 16 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the ADDR2 address register of custom programming device interface to the memory address 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the ADDR1 address register of custom programming device interface to the memory address 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the DATA2 data register of custom programming device interface to the storage data 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash data of 8 that need write and latches; Single-chip microcomputer, by the DATA1 data register of custom programming device interface to the storage data 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash data of 8 that need write and latches; The data of write needed for Flash all send; Single-chip microcomputer by custom programming device interface to CPLD write trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, CPLD is according to the Flash address of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register, the Flash data latched in DATA2 data register and DATA1 data register is sent to Flash, completes and the mono-recordable of FLASH is accessed;
Single-chip microcomputer reads Flash by CPLD, when single-chip microcomputer is to CPLD read access, read-write is high level, and chip selection signal is low level, and single-chip microcomputer is sent 31 ~ 24 of the Flash address of 8 that need access by the ADDR4 address register of custom programming device interface to CPLD and latched; Single-chip microcomputer is sent 23 ~ 16 of the Flash address of 8 that need access by the ADDR3 address register of custom programming device interface to CPLD and is latched; Single-chip microcomputer is sent 15 ~ 8 of the Flash address of 8 that need access by the ADDR2 address register of custom programming device interface to CPLD and is latched; Single-chip microcomputer is sent 7 ~ 0 of the Flash address of 8 that need access by the ADDR1 address register of custom programming device interface to CPLD and is latched; Single-chip microcomputer by custom programming device interface to CPLD read trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, the Flash address of 8 of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register is sent to Flash by CPLD, Flash by the storage data of appropriate address, in the DATA2 data register being sent to CPLD and DATA1 data register; Single-chip microcomputer reads and stores the data of DATA2 data register; Single-chip microcomputer reads and stores the data of DATA1 data register;
Whether single-chip microcomputer judges the read and write access of Flash successful, if so, then read and write access successful information is back to desktop application software, otherwise read and write access failure information is back to desktop application software.
On the basis of technique scheme, described operational order comprises scanning Flash instruction, erasing Flash instruction, programming Flash instruction and verification Flash instruction; When described operational order is for erasing Flash instruction, corresponding programming data is the length of Flash erase area and the start address of write Flash; When described operational order is for programming Flash instruction, the data file of corresponding programming data needed for programming Flash, the length of data file and the start address of write Flash; When described operational order is for verification Flash instruction, data file, the length of data file and the start address of Flash of corresponding programming data needed for verification Flash.
On the basis of technique scheme, described ADDR4 address register is positioned at the 3b000 address place of CPLD internal circuit; Described ADDR3 address register is positioned at the 3b001 address place of CPLD internal circuit; Described ADDR2 address register is positioned at the 3b010 address place of CPLD internal circuit; Described ADDR1 address register is positioned at the 3b011 address place of CPLD internal circuit; Described DATA2 data register is positioned at the 3b100 address place of CPLD internal circuit; Described DATA1 data register is positioned at the 3b101 address place of CPLD internal circuit; Described trigger address register-bit of writing is in the 3b110 address place of CPLD internal circuit; Described trigger address register-bit of reading is in the 3b110 address place of CPLD internal circuit.
On the basis of technique scheme, single-chip microcomputer described in step D judges to comprise the whether successful step of the read and write access of Flash: single-chip microcomputer reads the status register bit of Flash, single-chip microcomputer judges the numerical value whether right value of the status register bit of the Flash read, if, then read and write access success, otherwise read and write access failure.
Implementation method based on Flash online programming on the circuit board of said apparatus provided by the invention, it is characterized in that, comprise the following steps: A, user import the programming data needed for Flash on desktop application software, described programming data comprises data file, the length of data file, the write start address of Flash and the length of Flash erase area; User is to desktop application software transmit operation instruction, operational order and corresponding programming data are packaged into self-defining data frame format packet according to self-defining data frame format by desktop application software, self-defining data frame format packet is resolved to usb data bag by the USB bottom layer driving of desktop application software, and usb data bag is sent to USB by USB cable and turns FIFO protocol converter by computer; B, USB turn FIFO protocol converter and usb data Packet analyzing are become self-defined frame format packet, USB turn FIFO protocol converter by fifo interface by self-defined frame format Packet Generation to single-chip microcomputer, the Flash drive software of single-chip microcomputer is according to standard format indicating bit standard, resolve self-defined frame format packet, the order parsed is become some Flash read and write access sequences by Flash drive software with data decomposition; The start address of the length of the data file needed for each Flash read and write access sequence, data file and write Flash is resolved by Flash drive software, by the Flash address that the Flash address spaces of 32 is 48, the Flash data of 16 is converted into the Flash data of 28; C, single-chip microcomputer carry out read and write access by CPLD to Flash, single-chip microcomputer writes Flash by CPLD, when single-chip microcomputer is to CPLD write access, read-write and the chip selection signal of custom programming device interface are low level, and single-chip microcomputer completes a Flash write access according to following steps:
C101: single-chip microcomputer, by the ADDR4 address register of custom programming device interface to the memory address 31 ~ 24 of CPLD, sends 31 ~ 24 of the Flash address of 8 that need access and latches; C102: single-chip microcomputer, by the ADDR3 address register of custom programming device interface to the memory address 23 ~ 16 of CPLD, sends 23 ~ 16 of the Flash address of 8 that need access and latches; C103: single-chip microcomputer, by the ADDR2 address register of custom programming device interface to the memory address 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash address of 8 that need access and latches; C104: single-chip microcomputer, by the ADDR1 address register of custom programming device interface to the memory address 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash address of 8 that need access and latches; C105: single-chip microcomputer, by the DATA2 address register of custom programming device interface to the storage data 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash data of 8 that need write and latches; C106: single-chip microcomputer, by the DATA1 address register of custom programming device interface to the storage data 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash data of 8 that need write and latches; The data of write needed for Flash all send; C107: single-chip microcomputer by custom programming device interface to CPLD write trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, the Flash data latched in DATA2 data register and DATA1 data register, according to the Flash address of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register, is sent to Flash by CPLD;
Single-chip microcomputer reads Flash by CPLD, when single-chip microcomputer is to CPLD read access, read-write is high level, chip selection signal is low level, and single-chip microcomputer completes Flash read access a: C201 according to following steps: single-chip microcomputer is sent 31 ~ 24 of the Flash address of 8 that need access by the ADDR4 address register of custom programming device interface to CPLD and latched; C202: single-chip microcomputer is sent 23 ~ 16 of the Flash address of 8 that need access by the ADDR3 address register of custom programming device interface to CPLD and latched; C203: single-chip microcomputer is sent 15 ~ 8 of the Flash address of 8 that need access by the ADDR2 address register of custom programming device interface to CPLD and latched; C204: single-chip microcomputer is sent 7 ~ 0 of the Flash address of 8 that need access by the ADDR1 address register of custom programming device interface to CPLD and latched; C205: single-chip microcomputer by custom programming device interface to CPLD read trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, the Flash address of 8 of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register is sent to Flash by CPLD, Flash by the storage data of appropriate address, in the DATA2 data register being sent to CPLD and DATA1 data register; C206: single-chip microcomputer reads and stores the data of DATA2 data register; C207: single-chip microcomputer reads and stores the data of DATA1 data register;
Whether D, single-chip microcomputer judge the read and write access of Flash successful, if so, then read and write access successful information is back to desktop application software, otherwise read and write access failure information is back to desktop application software.
On the basis of technique scheme, described operational order comprises scanning Flash instruction, erasing Flash instruction, programming Flash instruction and verification Flash instruction; When described operational order is for erasing Flash instruction, corresponding programming data is the length of Flash erase area and the start address of write Flash; When described operational order is for programming Flash instruction, the data file of corresponding programming data needed for programming Flash, the length of data file and the start address of write Flash; When described operational order is for verification Flash instruction, data file, the length of data file and the start address of Flash of corresponding programming data needed for verification Flash.
On the basis of technique scheme, the address register of ADDR4 described in step C is positioned at the 3b000 address place of CPLD internal circuit; Described ADDR3 address register is positioned at the 3b001 address place of CPLD internal circuit; Described ADDR2 address register is positioned at the 3b010 address place of CPLD internal circuit; Described ADDR1 address register is positioned at the 3b011 address place of CPLD internal circuit; Described DATA2 data register is positioned at the 3b100 address place of CPLD internal circuit; Described DATA1 data register is positioned at the 3b101 address place of CPLD internal circuit; Described trigger address register-bit of writing is in the 3b110 address place of CPLD internal circuit; Described trigger address register-bit of reading is in the 3b110 address place of CPLD internal circuit.
On the basis of technique scheme, single-chip microcomputer described in step D judges to comprise the whether successful step of the read and write access of Flash: single-chip microcomputer reads the status register bit of Flash, single-chip microcomputer judges the numerical value whether right value of the status register bit of the Flash read, if, then read and write access success, otherwise read and write access failure.
On the basis of technique scheme, the step in step D, read and write access successful information being back to desktop application software comprises: successful for read and write access information is packaged into self-defined frame format packet according to self-defined frame format by single-chip microcomputer, and self-defined frame format Packet Generation is turned FIFO protocol converter to USB by fifo interface by single-chip microcomputer; USB turns FIFO protocol converter and self-defined frame format packet is resolved to usb data bag and is sent to desktop application software; The USB bottom layer driving of desktop application software becomes self-defined frame format packet to usb data Packet analyzing, and the self-defined frame format packet of desktop application software parses, obtains the successful data of read and write access, informs user operation success.
On the basis of technique scheme, the step in step D, read and write access failure information being back to desktop application software comprises: the information of read and write access failure is packaged into self-defined frame format packet according to self-defined frame format by single-chip microcomputer, and self-defined frame format Packet Generation is turned FIFO protocol converter to USB by fifo interface by single-chip microcomputer; USB turns FIFO protocol converter and self-defined frame format packet is resolved to usb data bag and is sent to desktop application software; The USB bottom layer driving of desktop application software becomes self-defined frame format packet to usb data Packet analyzing, and the self-defined frame format packet of desktop application software parses, obtains the data of read and write access failure, informs user operation failure.
Compared with prior art, beneficial effect of the present invention is:
(1) single-chip microcomputer of the present invention is directly by carrying out read and write access to the CPLD be positioned on Target Board to Flash, with in prior art by burning program in Flash, by Flash compared with the programmed method of welding circuit board, the present invention does not need by burning program in Flash, does not need Flash and welding circuit board yet.Therefore, by the present invention, to the Flash online programming on circuit board, not only production process is less, and operating process is fairly simple, and does not need Special programming and connector, and its production cost is lower.
(2) the present invention adopts and carries out data transmission by USB interface, its transmission data can reach 1M byte per second, and the speed of other interfaces of the present invention is greater than 1M byte per second, therefore, when the present invention programmes to Flash, the transfer rate of programming data can reach 1M byte per second, its transfer rate is higher, and empirical tests draws, the burning program of 512K byte was only needed for 4 seconds in Flash by the present invention, its speed of download is very fast, and production efficiency is higher.
(3) the present invention directly can carry out burning repeatedly to Flash on circuit boards, do not have the operation of welding, for BGA package Flash, the present invention's production process of burning program on BGA package Flash is less, not only operating process is fairly simple, and reliability is higher.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the device of Flash online programming on circuit board in the embodiment of the present invention;
Fig. 2 is the bus definition figure of custom programming device interface in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Shown in Figure 1, the device of Flash online programming on a kind of circuit board that the embodiment of the present invention provides, comprise the computer, the USB that are provided with desktop application software and turn FIFO(FirstInputFirstOutput, First Input First Output) protocol converter, the single-chip microcomputer being provided with Flash drive software, the CPLD(ComplexProgrammableLogicDevice be positioned on circuit board, CPLD) and Flash; Desktop application software design patterns has USB bottom layer driving.Computer turns FIFO protocol converter by USB standard cable with USB and is connected, USB is turned FIFO protocol converter and is connected with single-chip microcomputer by FIFO standard interface, single-chip microcomputer is connected with CPLD by custom programming device interface, custom programming device interface adopts the parallel asynchronous interface of controller general, and the sequential of custom programming device interface is by the hardware implementing of single-chip microcomputer.
Shown in Figure 2, a kind of parallel bus interface that custom programming device interface adopts common single-chip microcomputer to have, the A [2..0] of bus is 3 bit address lines, D [7..0] is 8 position datawires, R/W is read-write, and CS is chip selection signal, and RESET is reset signal, BAK1 is siding, and GND is signal ground.When custom programming device interface carries out data transmission, not only interface signal is less, and can keep certain data bandwidth.
The implementation method based on Flash online programming on the circuit board of said apparatus that the embodiment of the present invention provides, comprises the following steps:
S1: user imports the programming data needed for Flash on desktop application software, programming data comprises data file, the length of data file, the write start address of Flash and the length of Flash erase area.
S2: user is to desktop application software transmit operation instruction, operational order and corresponding programming data are packaged into self-defining data frame format packet according to self-defining data frame format by desktop application software, self-defining data frame format packet is resolved to usb data bag by the USB bottom layer driving of desktop application software, and usb data bag is sent to USB by USB cable and turns FIFO protocol converter by computer.
Operational order comprises scanning Flash instruction, erasing Flash instruction, programming Flash instruction and verification Flash instruction.When operational order is for scanning Flash instruction, do not need corresponding programming data; When operational order is for erasing Flash instruction, corresponding programming data is the length of Flash erase area and the start address of write Flash; When operational order is for programming Flash instruction, the data file of corresponding programming data needed for programming Flash, the length of data file and the start address of write Flash; When operational order is for verification Flash instruction, data file, the length of data file and the start address of Flash of corresponding programming data needed for verification Flash.
S3:USB turns FIFO protocol converter and usb data Packet analyzing is become self-defined frame format packet, USB turn FIFO protocol converter by fifo interface by self-defined frame format Packet Generation to single-chip microcomputer.The Flash drive software of single-chip microcomputer is according to CFI(CommonFlashInterface, standard format indicating bit) standard, resolve self-defined frame format packet, the order parsed is become some Flash read and write access sequences by Flash drive software with data decomposition; The start address of the length of the data file needed for each Flash read and write access sequence, data file and write Flash is resolved by Flash drive software, by the Flash address that the Flash address spaces of 32 is 48, the Flash data of 16 is converted into the Flash data of 28.
S4: single-chip microcomputer carries out read and write access by CPLD to Flash.
The address register storing 31 ~ 24, CPLD internal circuit address is defined as ADDR4 address register; The address register of memory address 23 ~ 16 is defined as ADDR3 address register; The address register of memory address 15 ~ 8 is defined as ADDR2 address register; The address register of memory address 7 ~ 0 is defined as ADDR1 address register; The data register storing data 15 ~ 8 is defined as DATA2 data register; The data register storing data 7 ~ 0 is defined as DATA1 data register.
When writing Flash, single-chip microcomputer carries out write access to CPLD, and R/W signal and the CS signal of custom programming device interface are low level; The Flash address of 48 is sent in the address register of CPLD internal logic circuit by custom programming device interface by single-chip microcomputer; Flash data with 28 is sent in the data register of CPLD internal logic circuit by custom programming device interface by single-chip microcomputer.Ginseng is shown in Table 1, and single-chip microcomputer sends Flash address to CPLD and Flash data comprises the following steps:
S411: the ADDR4 address register to the 3b000 address place of CPLD sends 31 ~ 24 of the Flash address of 8 that need access and latches.
S412: the ADDR3 address register to the 3b001 address place of CPLD sends 23 ~ 16 of the Flash address of 8 that need access and latches.
S413: the ADDR2 address register to the 3b010 address place of CPLD sends 15 ~ 8 of the Flash address of 8 that need access and latches.
S414: the ADDR1 address register to the 3b011 address place of CPLD sends 7 ~ 0 of the Flash address of 8 that need access and latches; The address of access needed for Flash all sends.
S415: the DATA2 data register to the 3b100 address place of CPLD sends 15 ~ 8 of the Flash data of 8 that need write and latches.
S416: the DATA1 data register to the 3b101 address place of CPLD sends 7 ~ 0 of the Flash data of 8 that need write and latches; The data of write needed for Flash all send.
S417: the WR_END address register (writing trigger address register) to the 3b110 address place of CPLD writes arbitrary value, trigger the control signal that CPLD accesses Flash, CPLD is according to the Flash address of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register, the Flash data latched in DATA2 data register and DATA1 data register is sent to Flash, completes and the mono-recordable of Flash is accessed.
Table 1: the visit data sequence list writing FLASH
When reading Flash, single-chip microcomputer carries out read access to CPLD, and R/W signal is high level, and CS signal is low level, and ginseng is shown in Table 2, and reads Flash and comprises the following steps:
S421: the ADDR4 address register to the 3b000 address place of CPLD sends 31 ~ 24 of the Flash address of 8 that need access and latches.
S422: the ADDR3 address register to the 3b001 address place of CPLD sends 23 ~ 16 of the Flash address of 8 that need access and latches.
S423: the ADDR2 address register to the 3b010 address place of CPLD sends 15 ~ 8 of the Flash address of 8 that need access and latches.
S424: the ADDR1 address register to the 3b011 address place of CPLD sends 7 ~ 0 of the Flash address of 8 that need access and latches; The address of access needed for Flash all sends.
S425: single-chip microcomputer writes arbitrary value to the RD_START address register (reading trigger address register) at the 3b110 address place of CPLD, trigger the control signal that CPLD accesses Flash, the Flash address of 8 of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register is sent to Flash by CPLD, Flash by the storage data of appropriate address, in the DATA2 data register being sent to CPLD and DATA1 data register.
S426: single-chip microcomputer, from CPLD internal circuit address 3b100, reads and stores the data of DATA2 data register.
S427: single-chip microcomputer, from CPLD internal circuit address 3b101, reads and stores the data of DATA1 data register, completing the read access of single to FLASH.
When single-chip microcomputer carries out the read-write operation of Flash by CPLD, that single-chip microcomputer completes the single read and write access of Flash and go here and there conversion, CPLD completes the string of the single read and write access of Flash and transforms (when namely completing single-chip microcomputer to Flash, going here and there and the bridging functionality transformed by also going here and there to be transformed into).
Table 2: the visit data sequence list reading Flash
S5: whether single-chip microcomputer judges the read and write access of Flash successful, if so, then forwards step S6 to, otherwise forwards step S7 to.
Single-chip microcomputer judges: single-chip microcomputer reads the status register bit of Flash, single-chip microcomputer judges the numerical value whether right value of the status register bit of the Flash read, if, to the read and write access success of Flash, forward step S6 to, otherwise to the read and write access failure of Flash, forward step S7 to.
S6: successful for read and write access information is packaged into self-defined frame format packet according to self-defined frame format by single-chip microcomputer, self-defined frame format Packet Generation is turned FIFO protocol converter to USB by fifo interface by single-chip microcomputer; USB turns FIFO protocol converter and self-defined frame format packet is resolved to usb data bag and is sent to desktop application software; The USB bottom layer driving of desktop application software becomes self-defined frame format packet to usb data Packet analyzing, and the self-defined frame format packet of desktop application software parses, obtains the successful data of read and write access, informs user operation success.
S7: the information of read and write access failure is packaged into self-defined frame format packet according to self-defined frame format by single-chip microcomputer, self-defined frame format Packet Generation is turned FIFO protocol converter to USB by fifo interface by single-chip microcomputer; USB turns FIFO protocol converter and self-defined frame format packet is resolved to usb data bag and is sent to desktop application software; The USB bottom layer driving of desktop application software becomes self-defined frame format packet to usb data Packet analyzing, and the self-defined frame format packet of desktop application software parses, obtains the data of read and write access failure, informs user operation failure.
In actual use, desktop application software designs by visual programming software, the driving that the manufacturer that USB bottom layer driving on computer can select USB to turn FIFO protocol converter provides, USB bottom layer driving can select the chip FT245BL of FTDI company, chip producer provides USB bottom layer driving, USB bottom layer driving does not need especial manufacture, and what reduce Flash programmed method realizes difficulty.Single-chip microcomputer needs enough I/O ports (pins of input and output), is connected to turn FIFO protocol converter with USB.
The present invention is not limited to above-mentioned embodiment, and for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications are also considered as within protection scope of the present invention.The content be not described in detail in this instructions belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. the device of Flash online programming on a circuit board, it is characterized in that: comprise the computer, the USB that are provided with desktop application software and turn FIFO protocol converter, be provided with the single-chip microcomputer of Flash drive software, be positioned at complex programmable logic device (CPLD) on circuit board and Flash, described desktop application software design patterns has USB bottom layer driving; Described computer turns FIFO protocol converter by USB standard cable with USB and is connected, and described USB is turned FIFO protocol converter and is connected with single-chip microcomputer by fifo interface, and described single-chip microcomputer is connected with CPLD by custom programming device interface; Described custom programming device interface adopts parallel bus interface, and bus comprises 3 bit address lines, 8 position datawires, read-write, chip selection signal, reset signal, siding and signal ground; Described custom programming device interface adopts the parallel asynchronous interface of controller general, and the sequential of custom programming device interface is by the hardware implementing of single-chip microcomputer;
User imports the programming data needed for Flash on desktop application software, and described programming data comprises data file, the length of data file, the write start address of Flash and the length of Flash erase area; User is to desktop application software transmit operation instruction, operational order and corresponding programming data are packaged into self-defining data frame format packet according to self-defining data frame format by desktop application software, self-defining data frame format packet is packaged into usb data bag by the USB bottom layer driving of desktop application software, and usb data bag is sent to USB by USB cable and turns FIFO protocol converter by computer;
USB turns FIFO protocol converter and usb data Packet analyzing is become self-defined frame format packet, USB turn FIFO protocol converter by fifo interface by self-defined frame format Packet Generation to single-chip microcomputer, the Flash drive software of single-chip microcomputer is according to standard format indicating bit standard C FI, resolve self-defined frame format packet, the order parsed is become some Flash read and write access sequences by Flash drive software with data decomposition; The start address of the length of the data file needed for each Flash read and write access sequence, data file and write Flash is resolved by Flash drive software, by the Flash address that the Flash address spaces of 32 is 48, the Flash data of 16 is converted into the Flash data of 28;
Single-chip microcomputer carries out read and write access by CPLD to Flash, single-chip microcomputer writes Flash by CPLD, when single-chip microcomputer is to CPLD write access, read-write and the chip selection signal of custom programming device interface are low level, single-chip microcomputer, by the ADDR4 address register of custom programming device interface to the memory address 31 ~ 24 of CPLD, sends 31 ~ 24 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the ADDR3 address register of custom programming device interface to the memory address 23 ~ 16 of CPLD, sends 23 ~ 16 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the ADDR2 address register of custom programming device interface to the memory address 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the ADDR1 address register of custom programming device interface to the memory address 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash address of 8 that need access and latches; Single-chip microcomputer, by the DATA2 data register of custom programming device interface to the storage data 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash data of 8 that need write and latches; Single-chip microcomputer, by the DATA1 data register of custom programming device interface to the storage data 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash data of 8 that need write and latches; The data of write needed for Flash all send; Single-chip microcomputer by custom programming device interface to CPLD write trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, CPLD is according to the Flash address of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register, the Flash data latched in DATA2 data register and DATA1 data register is sent to Flash, completes and the mono-recordable of FLASH is accessed;
Single-chip microcomputer reads Flash by CPLD, when single-chip microcomputer is to CPLD read access, read-write is high level, and chip selection signal is low level, and single-chip microcomputer is sent 31 ~ 24 of the Flash address of 8 that need access by the ADDR4 address register of custom programming device interface to CPLD and latched; Single-chip microcomputer is sent 23 ~ 16 of the Flash address of 8 that need access by the ADDR3 address register of custom programming device interface to CPLD and is latched; Single-chip microcomputer is sent 15 ~ 8 of the Flash address of 8 that need access by the ADDR2 address register of custom programming device interface to CPLD and is latched; Single-chip microcomputer is sent 7 ~ 0 of the Flash address of 8 that need access by the ADDR1 address register of custom programming device interface to CPLD and is latched; Single-chip microcomputer by custom programming device interface to CPLD read trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, the Flash address of 8 of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register is sent to Flash by CPLD, Flash by the storage data of appropriate address, in the DATA2 data register being sent to CPLD and DATA1 data register; Single-chip microcomputer reads and stores the data of DATA2 data register; Single-chip microcomputer reads and stores the data of DATA1 data register;
Whether single-chip microcomputer judges the read and write access of Flash successful, if so, then read and write access successful information is back to desktop application software, otherwise read and write access failure information is back to desktop application software.
2. the device of Flash online programming on circuit board as claimed in claim 1, is characterized in that: described operational order comprises scanning Flash instruction, erasing Flash instruction, programming Flash instruction and verification Flash instruction; When described operational order is for erasing Flash instruction, corresponding programming data is the length of Flash erase area and the start address of write Flash; When described operational order is for programming Flash instruction, the data file of corresponding programming data needed for programming Flash, the length of data file and the start address of write Flash; When described operational order is for verification Flash instruction, data file, the length of data file and the start address of Flash of corresponding programming data needed for verification Flash.
3. the device of Flash online programming on circuit board as claimed in claim 1, is characterized in that: described ADDR4 address register is positioned at the 3b000 address place of CPLD internal circuit; Described ADDR3 address register is positioned at the 3b001 address place of CPLD internal circuit; Described ADDR2 address register is positioned at the 3b010 address place of CPLD internal circuit; Described ADDR1 address register is positioned at the 3b011 address place of CPLD internal circuit; Described DATA2 data register is positioned at the 3b100 address place of CPLD internal circuit; Described DATA1 data register is positioned at the 3b101 address place of CPLD internal circuit; Described trigger address register-bit of writing is in the 3b110 address place of CPLD internal circuit; Described trigger address register-bit of reading is in the 3b110 address place of CPLD internal circuit.
4. the device of Flash online programming on circuit board as claimed in claim 1, it is characterized in that, described single-chip microcomputer judges to comprise the whether successful step of the read and write access of Flash: single-chip microcomputer reads the status register bit of Flash, single-chip microcomputer judges the numerical value whether right value of the status register bit of the Flash read, if, then read and write access success, otherwise read and write access failure.
5., based on an implementation method for Flash online programming on the circuit board of device described in any one of Claims 1-4, it is characterized in that, comprise the following steps:
A, user import the programming data needed for Flash on desktop application software, and described programming data comprises data file, the length of data file, the write start address of Flash and the length of Flash erase area; User is to desktop application software transmit operation instruction, operational order and corresponding programming data are packaged into self-defining data frame format packet according to self-defining data frame format by desktop application software, self-defining data frame format packet is resolved to usb data bag by the USB bottom layer driving of desktop application software, and usb data bag is sent to USB by USB cable and turns FIFO protocol converter by computer;
B, USB turn FIFO protocol converter and usb data Packet analyzing are become self-defined frame format packet, USB turn FIFO protocol converter by fifo interface by self-defined frame format Packet Generation to single-chip microcomputer, the Flash drive software of single-chip microcomputer is according to standard format indicating bit standard, resolve self-defined frame format packet, the order parsed is become some Flash read and write access sequences by Flash drive software with data decomposition; The start address of the length of the data file needed for each Flash read and write access sequence, data file and write Flash is resolved by Flash drive software, by the Flash address that the Flash address spaces of 32 is 48, the Flash data of 16 is converted into the Flash data of 28;
C, single-chip microcomputer carry out read and write access by CPLD to Flash, single-chip microcomputer writes Flash by CPLD, when single-chip microcomputer is to CPLD write access, read-write and the chip selection signal of custom programming device interface are low level, and single-chip microcomputer completes a Flash write access according to following steps:
C101: single-chip microcomputer, by the ADDR4 address register of custom programming device interface to the memory address 31 ~ 24 of CPLD, sends 31 ~ 24 of the Flash address of 8 that need access and latches;
C102: single-chip microcomputer, by the ADDR3 address register of custom programming device interface to the memory address 23 ~ 16 of CPLD, sends 23 ~ 16 of the Flash address of 8 that need access and latches;
C103: single-chip microcomputer, by the ADDR2 address register of custom programming device interface to the memory address 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash address of 8 that need access and latches;
C104: single-chip microcomputer, by the ADDR1 address register of custom programming device interface to the memory address 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash address of 8 that need access and latches;
C105: single-chip microcomputer, by the DATA2 address register of custom programming device interface to the storage data 15 ~ 8 of CPLD, sends 15 ~ 8 of the Flash data of 8 that need write and latches;
C106: single-chip microcomputer, by the DATA1 address register of custom programming device interface to the storage data 7 ~ 0 of CPLD, sends 7 ~ 0 of the Flash data of 8 that need write and latches; The data of write needed for Flash all send;
C107: single-chip microcomputer by custom programming device interface to CPLD write trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, the Flash data latched in DATA2 data register and DATA1 data register, according to the Flash address of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register, is sent to Flash by CPLD;
Single-chip microcomputer reads Flash by CPLD, and when single-chip microcomputer is to CPLD read access, read-write is high level, and chip selection signal is low level, and single-chip microcomputer completes a Flash read access according to following steps:
C201: single-chip microcomputer is sent 31 ~ 24 of the Flash address of 8 that need access by the ADDR4 address register of custom programming device interface to CPLD and latched;
C202: single-chip microcomputer is sent 23 ~ 16 of the Flash address of 8 that need access by the ADDR3 address register of custom programming device interface to CPLD and latched;
C203: single-chip microcomputer is sent 15 ~ 8 of the Flash address of 8 that need access by the ADDR2 address register of custom programming device interface to CPLD and latched;
C204: single-chip microcomputer is sent 7 ~ 0 of the Flash address of 8 that need access by the ADDR1 address register of custom programming device interface to CPLD and latched;
C205: single-chip microcomputer by custom programming device interface to CPLD read trigger address register write arbitrary value, trigger the control signal that CPLD accesses Flash, the Flash address of 8 of latching in ADDR4 address register, ADDR3 address register, ADDR2 address register and ADDR1 address register is sent to Flash by CPLD, Flash by the storage data of appropriate address, in the DATA2 data register being sent to CPLD and DATA1 data register;
C206: single-chip microcomputer reads and stores the data of DATA2 data register;
C207: single-chip microcomputer reads and stores the data of DATA1 data register;
Whether D, single-chip microcomputer judge the read and write access of Flash successful, if so, then read and write access successful information is back to desktop application software, otherwise read and write access failure information is back to desktop application software.
6. the implementation method of Flash online programming on circuit board as claimed in claim 5, is characterized in that: described operational order comprises scanning Flash instruction, erasing Flash instruction, programming Flash instruction and verification Flash instruction; When described operational order is for erasing Flash instruction, corresponding programming data is the length of Flash erase area and the start address of write Flash; When described operational order is for programming Flash instruction, the data file of corresponding programming data needed for programming Flash, the length of data file and the start address of write Flash; When described operational order is for verification Flash instruction, data file, the length of data file and the start address of Flash of corresponding programming data needed for verification Flash.
7. the implementation method of Flash online programming on circuit board as claimed in claim 5, is characterized in that: the address register of ADDR4 described in step C is positioned at the 3b000 address place of CPLD internal circuit; Described ADDR3 address register is positioned at the 3b001 address place of CPLD internal circuit; Described ADDR2 address register is positioned at the 3b010 address place of CPLD internal circuit; Described ADDR1 address register is positioned at the 3b011 address place of CPLD internal circuit; Described DATA2 data register is positioned at the 3b100 address place of CPLD internal circuit; Described DATA1 data register is positioned at the 3b101 address place of CPLD internal circuit; Described trigger address register-bit of writing is in the 3b110 address place of CPLD internal circuit; Described trigger address register-bit of reading is in the 3b110 address place of CPLD internal circuit.
8. the implementation method of Flash online programming on the circuit board as described in any one of claim 5 to 7, it is characterized in that, single-chip microcomputer described in step D judges to comprise the whether successful step of the read and write access of Flash: single-chip microcomputer reads the status register bit of Flash, single-chip microcomputer judges the numerical value whether right value of the status register bit of the Flash read, if, then read and write access success, otherwise read and write access failure.
9. the implementation method of Flash online programming on the circuit board as described in any one of claim 5 to 7, it is characterized in that, the step in step D, read and write access successful information being back to desktop application software comprises: successful for read and write access information is packaged into self-defined frame format packet according to self-defined frame format by single-chip microcomputer, and self-defined frame format Packet Generation is turned FIFO protocol converter to USB by fifo interface by single-chip microcomputer; USB turns FIFO protocol converter and self-defined frame format packet is resolved to usb data bag and is sent to desktop application software; The USB bottom layer driving of desktop application software becomes self-defined frame format packet to usb data Packet analyzing, and the self-defined frame format packet of desktop application software parses, obtains the successful data of read and write access, informs user operation success.
10. the implementation method of Flash online programming on the circuit board as described in any one of claim 5 to 7, it is characterized in that, the step in step D, read and write access failure information being back to desktop application software comprises: the information of read and write access failure is packaged into self-defined frame format packet according to self-defined frame format by single-chip microcomputer, and self-defined frame format Packet Generation is turned FIFO protocol converter to USB by fifo interface by single-chip microcomputer; USB turns FIFO protocol converter and self-defined frame format packet is resolved to usb data bag and is sent to desktop application software; The USB bottom layer driving of desktop application software becomes self-defined frame format packet to usb data Packet analyzing, and the self-defined frame format packet of desktop application software parses, obtains the data of read and write access failure, informs user operation failure.
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| US5889701A (en) * | 1998-06-18 | 1999-03-30 | Xilinx, Inc. | Method and apparatus for selecting optimum levels for in-system programmable charge pumps |
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