CN103365815B - The SD memory card interface that under support SD pattern, IP realizes - Google Patents
The SD memory card interface that under support SD pattern, IP realizes Download PDFInfo
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- CN103365815B CN103365815B CN201310262993.5A CN201310262993A CN103365815B CN 103365815 B CN103365815 B CN 103365815B CN 201310262993 A CN201310262993 A CN 201310262993A CN 103365815 B CN103365815 B CN 103365815B
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Abstract
A kind of SD memory card interface supporting that IP realizes under SD pattern, be connected between master control system and Flash controller, read-write operation can be carried out to Flash, comprise: order transceiver module, be responsible for receiving master control order and resolved to SD card command, be sent to status control module and correction verification module, and the respond style provided according to status control module produces corresponding response contents replys; Data transmit-receive module, is responsible for reception and the transmission of data; Status control module, is responsible for Interface status and controls; Correction verification module, be responsible for the completeness check of order and data, the present invention supports the basic command of SD2.0 physical layer specification, automatically can resolve the order of main frame transmission and respond, in order to the sequence problem solving data access employs Data cache technology, the present invention can transplant easily under different integrated circuit technology, and can run in FPGA platform, be applied in easily in SOC, decrease design cost and R&D cycle.
Description
Technical field
The present invention relates to the interfacing field in the design of embedded SOC, refer more particularly to SD card interface technology, be specifically related to a kind of SD memory card interface supporting that IP realizes under SD pattern.
Background technology
Along with the widespread use of portable digital product, increasing to the demand of Nonvolatile memory card in consumer-elcetronics devices.Nonvolatile memory card comprises SD (SecureDigital) card, mmc card, CF card memory stick etc.Wherein SD jig has high memory capacity, rapid data transmission rate, and great mobile dirigibility and well security, the feature that cost is relatively cheap, is therefore widely used on the video/audio equipment such as PC, camera, mobile phone.SD card is the abbreviation of " safe digital storage card ", is succeeded in developing in August, 1999 by SanDisk company of the U.S., Japanese Toshiba and PANASONIC joint development.In order to ensure the compatibility of the SD card that different manufacturers designs, formulated SD card standard communication protocol, pin distributes, electrical specification etc.From scale and the trend of whole market, the range of application of SD card is wide, and development space is very large, and the equipment with SD interface can be applied to every field more easily, and the design and development of SD interface also becomes hot issue.
Design in the market for SD card controller is more, but little for the design of SD card interface.And Flash chip wide variety, is difficult to the design Storage realizing versatility at present.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of SD memory card interface supporting that IP realizes under SD pattern, meeting SD standard, data read-write operation can be completed under SD main control equipment, and there is stronger dirigibility.
To achieve these goals, the technical solution used in the present invention is:
The SD memory card interface that under support SD pattern, IP realizes, is connected between master control system and Flash controller, comprises:
Order transceiver module, comprise order receiver module and command response module, order receiver module receives master control order and is resolved to SD card command, be sent to status control module and correction verification module, command response module produces corresponding response contents according to the respond style that status control module provides and replys;
Data transmit-receive module, comprises data reception module and data transmission blocks, and data reception module is responsible for the reception of data, and data transmission blocks is responsible for the transmission of data;
Status control module, is responsible for Interface status and controls;
Correction verification module, comprises the command checksum module being arranged at and being responsible for order completeness check between order receiver module and command response module and the data check module being arranged at responsible order completeness check between data reception module and data transmission blocks.
Described order transceiver module receives the standard commands from SD card Physical layer, parsing obtains 6 order of the bit indexes, 32 order of the bit parameters and CRC7 check bit, the parameter obtained is passed to status control module and correction verification module, according to the respond style that status control module provides during response, produce corresponding response contents, then send.
Described response contents comprises R1, R1b, R2, R3, R6, R7 six kinds, and wherein R1, R1b, R3, R6, R7 are 6 byte lengths, and R2 is 17 byte lengths, for reading the CID/CSD content of registers of SD card.
The order numbering that described status control module transmits according to order transceiver module produces command response type corresponding with it, the command parameter that further resolve command transceiver module transmits.
Described correction verification module comprises CRC7 command checksum module and CRC16 data check module, the command and response in CRC7 command checksum module in charge check command transceiver module; Data in CRC16 data check module in charge checking data transceiver module.
Data receiver buffer unit and data transmission buffer unit is provided with in described data transmit-receive module.
Described SD data transmission is in units of block, each piece is always made up of data start bit, data bit, CRC16 check bit sum ED position, data transmit-receive module receives according to the form of data block when receiving data, and data are deposited in data receiver buffer unit, data to be sent are first written to data and send in buffer unit by data when sending, then send according to same form.
Bit wide 16 bit of described data buffering, the degree of depth is 256.
Compared with prior art, the present invention can complete parsing to master control order and response, completes the data transmission between master control system and Flash, and, make it possible to transplant easily under different integrated circuit technology based on this structure, decrease design cost and R&D cycle.
Accompanying drawing explanation
Fig. 1 is the one-piece construction circuit diagram according to one embodiment of the present invention.
Fig. 2 is the order transmission circuit figure according to one embodiment of the present invention.
Fig. 3 is the data transmit-receive circuit diagram according to one embodiment of the present invention.
Fig. 4 is the state control circuit figure according to one embodiment of the present invention.
Embodiment
Embodiments of the present invention are described in detail below in conjunction with drawings and Examples.
As shown in Figure 1, SD memory card interface of the present invention, is connected between master control system and Flash controller, comprises: order transceiver module, data transmit-receive module, status control module and correction verification module.Wherein order transceiver module, data transmit-receive module and status control module are all connected to the top-level module of master control system.Order transceiver module comprises order receiver module and command response module, data transmit-receive module comprises data reception module and data transmission blocks, correction verification module comprises data check module and command checksum module, data check model calling carries out data integrity verifying between data reception module and data transmission blocks, and command checksum model calling carries out order completeness check between order receiver module and command response module.Data reception module connection data receives buffer unit and carries out buffer memory to reception data, and data transmission blocks connection data sends buffer unit and carries out buffer memory to transmission data.
As shown in Figure 2, the order of order transceiver module of the present invention receives and responds to send all to be transmitted on order wire CMD, so this port is a triple gate, whether its enable termination controller, controlled to export by output enable signal En.Controller is connected to the second counter and the second shift register, and the second shift register connects the second register and provides input by it to triple gate.The output of triple gate connects a start bit detecting unit, and start bit detecting unit connects the first counter, the first shift register and the first register, and the first counter is connected to a comparer.When order receives, start bit detecting unit first sense command start bit, provides Start1 signal and the first counter is started working after start bit being detected.According to the judgement of comparer, when receiving a complete order, sending receipt completion signal End, obtaining command index Ind, command parameter Arg corresponding in the first shift register and command checksum Crc7 respectively.In order receiving course, data dCrc7 is passed to CRC7 correction verification module, for generating checking data simultaneously.When response sends, produce corresponding response contents according to the respond style Rsp_type that status control module provides, after receiving transmission enable signal Start2, provide and send enable signal En, and the content of response is sent by the second shift register.Response settling signal Rsp_over is provided after response contents is sent completely.
As shown in Figure 3, the data line of data transmit-receive module of the present invention is two-way, wherein data transmission blocks comprises a controller with counter, this controller connects data by the 4th shift register and sends buffer unit, data reception module also comprises a controller with counter, and this controller connects data receiver buffer unit by the 3rd shift register.It is STD bus pattern or width bus pattern that Width signal indicates present data transmission pattern.The byte number that each data block of Size signal designation comprises.This module comprises two data bufferings, and receive buffering RxFIFO and send buffering TrFIFO, data buffering bit wide 16 bit, the degree of depth is 256, this is because data block is 512 bytes to the maximum.During data receiving state, first detect data start bit, after start bit being detected, counter is started working.After receiving the data of Size byte, receive CRC16 check bit, finally complete data block reception, send receipt completion signal End.In DRP data reception process, often receive 16 bit data and provide write signal Wr, data are write RxFIFO.If RxFIFO is full, provide Busy signal, main frame enters data and sends wait.When data send state, after reception controller receives Start3 signal, start to send Rd signal-obtaining TrFIFO data, and data are passed to shift register, enable data exports control signal Out_en, and data export according to data-transmission mode by shift register.
As shown in Figure 4, status control module: produce command response type corresponding with it according to the order numbering that receiver module transmits, resolve the command parameter that receiver module transmits further.The course of work has 9 states.All idle condition IDLE can be entered into from other state after receiving CMD0 order.After receiving acmd41 order, module enters READY state, enters IDENT state after receiving cmd2, enters STBY state after receiving cmd3, now completes initialization and the identifying of card.Next receive cmd7 order and enter data transmission TRAN state.Under this state, receive data write order cmd24, cmd25 etc. and then enter data receiver RCV state, wait-receiving mode data.Finish receiving, enter data write PROG state, under this state, the data of data receiver buffer memory are written in Flash.Data transmission TRAN state is got back to after completing data write; Under this state, receive data read command cmd17, cmd18 etc. and then enter digital independent DATA state, data in Flash are first written to data to send in buffering, then send to main control module by interface, complete after data send and turn back to data transmission TRAN state.
Correction verification module: CRC7 is responsible for the command and response in check command transceiver module.Crc7 in order transceiver module is connected with the data input pin of this module, as the data-in port of correction verification module; CRC16 is responsible for the data in checking data transceiver module, has four data correction verification modules, and when the correction verification module work for being wherein connected with DAT0 during 1 bit pattern, when being 4 bit pattern, four data correction verification modules work simultaneously.
The design Verilog carries out FPGA simulating, verifying, the reliability and feasibility of checking SD interface.Carry out comprehensively and download in fpga chip verifying based on AlteraFPGACycloneII Series FPGA, after being connected with computer, SD storage card can be identified as.Thus prove that the design is correct in feasible.
Above embodiment is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (7)
1. the SD memory card interface that under support SD pattern, IP realizes, is connected between master control system and Flash controller, it is characterized in that, comprising:
Order transceiver module, comprise order receiver module and command response module, order receiver module receives master control order and is resolved to SD card command, be sent to status control module and correction verification module, command response module produces corresponding response contents according to the respond style that status control module provides and replys;
Data transmit-receive module, comprises data reception module and data transmission blocks, and data reception module is responsible for the reception of data, and data transmission blocks is responsible for the transmission of data;
Status control module, is responsible for Interface status and controls;
Correction verification module, comprises the command checksum module being arranged at and being responsible for order completeness check between order receiver module and command response module and the data check module being arranged at responsible data integrity verifying between data reception module and data transmission blocks;
Described order transceiver module receives the standard commands from SD card Physical layer, parsing obtains 6 order of the bit indexes, 32 order of the bit parameters and CRC7 check bit, the parameter obtained is passed to status control module and correction verification module, according to the respond style that status control module provides during response, produce corresponding response contents, then send.
2. the SD memory card interface that under support SD pattern according to claim 1, IP realizes, it is characterized in that, described response contents comprises R1, R1b, R2, R3, R6, R7 six kinds, wherein R1, R1b, R3, R6, R7 are 6 byte lengths, R2 is 17 byte lengths, for reading the CID/CSD content of registers of SD card.
3. the SD memory card interface that under support SD pattern according to claim 1, IP realizes, it is characterized in that, the order numbering that described status control module transmits according to order transceiver module produces command response type corresponding with it, the command parameter that further resolve command transceiver module transmits.
4. the SD memory card interface that under support SD pattern according to claim 1, IP realizes, it is characterized in that, described correction verification module comprises CRC7 command checksum module and CRC16 data check module, the command and response in CRC7 command checksum module in charge check command transceiver module; Data in CRC16 data check module in charge checking data transceiver module.
5. the SD memory card interface that under support SD pattern according to claim 1, IP realizes, is characterized in that, is provided with data receiver buffer unit and data transmission buffer unit in described data transmit-receive module.
6. the SD memory card interface that under support SD pattern according to claim 5, IP realizes, it is characterized in that, described SD data transmission is in units of block, each piece is always made up of data start bit, data bit, CRC16 check bit sum ED position, data transmit-receive module receives according to the form of data block when receiving data, and data are deposited in data receiver buffer unit, data to be sent are first written to data and send in buffer unit by data when sending, then send according to same form.
7. the SD memory card interface that under support SD pattern according to claim 6, IP realizes, it is characterized in that, bit wide 16 bit of described data buffering, the degree of depth is 256.
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| CN103544079B (en) * | 2013-10-28 | 2017-02-01 | 公安部第三研究所 | Flash memory chip data recovery achieving system and method based on programmable logic controller |
| US9477549B2 (en) | 2014-09-15 | 2016-10-25 | Sandisk Technologies Llc | Methods, systems, and computer readable media for address and data integrity checking in flash memory operations |
| CN106897236A (en) * | 2015-12-17 | 2017-06-27 | 龙芯中科技术有限公司 | Method, device and SD card model with SD card console controller information exchange |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101266538A (en) * | 2008-05-06 | 2008-09-17 | 普天信息技术研究院有限公司 | Intelligent memory card interface access control method |
| CN102135859A (en) * | 2010-01-22 | 2011-07-27 | 智多星电子科技有限公司 | Flash memory card used for transmitting differential data |
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| KR101616100B1 (en) * | 2009-09-25 | 2016-04-28 | 삼성전자주식회사 | Memory system and operation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101266538A (en) * | 2008-05-06 | 2008-09-17 | 普天信息技术研究院有限公司 | Intelligent memory card interface access control method |
| CN102135859A (en) * | 2010-01-22 | 2011-07-27 | 智多星电子科技有限公司 | Flash memory card used for transmitting differential data |
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