CN103353557A - Main transformer protection tripping matrix exit auxiliary tester - Google Patents
Main transformer protection tripping matrix exit auxiliary tester Download PDFInfo
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- CN103353557A CN103353557A CN 201310223272 CN201310223272A CN103353557A CN 103353557 A CN103353557 A CN 103353557A CN 201310223272 CN201310223272 CN 201310223272 CN 201310223272 A CN201310223272 A CN 201310223272A CN 103353557 A CN103353557 A CN 103353557A
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- 230000004224 protection Effects 0.000 title claims abstract description 54
- 239000011159 matrix material Substances 0.000 title claims abstract description 24
- 238000001514 detection method Methods 0.000 claims abstract description 38
- 238000012360 testing method Methods 0.000 claims abstract description 14
- 239000004973 liquid crystal related substance Substances 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 9
- 101100028092 Drosophila melanogaster Or22a gene Proteins 0.000 claims description 6
- 101100028093 Drosophila melanogaster Or22b gene Proteins 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 6
- 101001057156 Homo sapiens Melanoma-associated antigen C2 Proteins 0.000 claims description 2
- 102100027252 Melanoma-associated antigen C2 Human genes 0.000 claims description 2
- 230000035945 sensitivity Effects 0.000 abstract 1
- 238000007689 inspection Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000012795 verification Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012905 input function Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
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Abstract
The invention relates to a main transformer protection tripping matrix exit auxiliary tester comprising a direct-current power supply VCC, a power switch K1, a time switch K2, an operation indicating lamp, ten detection and sound-light alarm circuits which are same in structure and ten time recording and displaying circuits which are same in structure, wherein the operation indicating lamp is connected with the direct-current power supply VCC through the power switch K1; the input terminals of the detection and sound-light alarm circuits are respectively connected with the lower opening corresponding ends of a tripping plate of a relay protection device to be tested; the power terminals of the detection and sound-light alarm circuits are connected with the direct-current power supply VCC through the power switch K1; the input terminals of the time recording and displaying circuits are respectively connected with a pair of dry contacts of a relay protection test bed; and the power terminals of the time recording and displaying circuits pass through the time switch K2 and the power switch K1 in sequence and then is connected with the direct-current power supply VCC. The advantages of the auxiliary tester are that: accuracy and sensitivity of the detection are high; and operation is safe, rapid, easy and feasible.
Description
Technical field
The present invention relates to a kind of main transformer protection Tripping matrix outlet assisted tester, be applicable to main transformer protection capital construction examination and the work for inspection of relay protection specialty.
Background technology
At present; the relay protection specialty is in carrying out main transformer protection capital construction examination and one-hundred-percent inspection work; especially for the 500kV Ultra-high Voltage Substations; face the multiple principle Backup Protections such as high, medium and low voltage side and public winding four partial earths distance, phase to phase impedance, zero sequence direction, zero sequence overcurrent; the back-up protection of each each principle of side divides again three sections of I, II, III; every section is divided again 1,2,3 three time limit, and this has just consisted of the Tripping matrix logic of main transformer protection.Because the configuration of relay protection dual, 1 main-transformer has 2 cover main transformer protections, nearly 200 kinds of all trip protection logics.In the protection check, if 200 kinds of logic complete verifications are complete, need the fault of each logic of simulation, and measure simultaneously all tripping operation output clampings.At least need 2 people, Yi Bian add the fault simulation amount, measure one by one more than 10 output clamping Yi Bian hold multimeter, consuming time more.In the face of the larger verification of this workload, present stage just continues to use side classification, segmentation in traditional minute and divides time limit, the logic out-of-date methods checked successively of pressing plate one by one one by one, this frequency repeatability operation not only expends a large amount of manpowers, time, and it is not directly perceived, cause easily fatigue to make mistakes, have a strong impact on repair schedule and efficient.
If adopt the reaying protection test platform, such as the equipment of the rich electricity in Beijing, Guangzhou Onlly etc., it just possesses 8 dry contact input functions; and in the situation of main transformer maintenance prerun; the upper and lower port of pressing plate is charged, and voltage suitable for reading is-110V that end opening voltage is+110V.For the consideration of safety practice, do not advise that the cutting-off controlling power supply overhauls prerun.So conventional reaying protection test platform is not suitable for measuring the output pulse of charged pressing plate, in working at ordinary times, still generally adopt the artificial hand-held multimeter of wasting time and energy to detect the method for pressing plate outlet.
Summary of the invention
Technical matters to be solved by this invention provide a kind of safe and efficient, simple, measure accurately main transformer protection Tripping matrix outlet assisted tester.
Be a kind of main transformer protection Tripping matrix outlet assisted tester for solving the problems of the technologies described above the technical scheme of taking, comprise direct supply VCC, power switch K1, time switch K2, run indicator, detection and sound light alarming circuit time timing and the display circuit identical with 10 line structures that 10 line structures are identical; Described run indicator meets direct supply VCC through power switch K1; The input end of described detection and sound light alarming circuit connects respectively the trip pressing plate end opening corresponding end of detected protective relaying device; The power end of described detection and sound light alarming circuit meets direct supply VCC through power switch K1; The input end of described time timing and display circuit is succeeded respectively a pair of dry contact of electric protection testing table; The power end of described time timing and display circuit meets direct supply VCC through time switch K2, power switch K1 successively.
The beneficial effect that adopts technique scheme to produce is:
(1) this tester can be in situation about not having a power failure; once detect simultaneously 10 tripping operation outlets, avoided protection action, switch transmission number of times, prevent frequent deciliter damage that causes of switch; remove switch from and suppress the stand-by period, shortened the time of main transformer protection maintenance prerun.
(2) wiring of this tester is safe and efficient, simple; the work for inspection that in the past need to just can be finished half a day by two people; at present can be by people's complete independently in 2h; save the work that people's conjunction measuring output clamping need to be arranged when protective relaying device passes into the fault simulation amount, greatly alleviated the workload that each pressing plate is in the past measured one by one.
(3) this tester provides sound and light of alarm, can by sound and light alarm as prompting, make work for inspection more directly perceived, efficient.
(4) this tester provides 10 independent timing Presentation Functions of passage tripping operation outlet; totally four of timing digital displays; such as 00.00; timing least unit 0.01s; timing range 0.01～99.99s; it more accurate recording protection action further accurately verify the correctness of transformer tripping matrix to the time of tripping operation outlet.
(5) this tester is measured accurately; highly sensitive; be not only applicable to the verification of main transformer protection Tripping matrix logic; also be applicable to the work for inspection of a plurality of device tripping operation such as bus protection, route protection, breaker protection outlet; it overhauls at the scene and has also obtained good application in the prerun process, and overall inspection progress and the efficient of relay protection of power system are improved.
Description of drawings
Fig. 1 is theory diagram of the present invention;
Fig. 2 is detection of the present invention and sound light alarming circuit schematic diagram;
Fig. 3 is time timing of the present invention and displaying principle block diagram;
Fig. 4 is time timing of the present invention and display circuit schematic diagram.
Embodiment
By the embodiment shown in Fig. 1-4 as can be known, the present invention includes direct supply VCC, power switch K1, time switch K2, run indicator, detection and sound light alarming circuit time timing and the display circuit identical with 10 line structures that 10 line structures are identical; Described run indicator meets direct supply VCC through power switch K1; The input end of described detection and sound light alarming circuit connects respectively the trip pressing plate end opening corresponding end of detected protective relaying device; The power end of described detection and sound light alarming circuit meets direct supply VCC through power switch K1; The input end of described time timing and display circuit is succeeded respectively a pair of dry contact of electric protection testing table; The power end of described time timing and display circuit meets direct supply VCC through time switch K2, power switch K1 successively.
Described the 1 tunnel detection and sound light alarming circuit are comprised of detection contact CT1, diode D11, light emitting diode D12, triode VT11, triode VT12, variable resistor RW1, current-limiting resistance R1 and hummer HA; The trip pressing plate end opening corresponding end of the detected protective relaying device of the termination of described detection contact CT1; The other end of described detection contact CT1 connects the base stage of triode VT11 successively through diode D11, variable resistor RW1; The collector of described triode VT11 connects the M1 end of hummer; The emitter of described triode VT11 connects the base stage of triode VT12; The grounded emitter of described triode VT12; Between the M2 end of described light emitting diode D12 and the collector that is connected on triode VT12 after current-limiting resistance R1 connects and hummer HA; The M1 end of described hummer HA meets direct supply VCC through power switch K1; Described hummer HA is that 10 tunnel detections and sound light alarming circuit share;
Described the 10 tunnel detection and sound light alarming circuit are comprised of detection contact CT10, diode D101, light emitting diode D102, triode VT101, triode VT102, variable resistor RW10, current-limiting resistance R10 and hummer HA.
Described the 1 tunnel time timing and display circuit by multi-resonant oscillating circuit, when record button AN11, timing circuit and display circuit form; The input end of described multi-resonant oscillating circuit is succeeded a pair of dry contact of electric protection testing table; The output terminal of described multi-resonant oscillating circuit successively through when record button AN11, timing circuit connect the input end of display circuit.
Described multi-resonant oscillating circuit is comprised of integrated package U11, resistance R 11-R12, capacitor C 11-C12 and input trigger terminal T11-T12; Described input trigger terminal T11-T12 succeeds respectively a pair of dry contact of electric protection testing table, and described input trigger terminal T12 meets direct supply VCC through time switch K2, power switch K1 successively; 4 pin of described integrated package U11 and 8 pin meet respectively input trigger terminal T11; Described resistance R 11 be connected between 6 pin and 8 pin of integrated package U11 after R12 connects; The 7 pin connecting resistance R11 of described integrated package U11 and the node of resistance R 12; 2 pin of described integrated package U11 are connected with 6 pin, and through capacitor C 11 ground connection; The 5 foot meridian capacitor C12 ground connection of described integrated package U11; The 1 pin ground connection of described integrated package U11.
Described timing circuit comprises counter U12, counter U13 and zero setting button AN12; Described display circuit comprises integrated package U14-U17 and seven segment liquid crystal digitron L11-L14;
9 pin of described counter U13 button AN11 when record connects output terminal 3 pin of integrated package U11; 9 pin of described counter U12 connect 6 pin of counter U13; 1 pin of described counter U12-U13 connects 14 pin;
16 pin of described counter U12 and 16 pin of described counter U13,10 pin meet direct supply VCC through time switch K2, power switch K1 successively; 2 pin of 2 pin of described counter U12,8 pin, 10 pin and described counter U13,8 pin ground connection; The normally opened contact N1 of described zero setting button AN12 meets direct supply VCC through time switch K2, power switch K1 successively; 7 pin of described counter U12-U13,15 pin are through the normally closed contact N2 of zero setting button AN12 ground connection;
The 3-6 pin of described counter U12 meets respectively the input end A-D of integrated package U14; The 11-14 pin of described counter U12 meets respectively the input end A-D of integrated package U15; The 3-6 pin of described counter U13 meets respectively the input end A-D of integrated package U16; The 11-14 pin of described counter U13 meets respectively integrated package U17 input end A-D;
The 3-5 pin of described integrated package U14-U17,16 pin meet direct supply VCC through time switch K2, power switch K1 successively; The 8 pin ground connection of described integrated package U14-U17; The output terminal a-g of described integrated package U14-U17 meets respectively the input end A-G of seven segment liquid crystal digitron L11-L14;
The model of described integrated package U11 is 555 chips.
The model of described counter U12-U13 is CD4518.
The model of described integrated package U14-U17 is 74LS48.
The model of described seven segment liquid crystal digitron L11-L14 is R5011A.
The ground of present embodiment is grounding copper bar.
The course of work of present embodiment is as follows:
Before the work of main transformer protection Tripping matrix outlet assisted tester, first with its ground connection, ground is grounding copper bar, and the safety of assurance equipment and the person provides galvanic reference potential on the other hand on the one hand.Then the input trigger terminal T11-T12 with main transformer protection Tripping matrix outlet assisted tester is connected to a pair of dry contact of reaying protection test platform; and 10 detection contact are connected to the detected corresponding trip pressing plate end opening of protective relaying device, this has just finished the detection wiring.After power switch K1 closure, the run indicator conducting, the direct supply of bright explanation 10 tunnel detections of pilot lamp and sound light alarming circuit and time timing and display circuit is normal.Again timing button K2 is pressed, the power end of every road time timing and display circuit is connected VCC, the liquid crystal digital display tube of the timing of 10 tunnel times and display circuit all begins displaying time, press successively the zero setting button of each time timing and display circuit, 15 pin of all counters are the zero setting position, high level after triggering makes zero the liquid crystal digital display tube time, and it all is 0 that the 4-digit number of every road time timing and display circuit shows.This has just finished and has detected the front preparation of test.
When adding the fault simulation amount for detected protective relaying device; the a pair of dry contact of reaying protection test platform is closed simultaneously; input trigger terminal T11-T12 by main transformer protection Tripping matrix outlet assisted tester starts the if having time clocking capability of timing and display circuit of institute; each 555 chip is started working; the time of all liquid crystal digital display tubes begins timing from 00.00s, accuracy of timekeeping 0.01s.When detecting voltage, a certain detection and sound light alarming circuit be+110V, time when being the instantaneous voltage pulse of several ms; the conducting that is triggered of the transistor of this branch road; detect and the sound light alarming circuit connection; alarm lamp is bright; hummer HA sends " dripping---" one; button during record that the staff presses rapidly corresponding time timing and display circuit; 555 chip outputs, 3 pin are disconnected; the time timing stops immediately; the protection action trip time is recorded on the corresponding liquid crystal digital display tube, and timing error is 0.01s.The circuit that other pressing plate end openings do not detect potential pulse then continues timing, the normal operation of 555 chips, until corresponding detect and sound light alarming circuit detects size and is+110V, time when being the potential pulse of several ms, after the triode conducting of this detection and sound light alarming circuit, send sound and light alarm, the button during record of pressing rapidly more corresponding time timing and display circuit then records and shows tripping operation outlet time of this test channel.In the course of the work, if press " the zero setting button " of corresponding time timing and display circuit, then the demonstration of the liquid crystal digital display tube of this circuit is made zero.
A CD4518 chip can show 2 tens digits, because the present embodiment timing range is 00.00～99.99s, needs 2 CD4518 chip cascades, is aided with some logic gates again, jointly finishes corresponding carry and zero setting function.
The every 10ms run-down of liquid crystal digital display tube.
The operating ambient temperature of present embodiment :-10～50 ℃, during normal operation, consumed power≤40W.In addition, the insulation resistance 〉=50M of main transformer protection Tripping matrix outlet assisted tester
, the forceful electric power loop can be born ± the 250V voltge surge, and weak electrical loop can be born the voltge surge of 50V.
This tester possesses 4 technical standards:
(1) security performance.Article 10, branch road works alone, and isolation the crosstalk phenomenon can not occur mutually.Detection voltage is forceful electric power; can not cause the short circuit with ground wire; yet can not interfere with each other, be connected in series with light current; guarantee between the forceful electric power, between the forceful electric power light current, the isolation between forceful electric power and the ground wire, more can not advance detected protective relaying device to main transformer protection Tripping matrix outlet assisted tester power supply foldback.
(2) detect voltage request.Detection contact can be replaced wire clamp contact, U-shaped contact, pin hole contact (universal), to adapt to the upper and lower opening of variety classes pressing plate.When detection voltage is direct current 30～110V, can drive detection and sound light alarming circuit and time timing and display circuit.When the voltage that detects＜30V, detection and sound light alarming circuit and time timing and not conducting of display circuit detect voltage and can escape reliably 30V and following.
(3) time precision requirement.The time showing scope is 00.00～99.99s, and precision is 0.01s, and error is ± 0.01s that catching the time precision that detects potential pulse is 1ms.
(4) power switch is for to open with the automatic trip sky of currents match, and electric power loop also arranges sizeable current fusing silk (device), and the personnel of preventing injure and install overcurrent and burn.
Claims (10)
1. main transformer protection Tripping matrix outlet assisted tester is characterized in that: comprise direct supply VCC, power switch K1, time switch K2, detection and sound light alarming circuit time timing and the display circuit identical with 10 line structures that 10 line structures are identical; The input end of described detection and sound light alarming circuit connects respectively the trip pressing plate end opening corresponding end of detected protective relaying device; The power end of described detection and sound light alarming circuit meets direct supply VCC through power switch K1; The input end of described time timing and display circuit is succeeded respectively a pair of dry contact of electric protection testing table; The power end of described time timing and display circuit meets direct supply VCC through time switch K2, power switch K1 successively.
2. main transformer protection Tripping matrix according to claim 1 exports assisted tester, and it is characterized in that: also comprise run indicator, described run indicator meets direct supply VCC through power switch K1.
3. main transformer protection Tripping matrix according to claim 2 exports assisted tester, it is characterized in that: described the 1 tunnel detection and sound light alarming circuit are comprised of detection contact CT1, diode D11, light emitting diode D12, triode VT11, triode VT12, variable resistor RW1, current-limiting resistance R1 and hummer HA; The trip pressing plate end opening corresponding end of the detected protective relaying device of the termination of described detection contact CT1; The other end of described detection contact CT1 connects the base stage of triode VT11 successively through diode D11, variable resistor RW1; The collector of described triode VT11 connects the M1 end of hummer; The emitter of described triode VT11 connects the base stage of triode VT12; The grounded emitter of described triode VT12; Between the M2 end of described light emitting diode D12 and the collector that is connected on triode VT12 after current-limiting resistance R1 connects and hummer HA; The M1 end of described hummer HA meets direct supply VCC through power switch K1; Described hummer HA is that 10 tunnel detections and sound light alarming circuit share;
Described the 10 tunnel detection and sound light alarming circuit are comprised of detection contact CT10, diode D101, light emitting diode D102, triode VT101, triode VT102, variable resistor RW10, current-limiting resistance R10 and hummer HA.
4. main transformer protection Tripping matrix according to claim 3 outlet assisted tester is characterized in that: described the 1 tunnel time timing and display circuit during by multi-resonant oscillating circuit, record button AN11, timing circuit and display circuit form; The input end of described multi-resonant oscillating circuit is succeeded a pair of dry contact of electric protection testing table; The output terminal of described multi-resonant oscillating circuit successively through when record button AN11, timing circuit connect the input end of display circuit.
5. main transformer protection Tripping matrix according to claim 4 exports assisted tester, it is characterized in that: described multi-resonant oscillating circuit is comprised of integrated package U11, resistance R 11-R12, capacitor C 11-C12 and input trigger terminal T11-T12; Described input trigger terminal T11-T12 succeeds respectively a pair of dry contact of electric protection testing table, and described input trigger terminal T12 meets direct supply VCC through time switch K2, power switch K1 successively; 4 pin of described integrated package U11 and 8 pin meet respectively input trigger terminal T11; Described resistance R 11 be connected between 6 pin and 8 pin of integrated package U11 after R12 connects; The 7 pin connecting resistance R11 of described integrated package U11 and the node of resistance R 12; 2 pin of described integrated package U11 are connected with 6 pin, and through capacitor C 11 ground connection; The 5 foot meridian capacitor C12 ground connection of described integrated package U11; The 1 pin ground connection of described integrated package U11.
6. main transformer protection Tripping matrix according to claim 5 exports assisted tester, it is characterized in that:
Described timing circuit comprises counter U12, counter U13 and zero setting button AN12; Described display circuit comprises integrated package U14-U17 and seven segment liquid crystal digitron L11-L14;
9 pin of described counter U13 button AN11 when record connects output terminal 3 pin of integrated package U11; 9 pin of described counter U12 connect 6 pin of counter U13; 1 pin of described counter U12-U13 connects 14 pin;
16 pin of described counter U12 and 16 pin of described counter U13,10 pin meet direct supply VCC through time switch K2, power switch K1 successively; 2 pin of 2 pin of described counter U12,8 pin, 10 pin and described counter U13,8 pin ground connection; The normally opened contact N1 of described zero setting button AN12 meets direct supply VCC through time switch K2, power switch K1 successively; 7 pin of described counter U12-U13,15 pin are through the normally closed contact N2 of zero setting button AN12 ground connection;
The 3-6 pin of described counter U12 meets respectively the input end A-D of integrated package U14; The 11-14 pin of described counter U12 meets respectively the input end A-D of integrated package U15; The 3-6 pin of described counter U13 meets respectively the input end A-D of integrated package U16; The 11-14 pin of described counter U13 meets respectively integrated package U17 input end A-D;
The 3-5 pin of described integrated package U14-U17,16 pin meet direct supply VCC through time switch K2, power switch K1 successively; The 8 pin ground connection of described integrated package U14-U17; The output terminal a-g of described integrated package U14-U17 meets respectively the input end A-G of seven segment liquid crystal digitron L11-L14;
Common port 3 pin of described seven segment liquid crystal digitron L11-L14,8 pin ground connection; 5 pin of described seven segment liquid crystal digitron L12 meet direct supply VCC through time switch K2, power switch K1 successively.
7. main transformer protection Tripping matrix according to claim 6 exports assisted tester, and it is characterized in that: the model of described integrated package U11 is 555 chips.
8. main transformer protection Tripping matrix according to claim 7 exports assisted tester, and it is characterized in that: the model of described counter U12-U13 is CD4518.
9. main transformer protection Tripping matrix according to claim 8 exports assisted tester, and it is characterized in that: the model of described integrated package U14-U17 is 74LS48.
10. main transformer protection Tripping matrix according to claim 9 exports assisted tester, and it is characterized in that: the model of described seven segment liquid crystal digitron L11-L14 is R5011A.
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| CN 201310223272 CN103353557A (en) | 2013-06-06 | 2013-06-06 | Main transformer protection tripping matrix exit auxiliary tester |
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| CN 201310223272 CN103353557A (en) | 2013-06-06 | 2013-06-06 | Main transformer protection tripping matrix exit auxiliary tester |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407244A (en) * | 2014-11-21 | 2015-03-11 | 国家电网公司 | Main transformer tripping matrix testing system |
| CN104062583B (en) * | 2014-07-18 | 2016-06-15 | 国家电网公司 | A kind of simulated test detection method of closing in quick-break fault |
| CN110865261A (en) * | 2019-11-29 | 2020-03-06 | 国网四川省电力公司眉山供电公司 | Protection device outlet matrix calibrator and calibration method |
| CN112444742A (en) * | 2020-11-09 | 2021-03-05 | 国网山东省电力公司信息通信公司 | Relay protection channel monitoring and early warning system |
-
2013
- 2013-06-06 CN CN 201310223272 patent/CN103353557A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104062583B (en) * | 2014-07-18 | 2016-06-15 | 国家电网公司 | A kind of simulated test detection method of closing in quick-break fault |
| CN104407244A (en) * | 2014-11-21 | 2015-03-11 | 国家电网公司 | Main transformer tripping matrix testing system |
| CN104407244B (en) * | 2014-11-21 | 2024-04-09 | 国家电网公司 | Main Transformer Tripping Matrix Test System |
| CN110865261A (en) * | 2019-11-29 | 2020-03-06 | 国网四川省电力公司眉山供电公司 | Protection device outlet matrix calibrator and calibration method |
| CN112444742A (en) * | 2020-11-09 | 2021-03-05 | 国网山东省电力公司信息通信公司 | Relay protection channel monitoring and early warning system |
| CN112444742B (en) * | 2020-11-09 | 2022-05-06 | 国网山东省电力公司信息通信公司 | Relay protection channel monitoring and early warning system |
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Application publication date: 20131016 |