CN103337514A - High-voltage NPN device and layout structure thereof - Google Patents
High-voltage NPN device and layout structure thereof Download PDFInfo
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- CN103337514A CN103337514A CN2013102864511A CN201310286451A CN103337514A CN 103337514 A CN103337514 A CN 103337514A CN 2013102864511 A CN2013102864511 A CN 2013102864511A CN 201310286451 A CN201310286451 A CN 201310286451A CN 103337514 A CN103337514 A CN 103337514A
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Abstract
The invention provides a high-voltage NPN (Negative-Positive-Negative) device and a layout structure thereof. The high-voltage NPN device is characterized by comprising an emitter region, a collector region, a base region and a P-type impurity region, wherein the emitter region, the collector region, the base region and the P-type impurity region are isolated by shallow groove isolation regions, and the P-type impurity region is located between the collector region and the base region, and connected with a semiconductor substrate. According to the high-voltage NPN device and the layout structure thereof, the P-type impurity region is introduced between the collector region and the base region, and connected with the substrate to generate a JFET (Junction Field Effect Transistor) effect, so that a safe working region of the high-voltage NPN device is increased, and an output curve of the high-voltage NPN device cannot be upwarped under the condition that high-voltage large current is injected.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of high pressure NPN device and domain structure thereof.
Background technology
High-voltage semi-conductor device generally is applied in imput output circuit, memory circuit and similar circuit thereof.Wherein, high-voltage bipolar CMOS (Complementary Metal Oxide Semiconductor) (HVBICMOS) is the formant circuit with the cmos device, requiring to drive big capacitive load part adding bipolar device or circuit, having characteristics such as high integration, low-power consumption and at a high speed big driving force concurrently, is high performance semiconductor device of new generation.
Concrete structure based on the high pressure NPN device of HVBICMOS technology, please refer to Fig. 1, it is the domain of the high pressure NPN device of prior art, as shown in Figure 1, high pressure NPN device includes the source region and is surrounded with the trench region in source region, wherein, active area comprises emitter region (E), collector area (C) and base stage (B), and described emitter region (E), collector area (C) and base stage (B) all are positioned at the inside of high voltage N trap (HVNW).
Fig. 2 is the cutaway view of the high pressure NPN device of prior art, as shown in Figure 2, emitter region (E), collector area (C) and base stage (B) are formed at has the P trap, on the Semiconductor substrate of high voltage N trap (HVNW) and buried regions (NBL), buried regions (NBL) is positioned at high voltage N trap (HVNW) below, and the width of the width of buried regions (NBL) and high voltage N trap (HVNW) is suitable, emitter region (E), collector area (C) and base region (B) all be positioned at high voltage N trap (HVNW) above, wherein, collector area (C) comprises the first heavy doping N-type district and is positioned at high voltage N trap (HVNW) below the first heavy doping N-type district, emitter region (E) comprises the second heavy doping N-type district and is positioned at P trap below the second heavy doping N-type district, and base region (B) comprises the P trap of a heavy doping p type island region and its below, the first heavy doping N-type district, the second heavy doping N-type district and heavy doping p type island region are drawn collector electrode respectively, emitter and base stage.
Please continue with reference to figure 2, electronics can inject path and vertical electronics injection path injection collector area (C) via the side direction electronics shown in the arrow in spontaneous emission polar region (E) in high pressure NPN device.Emitter region (E) is realized the side direction isolation by channel separating zone (STI) and base region (B) and high voltage N trap (HVNW).In order to satisfy the demand of high pressure, high pressure NPN device generally can draw back the spacing of collector area (C) and base region (B), and reduces the doped in concentrations profiled of high voltage N trap (HVNW).
Because the high voltage N trap (HVNW) in the high pressure NPN device is low-doped, when high-voltage great-current injected, upwarping can appear in the curve of output of high pressure NPN device, make dissipation power become big, junction temperature raises, the reliability variation of device, and the safety operation area is greatly limited.
Summary of the invention
The object of the present invention is to provide a kind of high pressure NPN device and domain structure thereof, to solve the existing high pressure NPN device problem that upwarping appears in curve of output when high-voltage great-current injects.
For solving the problems of the technologies described above, the invention provides a kind of high pressure NPN device, described high pressure NPN device comprises:
Emitter region, collector area, base region and p type impurity district;
Described emitter region, collector area, base region and p type impurity district all isolate mutually by shallow channel isolation area;
Described p type impurity district is positioned between described collector area and the described base region, and joins with described Semiconductor substrate.
Optionally, in described high pressure NPN device, described Semiconductor substrate has high voltage N trap, a P trap, the 2nd p trap and buried regions;
Described high voltage N trap surrounds a described P trap and the 2nd P trap;
Described buried regions be positioned at described base region below, and with described high voltage N trap in away from a side contacts of described base region.
Optionally, in described high pressure NPN device, described collector area comprises first heavily doped region and is positioned at high voltage N trap below first heavily doped region;
Described emitter region comprises second heavily doped region and is positioned at a P trap below second heavily doped region;
Described base region comprises the 3rd heavily doped region and is positioned at a P trap below the 3rd heavily doped region;
Described p type impurity district comprises the quadruple doped region and is positioned at the 2nd P trap below the quadruple doped region.
Optionally, in described high pressure NPN device, described buried regions, first heavily doped region and second heavily doped region are the N-type conductivity type, and described the 3rd heavily doped region and quadruple doped region are the P-type conduction type.
Optionally, in described high pressure NPN device, described high voltage N trap is for gently mixing up the N-type impurity range.
Optionally, in described high pressure NPN device, the width of described buried regions equates with the distance at two ends, described base region.
The present invention also provides a kind of domain structure of high pressure NPN device, and the domain structure of described high pressure NPN device comprises:
High voltage N trap, emitter region, collector area, base region, p type impurity district and shallow trench isolation regions;
Described emitter region, collector area, base region and shallow trench isolation regions all are arranged at the inside of described high voltage N trap;
The center of described base region and described emitter region is at same position, and described base region is around described emitter region;
Described p type impurity district is positioned between described collector area and the described base region, and the width in described p type impurity district is greater than the width of high voltage N trap;
Described emitter region, collector area, base region, p type impurity district are all centered on by described shallow trench isolation regions.
Optionally, in the domain structure of described high pressure NPN device, described collector area and emitter region are the N-type conductivity type, and described base region is the P-type conduction type.
In sum, in high pressure NPN device of the present invention and the domain structure thereof, introduced the p type impurity district between collector area and the base region, described p type impurity district and substrate join and produce the JFET effect, thereby improved the safety operation area of high pressure NPN device, even under the situation of injecting high-voltage great-current, upwarping can not appear in the curve of output of described high pressure NPN device yet.
Description of drawings
Fig. 1 is the domain of the high pressure NPN device of prior art;
Fig. 2 is the cutaway view of the high pressure NPN device of prior art;
Fig. 3 is the cutaway view of the high pressure NPN device of the embodiment of the invention;
Fig. 4 is the domain of the high pressure NPN device of the embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments high pressure NPN device and the domain structure thereof that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
[embodiment one]
Please refer to Fig. 3, it is the cutaway view of the high pressure NPN device of the embodiment of the invention.As shown in Figure 3, described high pressure NPN device is formed on the Semiconductor substrate, and described high pressure NPN device comprises: emitter region, collector area, base region and p type impurity district; Described emitter region, collector area, base region and p type impurity district be positioned at described Semiconductor substrate 10 above, and mutually isolate by shallow channel isolation area (STI); Described p type impurity district is positioned between collector area and the base region, and joins with described Semiconductor substrate 10.
Concrete, described Semiconductor substrate 10 has high voltage N trap 11, a P trap 12, the 2nd p trap 13 and buried regions 14.Wherein, described high voltage N trap 11 is for gently mixing up the N-type impurity range, and described buried regions 14 is the N-type doped region.The position of described buried regions 14 be positioned at described base region below, and with described high voltage N well region 11 in contact away from the surface of described base region, described high voltage N trap 11 surrounds a described P trap 12 and the 2nd P traps 13.
Please continue with reference to figure 3, as shown in Figure 3, described collector area comprises first heavily doped region 15 and the high voltage N trap 11 that is positioned at first heavily doped region, 15 belows, and described first heavily doped region 15 contacts with described high voltage N trap 11, and described collector area is drawn collector electrode by first heavily doped region 15.Described emitter region comprises second heavily doped region 16 and a P trap 12 that is positioned at second heavily doped region, 16 belows, and described second heavily doped region 16 contacts with a described P trap 12, and described emitter region is drawn emitter by second heavily doped region 16.Described base region comprises that the 3rd heavily doped region 17 and a P trap 12, the three heavily doped regions 17 that are positioned at the 3rd heavily doped region 17 belows contact with a described P trap 12, and base stage is drawn by the 3rd heavily doped region 17 in described base region.As shown in Figure 3, described base region is around described emitter region, and by shallow channel isolation area 19 and described emitter region isolation, the distance at two ends, described base region equates with the width d of described buried regions 14.Described p type impurity district comprises that quadruple doped region 183 and the 2nd P trap 13, the two P traps 13 that are positioned at quadruple doped region 18 belows contact with described quadruple doped region 18.
Described buried regions 14, first heavily doped region 15, high voltage N trap 11 and second heavily doped region 16 are first conductivity type, i.e. the N-type conductivity type.Described the 3rd heavily doped region 17 and quadruple doped region 18 are second conductivity type, and the conductivity type opposite of the conduction type of described second conductivity type and described first conductivity type is the P-type conduction type.
Please continue with reference to figure 3, as shown in Figure 3, emitter region, collector area, base region and p type impurity district all by 19 of shallow channel isolation areas around, shallow channel isolation area 19 is insulation layer.Emitter region, collector area, base region and p type impurity district are isolated from each other by shallow channel isolation area 19.
Because the gap ratio of collector area and base region is bigger in the described high pressure NPN device, and the high voltage N trap 11 in the collector area structure is low-doped, can concentrate more multiple carrier, therefore, can apply high voltage between collector electrode and the emitter.
And, in the high pressure NPN of embodiment of the invention device, introduced the p type impurity district, stretch out the certain distance of high voltage N trap 11 and join with described Semiconductor substrate 10 in described p type impurity district, thus, has formed a PN junction between high voltage N trap 11 and p type impurity district.The existence of PN junction has increased the distance of emitter to collector electrode, has improved electric field strength and current density herein simultaneously, has finally reduced the dissipation power of device, has increased resistance to pressure, has improved its safety operation area.
This shows, described high pressure NPN devices use the JFET effect, PN junction is as the size of grid (back of the body grid) control source/leakage current in the JFET effect.When source-drain voltage was low, JFET was in linear working state, and source-drain current increases along with the rising of source-drain voltage; When source-drain voltage is higher, the narrowed width of raceway groove, JFET is in the saturation current operating state, and source-drain current can not increase along with the rising of source-drain voltage.Therefore, improved the safety operation area of high pressure NPN device.
[embodiment two]
Please refer to Fig. 4, it is the domain of the high pressure NPN device of the embodiment of the invention.As shown in Figure 4, the domain structure of described high pressure NPN device comprises:
High voltage N trap 20, emitter region 21, collector area 22, base region 23, p type impurity district 24 and shallow trench isolation regions 25; Described emitter region 21, collector area 22, base region 23 and shallow trench isolation regions 25 all are arranged at the inside of described high voltage N trap 20; The center of described base region 23 and described emitter region 21 is at same position, and described base region 23 is around described emitter region 21; Described p type impurity district 24 is between described collector area 22 and described base region 23, and the width in described p type impurity district 24 is greater than the width of high voltage N trap 20; Described emitter region 21, collector area 22, base region 23, p type impurity district 24 are all centered on by described shallow trench isolation regions 25.
Concrete, the basic process of the domain structure of high pressure NPN device comprises: at first, determine position and the width of high voltage N trap 20, high voltage N trap 20 is gently to mix up the N-type extrinsic region, has defined the zone of whole high pressure NPN device; Then, determine distance between collector area and the base region; Then, determine position and the width of base region and emitter region; Afterwards, determine position and the width in p type impurity district, the p type impurity district requires to stretch out high voltage N trap 20; Adopt the domain structure of bar shaped at last, the p type impurity district between definition emitter region, base region, collector area, base region and the collector area.Wherein, the base region is the P-type conduction type, and collector area and emitter region are the N-type conductivity type.
Please continue with reference to figure 4, as shown in Figure 4, the width in emitter region, collector area, base region, p type impurity district is respectively E, C, B, P.Wherein, the width P in p type impurity district is the longest, has exceeded the width of high voltage N trap 20, and the width P in p type impurity district can adjust according to the requirement of product, and is common, and the width P in p type impurity district is more big, and the safety operation area is more big.
Adopt the high pressure NPN device of the domain structure manufacturing of described high pressure NPN device, its curve of output is more level and smooth, better reliability, and the safety operation area is wideer.
To sum up, in the high pressure NPN device that the embodiment of the invention provides, introduced the p type impurity district, utilize the JFET effect between p type impurity district and the high voltage N trap to improve the safety operation area, make described high pressure NPN device curve of output under the situation of injecting high-voltage great-current also can not occur upwarping, thereby improved the safety operation area of described high pressure NPN device, optimized the performance of high pressure NPN device.Simultaneously, the embodiment of the invention provides the domain structure of high pressure NPN device, can be for the manufacture of described high pressure NPN device, by the width in the p type impurity district in the domain structure of adjusting high pressure NPN device, improve the safety operation area, can adapt to the demand of different product.
Foregoing description only is the description to preferred embodiment of the present invention, is not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure all belong to the protection range of claims.
Claims (8)
1. a high pressure NPN device is formed on the Semiconductor substrate, it is characterized in that, comprising:
Emitter region, collector area, base region and p type impurity district;
Described emitter region, collector area, base region and p type impurity district all isolate mutually by shallow channel isolation area;
Described p type impurity district is positioned between described collector area and the described base region, and joins with described Semiconductor substrate.
2. high pressure NPN device as claimed in claim 1 is characterized in that, described Semiconductor substrate has high voltage N trap, a P trap, the 2nd p trap and buried regions;
Described high voltage N trap surrounds a described P trap and the 2nd P trap;
Described buried regions be positioned at described base region below, and with described high voltage N trap in away from a side contacts of described base region.
3. high pressure NPN device as claimed in claim 2 is characterized in that, described collector area comprises first heavily doped region and is positioned at high voltage N trap below first heavily doped region;
Described emitter region comprises second heavily doped region and is positioned at a P trap below second heavily doped region;
Described base region comprises the 3rd heavily doped region and is positioned at a P trap below the 3rd heavily doped region;
Described p type impurity district comprises the quadruple doped region and is positioned at the 2nd P trap below the quadruple doped region.
4. high pressure NPN device as claimed in claim 3 is characterized in that, described buried regions, first heavily doped region and second heavily doped region are the N-type conductivity type, and described the 3rd heavily doped region and quadruple doped region are the P-type conduction type.
5. high pressure NPN device as claimed in claim 2 is characterized in that, described high voltage N trap is for gently mixing up the N-type impurity range.
6. high pressure NPN device as claimed in claim 2 is characterized in that, the width of described buried regions equates with the distance at two ends, described base region.
7. the domain structure of a high pressure NPN device is characterized in that, comprising:
High voltage N trap, emitter region, collector area, base region, p type impurity district and shallow trench isolation regions;
Described emitter region, collector area, base region and shallow trench isolation regions all are arranged at the inside of described high voltage N trap;
The center of described base region and described emitter region is at same position, and described base region is around described emitter region;
Described p type impurity district is positioned between described collector area and the described base region, and the width in described p type impurity district is greater than the width of high voltage N trap;
Described emitter region, collector area, base region, p type impurity district are all centered on by described shallow trench isolation regions.
8. the domain structure of high pressure NPN device as claimed in claim 7 is characterized in that, described collector area and emitter region are the N-type conductivity type, and described base region is the P-type conduction type.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310286451.1A CN103337514B (en) | 2013-07-09 | High-voltage NPN device and domain structure thereof |
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| CN201310286451.1A CN103337514B (en) | 2013-07-09 | High-voltage NPN device and domain structure thereof |
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| CN103337514A true CN103337514A (en) | 2013-10-02 |
| CN103337514B CN103337514B (en) | 2016-11-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680908A (en) * | 2016-08-01 | 2018-02-09 | 中芯国际集成电路制造(北京)有限公司 | High-voltage semi-conductor device and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518124A (en) * | 2003-01-28 | 2004-08-04 | ��ʽ���������Ƽ� | Lateral transistor |
| CN101026189A (en) * | 2006-02-24 | 2007-08-29 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| US7759759B2 (en) * | 2002-12-17 | 2010-07-20 | Micrel Incorporated | Integrated circuit including a high voltage bipolar device and low voltage devices |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7759759B2 (en) * | 2002-12-17 | 2010-07-20 | Micrel Incorporated | Integrated circuit including a high voltage bipolar device and low voltage devices |
| CN1518124A (en) * | 2003-01-28 | 2004-08-04 | ��ʽ���������Ƽ� | Lateral transistor |
| CN101026189A (en) * | 2006-02-24 | 2007-08-29 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 王志功、沈永朝: "《电路与电子线路基础 电子线路部分 》", 30 April 2013, article "4.3 BJT的制造工艺", pages: 98-99 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680908A (en) * | 2016-08-01 | 2018-02-09 | 中芯国际集成电路制造(北京)有限公司 | High-voltage semi-conductor device and preparation method thereof |
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