CN103327360A - VGA-format output embedded high-resolution visual inspection device - Google Patents
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Abstract
The invention provides a VGA-format output embedded high-resolution visual inspection device which comprises a high-resolution industrial lens, a CMOS imaging assembly, an image processing assembly and a VGA liquid crystal display. The connecting relationships among the parts include: the CMOS imaging assembly is respectively connected with the high-resolution industrial lens and the image processing assembly, and the image processing assembly is further connected with the VGA liquid crystal display. The VGA-format output embedded high-resolution visual inspection device is achieved through a digital signal processing chip, is high in processing speed, and therefore guarantees good real-time performance. Meanwhile, the VGA-format output embedded high-resolution visual inspection device adopts the embedded design mode so as to be low in power consumption. The VGA-format output embedded high-resolution visual inspection device can be well used in an assembly system and achieve detection and display on postures of tiny assembly parts.
Description
Technical field
The invention belongs to machine vision metrology and vision control technology field, be specifically related to a kind of embedded high-resolution vision inspection apparatus of VGA formatted output.
Background technology
In traditional little assembling field, such as clockwork, fuse security mechanism etc., generally adopt the mode of hand assembled for mini system.The shortcomings such as this assembling mode exists efficiency of assembling low, and assembly quality is not high are difficult to adapt to the at a high speed needs of assembling in enormous quantities.Therefore the mini system assembling line of automation just become in the urgent need to.The key technology of little assembly line and detect for the pose of micro part.Two kinds of methods of the general employing of present existing industrial detection system, the one, the mode of camera+PC, this mode can connect high resolution camera, software programming is also more flexible, but there is following deficiency in this mode: volume is large, and power consumption is high, and real-time is poor, cost is higher, and inconvenience and other control system integrated; The 2nd, embedded system, but industrial camera is not because the reasons such as trade secret can provide physical layer interface to drive at present, therefore embedded processing systems is difficult to have industrial camera now integrated, although can use NTSC or pal mode analogue camera, but analogue camera resolution is lower, only have about 400,000 pixels, be difficult to satisfy the needs of accurate microminiature units test.Need in a hurry a kind of volume little in little assembly line, real-time is good, and resolution is high, conveniently is integrated in the micro part apparatus for detecting position and posture in the control system.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the invention provides a kind of embedded high-resolution vision inspection apparatus of VGA formatted output, this device volume is little, cost is low, and real-time is good.
Realize that technical scheme of the present invention is as follows:
A kind of embedded high-resolution vision inspection apparatus of VGA formatted output comprises high resolution industrial camera lens, cmos imaging assembly, image processing modules and VGA liquid crystal display; Annexation between the each part mentioned above is: the cmos imaging assembly links to each other with image processing modules with the high resolution industrial camera lens respectively, and image processing modules further links to each other with the VGA display;
The cmos imaging component internal is integrated cmos imaging transducer, power management module and level switch module; Described cmos imaging transducer gathers the view data of measured piece by the high resolution industrial camera lens; Described level switch module is used for the level conversion of the view data of cmos imaging transducer collection is become to meet the level that image processing modules requires; It is the cmos imaging assembly power supply that described power management module is used for converting the power supply electrical level that image processing modules provides to cmos imaging assembly required level;
Image processing modules comprises image processing module, video encoding module, serial communication modular, Logic control module, expansion I/O mouth and memory module; Wherein the video port VP1 on the image processing module links to each other with the cmos imaging assembly, video port VP2 andlogic control module on the image processing module links to each other, Logic control module links to each other respectively with video encoding module, serial communication modular and expansion I/O mouth, and image processing module further links to each other with memory module;
Image processing module on the one hand gathers the view data that the cmos imaging assembly obtains by video port VP1, and it is transferred to memory module stores; On the other hand the 12 bit image data transaction of storing are become RGB565 format-pattern data and process, then the position of processing measured piece on the rear view data is detected, obtain measured piece position parameter, and the view data after will processing and position parameter are transferred to Logic control module by video port VP2;
Logic control module receives measured piece position parameter on the one hand, then by serial communication modular it is transferred to the bottom control system, on the other hand the view data that receives is converted to the dual rate data format, exports to video encoding module again;
The view data that video encoding module is used for the dual rate data format that will receive converts VGA formatted output to VGA display to and shows.
Further, cmos imaging transducer of the present invention adopts the MT9P031STMSTM chip to realize, it is output as 12 RAW format-patterns of black and white data.
Further, image processing module of the present invention adopts the TMS320DM642 chip to realize.
Further, the VP1 mouth of cmos imaging assembly of the present invention and TMS320DM642 chip adopts the connector mode to be connected by winding displacement, and integrated image processing modules is the power line of cmos imaging assembly power supply in connecting winding displacement.
Further, Logic control module of the present invention has adopted the EP2C5Q208C8N chip.
Further, video encoding module of the present invention adopts the SAA7105H chip to realize.
Further, Logic control module of the present invention comprises data converting circuit, and this data converting circuit is used for view data is converted to the dual rate data format, and it comprises the alternative selectors of 8 latch A, 8 latch B and 16 inputs, 8 outputs; Latch A is used for latching the least-significant byte of RGB565 format-pattern data, and latch B is used for latching the most-significant byte of RGB565 format-pattern data; The data that the alternative selector is used for latching on gating latch A or the latch B are exported; The driving clock signal of latch A, latch B, alternative selector and video port VP2 all comes from video encoding module;
When the rising edge clock signal of video encoding module arrives, the VP2 video port sends RGB565 format-pattern data to the data converting circuit of Logic control module, and the latch A of data converting circuit and latch B latch respectively least-significant byte and the most-significant byte of RGB565 format-pattern data; The alternative selector is when rising edge clock signal arrives, and the data that latch on the gating latch A are exported, when the clock signal trailing edge arrives, and the data output of latching on the gating latch B.
Beneficial effect
The first, image processing modules employing digital signal processing chip of the present invention realization, its processing speed is fast, thereby guarantees that vision inspection apparatus real-time of the present invention is good; Simultaneously, vision inspection apparatus of the present invention adopts the embedded design pattern, and it is low in energy consumption (be PC power consumption commonly used 1/30); The present invention can be good at being used in the assembly system, realizes the attitude of small assembly parts (measured piece) is detected and reality.
The second, cmos imaging transducer employing MT9P031STMSTM chip of the present invention realization has higher resolution, can finish 5,000,000 pixel black and white image collections; Image processing module of the present invention adopts the TMS320DM642 chip to realize, this chip frequency has reached 600Mhz makes it have faster processing speed.
Three, the present invention is in the process to MT9P031STMSTM chip and the configuration of TMS320DM642 chip drives, arrange by line number and columns to image, so that the present invention can adjust the resolution that gathers image, and the present invention becomes the VGA form with image transitions, so that vision inspection apparatus of the present invention can connect the VGA display of present extensive use, image shows convenient.
Description of drawings
Fig. 1 is the present invention's connection diagram in kind;
Fig. 2 is overall construction drawing of the present invention;
Fig. 3 is image-forming assembly of the present invention and image processing modules electric interfaces figure;
Fig. 4 is image processing modules internal circuit block diagram of the present invention;
Fig. 5 is image-forming assembly internal circuit block diagram of the present invention;
Fig. 6 is the image acquisition process of video port VP1 of the present invention;
Fig. 7 is pose testing process overview flow chart of the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiments principle of the present invention and details are described further.
As shown in Figure 1, the embedded high-resolution vision inspection apparatus of VGA formatted output of the present invention comprises high resolution industrial camera lens, cmos imaging assembly, image processing modules and VGA display; Annexation between its each several part is: high resolution industrial camera lens, cmos imaging assembly, image processing modules and VGA display connect successively, and high resolution industrial alignment lens micro parts to be measured.
Its course of work is: the cmos imaging assembly is treated by the high resolution industrial camera lens after the micro parts imaging of location appearance image transmitting to image processing modules, after image processing modules is processed image image is shown on the VGA display, simultaneously result (being the position parameter of measured piece) is outputed to the bottom control system by serial ports.
The below is described in detail each parts of the present invention:
The cmos imaging assembly has 24 pin connectors by the standard interface connection high resolution industrial camera lens on the shell on the backboard of cmos imaging assembly, the video port of the TMS320DM642 chip by 24 pin connectors and image processing modules is direct-connected.
The cmos imaging component internal is integrated cmos imaging transducer, power management module and level switch module; Described cmos imaging transducer gathers the view data of measured piece by the high resolution industrial camera lens, this view data is 12 RAW form; Described level switch module is used for the level conversion of the view data of cmos imaging transducer collection is become to meet the level that image processing modules requires, and it is the cmos imaging assembly power supply that described power management module is used for converting the power supply electrical level that image processing modules provides to cmos imaging assembly required level.
As shown in Figure 2, image processing modules comprises image processing module, video encoding module, serial communication modular, Logic control module, expansion I/O mouth and memory module; Wherein the video port VP1 on the image processing module links to each other with the cmos imaging assembly, video port VP2 andlogic control module on the image processing module links to each other, Logic control module links to each other respectively with video encoding module, serial communication modular and expansion I/O mouth, and image processing module further links to each other with memory module;
Image processing module adopts the TMS320DM642 chip to realize, on the one hand, image processing module gathers the view data that the cmos imaging assembly obtains by video port VP1, and it is transferred to memory module stores; On the other hand, image processing module becomes RGB565 format-pattern data with the 12 bit image data transaction of storing and processes (this processing can for image being carried out binary conversion treatment, sharpening processing etc.), then the position of processing measured piece on the rear view data is detected, obtain measured piece position parameter, described position parameter comprises measured piece x direction side-play amount, y direction side-play amount and the anglec of rotation; View data and position parameter after will processing simultaneously are transferred to Logic control module by video port VP2.
The present invention becomes the view data of RGB565 form can adopt multiple conversion regime 12 bit image data transaction, for example, can take 12 bit image data high 5 as R, Gao Liuwei is G, high 5 forms that convert thereof into RGB565 for the mode of B also can mend 0000 in 12 bit image data fronts, then make high 5 to be R, middle 6 is G, low 5 forms that convert thereof into RGB565 for B.
Logic control module, receive on the one hand measured piece position parameter, then by serial communication modular measured piece position parameter is transferred to the bottom control system, the bottom control system is according to the rotation of described position parameter control precision displacement table, so that measured piece reaches desirable rigging position; View data with the RGB565 form that receives is converted to the dual rate data format on the other hand, exports to video encoding module again.
Logic control module of the present invention comprises data converting circuit, and view data converts the dual rate data to and realized by data converting circuit, and this data converting circuit comprises the alternative selectors of 8 latch A, 8 latch B and 16 inputs, 8 outputs; Latch A is used for latching the least-significant byte of RGB565 format-pattern data, and latch B is used for latching the most-significant byte of RGB565 format-pattern data; The view data that the alternative selector is used for latching on gating latch A or the latch B is exported; The driving clock signal of latch A, latch B, alternative selector and video port VP2 all comes from video encoding module;
When the rising edge clock signal of video encoding module arrives, the VP2 video port sends RGB565 format-pattern data to the data converting circuit of Logic control module, the latch A of data converting circuit, latch B latch respectively least-significant byte and the most-significant byte of RGB565 format-pattern data; The alternative selector is when rising edge clock signal arrives, and the data that latch on the gating latch A are exported, when the clock signal trailing edge arrives, and the data output of latching on the gating latch B.So just make 16 RGB565 format-pattern data transaction that arrive at rising edge clock signal become to export respectively 8 dual rate clock data at rising edge clock signal and trailing edge.
Video encoding module adopts the SAA7105H chip to realize, its view data with the dual rate data format of reception converts VGA formatted output to VGA display to and shows.
Memory module of the present invention comprises the sdram memory of 32Mbyte and the flash memory of 4Mbyte, is respectively applied to storing image data and program curing.
The electrical connection of cmos imaging assembly of the present invention and image processing modules as shown in Figure 3.Image processing modules provides 5V and 3.3V power supply for the cmos imaging assembly, and image processing modules is by I2C bus configuration cmos imaging assembly.The field signal line FV of cmos imaging assembly, row signal line LV, pixel clock signal line PIXEL is connected respectively the video port VP1 of TMS320DM642, for image output provides control signal, 12 data lines VPD[0..11] receive the data wire of VP video port, output image data.
The drive arrangements process of video port VP1 of the present invention and cmos imaging assembly may further comprise the steps:
(1) 32 VPIE registers of configuration TMS320DM642 chip, the in advance interrupt event of initialization video port VP1 in this register; The concrete configuration mode is: the 2nd with this 32 bit register is defined as CCMPA, and CCMPA is set to 1, it is used for catching finishing and interrupts CCMPA, and the 1st of this 32 bit register is defined as COVRA, and COVRA is set to 1, it be used for to cover interrupts, and the 3rd of this 32 bit register is defined as SERRA, and SERRA is set to 1, it is used for timing error and interrupts, the 0th with this 32 bit register is defined as VPIE, and VPIE is set to 1, is used for enabling the global interrupt of video port.
(2) 32 VCASTOP1 registers of configuration TMS320DM642 chip arrange the size of video port image that VP1 gathers in advance in this register; The concrete configuration mode is: the 16-27 position of this 32 bit register is defined as VCAYSTOP, and it is set to gather size high 12 of image, and the 0-11 position of this 32 bit register is defined as VCAXSTOP, and it is set to gather low 12 of picture size.
(3) 32 VCASTRT1 registers of configuration TMS320DM642 chip arrange the vertical blanking time of video port image that VP1 gathers and the time started that gathers image in advance in this register; The concrete configuration mode is: the 16-27 position of this 32 bit register is defined as VCYSTART, and with VCYSTART everybody is set to 0, the 15th with this 32 bit register is defined as SSE, and SSE is set to 1, the 0-11 position of this 32 bit register is defined as VCVBLNKP, and everybody is set to 1 with VCVBLNKP.
(4) 32 VCATHRLD registers of configuration TMS320DM642 chip, the trigger condition that the DMA event is set in this register in advance are that the number of pixels of the FIFO storage of video port VP1 is the number of view data one-row pixels; The concrete configuration mode is: the 16-25 position of this 32 bit register is defined as VCTHRLD2, and with VCTHRLD2 everybody is set to 0, the 0-9 position of this 32 bit register is defined as VCTHRLD1, and the value of VCTHRLD1 is set to 1/4th of institute's acquisition of image data one-row pixels number.
(5) 32 VCACTL registers of configuration TMS320DM642 chip, the IMAQ mode that video port VP1 is set in this register in advance is 16 RAW IMAQs of discontinuous single frames; The concrete configuration mode is: the 7th with this 32 bit register is defined as CON, and CON is set to 0, the 6th with this 32 bit register is defined as FRAME, and FRAME is set to 1, the 5th of this 32 bit register is defined as CF2, and CF2 is set to 0, the 4th with this 32 bit register is defined as CF1, and CF1 is set to 0, the 0-2 position of this 31 bit register is defined as CMODE, and the value of CMODE is set to 6.
(6) 32 VPCTL registers of configuration TMS320DM642 chip, the in advance time-out of cancellation video port VP1 (namely activate video port VP1 make its in running order) in this register; Its configuration mode is: the 14th with this register is defined as VPHLT, and VPHLT is set to 1.
(7) 32 VCACTL registers of configuration TMS320DM642 chip enable the IMAQ of video port VP1 in advance in this register; Its configuration mode is: the 15th with this register is defined as VCEN, and VCEN is set to 1, the 30th of this 31 bit register is defined as BLKCAP, and BLKCAP is set to 0.
(8) 16 R13 registers of configuration cmos imaging assembly, imager chip MT9P031STM in advance resets in this 32 bit register; The concrete configuration mode is: write 0x0001 by the I2C bus to R13, wait for 200ms, write 0x0000 to R13.
(9) 16 R3 registers of configuration cmos imaging assembly arrange the line number of output image in advance in this 32 bit register; The concrete configuration mode is: write 0x01df by the I2C bus to the R3 register, it is 768 that the output image line number is set.
(10) 16 R4 registers of configuration cmos imaging assembly arrange the columns of output image in advance in this 32 bit register; The concrete configuration mode is: write 0x027f by the I2C bus to the R4 register, it is 1024 that the output image columns is set.
(11) 16 R5 registers of configuration cmos imaging assembly 32 arrange the horizontal blanking interval in the register at this in advance; The concrete configuration mode is: write 0x00a0 by the I2C bus to the R5 register, it is 97 that the horizontal blanking interval is set.
(12) 16 R6 registers of configuration cmos imaging assembly arrange vertical blanking time in advance in this 32 bit register; The concrete configuration mode is: write 0x0154 by the I2C bus to the R6 register, it is 1365 that vertical blanking time is set.
(13) 16 R10 registers of configuration cmos imaging assembly arrange the pixel output clock in advance in this 32 bit register; The concrete configuration mode is: write respectively 0x8000 by the I2C bus to the R10 register.
(14) 16 R1 registers of configuration cmos imaging assembly arrange the start of line position of output image in advance in this 32 bit register; The concrete configuration mode is: write respectively 0x02dc by the I2C bus to the R1 register.
(15) 16 R2 registers of configuration cmos imaging assembly arrange the row original position of output image in advance in this 32 bit register; The concrete configuration mode is: write respectively 0x0470 by the I2C bus to the R2 register.
(16) 16 R11 registers of configuration cmos imaging assembly restart MT9P031STM in advance in this 32 bit register; The concrete configuration mode is: write respectively 0x0001 by the I2C bus to the R11 register.
As shown in Figure 6, it is the image acquisition process of video port VP1.
The particular hardware circuit of image processing modules of the present invention realizes as shown in Figure 4, and TMS320DM642 has 3 video ports, and these 3 video ports can be configured to video output or video input.Control signal wire and the image line data of the output of cmos imaging assembly are received the VP1 video port by connector, by VP1 video port acquisition of image data.Logic control module has adopted fpga chip EP2C5Q208C8N, and this chip provides sufficient logical resource and expanded 36 road I/O interfaces.The VP2 video port is configured to the image output mode, and the VP2 video port is connected to Logic control module, view data outputs to the video encoding module coding through converting the dual rate clock data after the logical conversion of Logic control module to, encodes the data to VGA video flowing display by the screen coding module and shows.
TMS320DM642 has expanded 32Msdram, 4Mflash and serial communication modular by EMIFA bus and Logic control module.Serial communication modular has used the TL16C752B chip, and two serial ports have been processed in the decoding of this chip by Logic control module integrated, and the result that image is processed is transferred to the bottom control system by these two serial ports.
Micro part appearance testing process overview flow chart of the present invention as shown in Figure 7, concrete treatment step is: after 1, system powered on, system boot program copy user program was carried out master processor program to internal memory; 2, master processor program begins to finish EMIFA bus initialization, system break initialization, the I2C bus initialization of TMS320DM642, then by I2C bus initialization cmos imaging assembly; 3, configuration VP1 video port is 16 bit digital image acquisition modality, and the VP2 video port is 16 bit digital image output modes, and the configuration video encoding module is VGA output; 4, begin to start the IMAQ process; 5, judge whether the VP1 mouth collects a two field picture, calling graph carries out the image processing as the algorithm in the algorithms library after collecting a two field picture, after finishing dealing with, processes structure output to serial ports, and the view data after the processing is exported by the VP2 mouth.
In sum, above is preferred embodiment of the present invention only, is not for limiting protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the embedded high-resolution vision inspection apparatus of a VGA formatted output is characterized in that, comprises high resolution industrial camera lens, cmos imaging assembly, image processing modules and VGA liquid crystal display; Annexation between the each part mentioned above is: the cmos imaging assembly links to each other with image processing modules with the high resolution industrial camera lens respectively, and image processing modules further links to each other with the VGA display;
The cmos imaging component internal is integrated cmos imaging transducer, power management module and level switch module; Described cmos imaging transducer gathers the view data of measured piece by the high resolution industrial camera lens; Described level switch module is used for the level conversion of the view data of cmos imaging transducer collection is become to meet the level that image processing modules requires; It is the cmos imaging assembly power supply that described power management module is used for converting the power supply electrical level that image processing modules provides to cmos imaging assembly required level;
Image processing modules comprises image processing module, video encoding module, serial communication modular, Logic control module and memory module; Wherein the video port VP1 on the image processing module links to each other with the cmos imaging assembly, video port VP2 andlogic control module on the image processing module links to each other, Logic control module links to each other respectively with video encoding module and serial communication modular, and image processing module further links to each other with memory module;
Image processing module on the one hand gathers the view data that the cmos imaging assembly obtains by video port VP1, and it is transferred to memory module stores; On the other hand the 12 bit image data transaction of storing are become RGB565 format-pattern data and process, then the position of processing measured piece on the rear view data is detected, obtain measured piece position parameter, and the view data after will processing and position parameter are transferred to Logic control module by video port VP2;
Logic control module receives measured piece position parameter on the one hand, then by serial communication modular it is transferred to the bottom control system, on the other hand the view data that receives is converted to the dual rate data format, exports to video encoding module again;
The view data that video encoding module is used for the dual rate data format that will receive converts VGA formatted output to VGA display to and shows.
2. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 1 is characterized in that, described cmos imaging transducer adopts the MT9P031STMSTM chip to realize, it is output as 12 RAW format-patterns of black and white data.
3. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 1 and 2 is characterized in that, described image processing module adopts the TMS320DM642 chip to realize.
4. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 3, it is characterized in that, the VP1 mouth of described cmos imaging assembly and TMS320DM642 chip adopts the connector mode to be connected by winding displacement, and integrated image processing modules is the power line of cmos imaging assembly power supply in connecting winding displacement.
5. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 1, it is characterized in that, described Logic control module comprises data converting circuit, this data converting circuit is used for view data is converted to the dual rate data format, and it comprises the alternative selectors of 8 latch A, 8 latch B and 16 inputs, 8 outputs; Latch A is used for latching the least-significant byte of RGB565 format-pattern data, and latch B is used for latching the most-significant byte of RGB565 format-pattern data; The data that the alternative selector is used for latching on gating latch A or the latch B are exported; The driving clock signal of latch A, latch B, alternative selector and video port VP2 all comes from video encoding module;
When the rising edge clock signal of video encoding module arrives, the VP2 video port sends RGB565 format-pattern data to the data converting circuit of Logic control module, and the latch A of data converting circuit and latch B latch respectively least-significant byte and the most-significant byte of RGB565 format-pattern data; The alternative selector is when rising edge clock signal arrives, and the data that latch on the gating latch A are exported, when the clock signal trailing edge arrives, and the data output of latching on the gating latch B.
6. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 1 is characterized in that, described Logic control module has adopted the EP2C5Q208C8N chip.
7. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 1 is characterized in that, described video encoding module adopts the SAA7105H chip to realize.
8. the embedded high-resolution vision inspection apparatus of described VGA formatted output according to claim 1 is characterized in that, described image processing modules also comprises the expansion I/O mouth.
9. based on the embedded high-resolution vision inspection apparatus of the described VGA formatted output of claim 3, it is characterized in that, the drive arrangements process of video port VP1 and cmos imaging assembly may further comprise the steps:
(1) 32 VPIE registers of configuration TMS320DM642 chip, the in advance interrupt event of initialization video port VP1 in this register;
(2) 32 VCASTOP1 registers of configuration TMS320DM642 chip arrange the size of video port image that VP1 gathers in advance in this register;
(3) 32 VCASTRT1 registers of configuration TMS320DM642 chip arrange the vertical blanking time of video port image that VP1 gathers and the time started that gathers image in advance in this register;
(4) 32 VCATHRLD registers of configuration TMS320DM642 chip, the trigger condition that the DMA event is set in this register in advance are that the number of pixels of the FIFO storage of video port VP1 is the number of view data one-row pixels;
(5) 32 VCACTL registers of configuration TMS320DM642 chip, the IMAQ mode that video port VP1 is set in this register in advance is 16 RAW IMAQs of discontinuous single frames;
(6) 32 VPCTL registers of configuration TMS320DM642 chip, the in advance time-out of cancellation video port VP1 in this register;
(7) 32 VCACTL registers of configuration TMS320DM642 chip enable the IMAQ of video port VP1 in advance in this register;
(8) 16 R13 registers of configuration cmos imaging assembly, imager chip MT9P031STM in advance resets in this 32 bit register;
(9) 16 R3 registers of configuration cmos imaging assembly arrange the line number of output image in advance in this 32 bit register;
(10) 16 R4 registers of configuration cmos imaging assembly arrange the columns of output image in advance in this 32 bit register;
(11) 16 R5 registers of configuration cmos imaging assembly 32 arrange the horizontal blanking interval in the register at this in advance;
(12) 16 R6 registers of configuration cmos imaging assembly arrange vertical blanking time in advance in this 32 bit register;
(13) 16 R10 registers of configuration cmos imaging assembly arrange the pixel output clock in advance in this 32 bit register;
(14) 16 R1 registers of configuration cmos imaging assembly arrange the start of line position of output image in advance in this 32 bit register;
(15) 16 R2 registers of configuration cmos imaging assembly arrange the row original position of output image in advance in this 32 bit register;
(16) 16 R11 registers of configuration cmos imaging assembly restart MT9P031STM in advance in this 32 bit register.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101509878A (en) * | 2009-03-09 | 2009-08-19 | 北京航空航天大学 | Part vision detection device |
| CN102073148A (en) * | 2011-01-14 | 2011-05-25 | 北京理工大学 | High-accuracy visual coaxial optical alignment assembly system for miniature structural member |
-
2013
- 2013-06-14 CN CN201310236281.6A patent/CN103327360B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101509878A (en) * | 2009-03-09 | 2009-08-19 | 北京航空航天大学 | Part vision detection device |
| CN102073148A (en) * | 2011-01-14 | 2011-05-25 | 北京理工大学 | High-accuracy visual coaxial optical alignment assembly system for miniature structural member |
Non-Patent Citations (2)
| Title |
|---|
| 唐永龙，张之敬，张晓峰，孙媛: "微装配正交精确对准系统的设计", 《光学精密工程》, vol. 20, no. 7, 31 July 2012 (2012-07-31), pages 1542 - 1550 * |
| 王强，张之敬等: "微装配检测棱镜机构方位调整及误差分析", 《北京理工大学学报》, vol. 31, no. 8, 31 August 2011 (2011-08-31), pages 896 - 900 * |
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