CN1033252C - Method of Manufacturing Thin Film Transistor - Google Patents

Method of Manufacturing Thin Film Transistor Download PDF

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CN1033252C
CN1033252C CN 93119958 CN93119958A CN1033252C CN 1033252 C CN1033252 C CN 1033252C CN 93119958 CN93119958 CN 93119958 CN 93119958 A CN93119958 A CN 93119958A CN 1033252 C CN1033252 C CN 1033252C
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layer
gate insulating
semiconductor layer
insulating film
photoresist film
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CN1091551A (en
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吴义烈
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LG Display Co Ltd
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Venus Corp
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Priority claimed from KR1019930000263A external-priority patent/KR960008737B1/en
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Abstract

一种制造薄膜晶体管的方法，在绝缘透明衬底上形成一栅电极，再叠置多层不同折射率的栅绝缘膜，然后依次沉积半导体层、蚀刻阻止层和光刻胶膜；再经反向曝光、显影将光刻胶膜制成图形，并用其作为掩模选择蚀刻该蚀刻阻止层；再除去光刻胶膜，再依次制成n型掺杂半导体层和金属层，最后形成源、漏电极；用本法制造的薄膜晶体管用作LCD的开关元件，可改善器件特性，提高并简化工艺，提高产品生产率。

A method for manufacturing a thin-film transistor. A gate electrode is formed on an insulating transparent substrate, and then multiple layers of gate insulating films with different refractive indices are stacked, and then a semiconductor layer, an etching stopper layer and a photoresist film are deposited in sequence; To expose and develop the photoresist film into a pattern, and use it as a mask to selectively etch the etch stop layer; then remove the photoresist film, and then make an n-type doped semiconductor layer and a metal layer in sequence, and finally form the source, Drain electrode; the thin film transistor manufactured by this method is used as a switch element of LCD, which can improve the characteristics of the device, improve and simplify the process, and increase the product productivity.

Description

Make the method for thin-film transistor
The present invention relates to a kind of method of making thin-film transistor, particularly relate to the method for thin-film transistor that a kind of manufacturing is used as the switch element of liquid crystal indicator, it adopts self-registered technology, makes device be easy to make, and its characteristic is also improved.
Generally, thin-film transistor-liquid crystal display (TFT-LCD) device comprises that a preparation has base plate and top board for preparing chromatic colour filter and common electrode of TFT and each pixel capacitors.Liquid crystal just is filled in the space that is limited between upper plate and lower plate.Be used to make the polarizer of the linear polarization of visible light to be attached to relative two sides respectively such as the substrate that constitutes by glass plate.
Fig. 1 a is the equivalent circuit diagram with general TFT-LCD array of above-mentioned layout.
Fig. 1 b is the equivalent circuit diagram of unit pixel in the array shown in Fig. 1 a.
As shown in Figure 1a, the TFT-LCD device comprises a plurality of gate signal line G 1～G n, each line all is arranged between the adjacent image point zone along a direction; A plurality of data signal line D 1-D n, each line is arranged between the adjacent image point zone along the direction vertical with gate signal line direction; And a plurality of thin-film transistor Q 11～Q NnEach pipe is arranged in corresponding separately pixel area, and is suitable for basis from each corresponding gate signal line G 1-G nThe signal that comes, data voltage from each relative data wire D 1～D nBe applied to each corresponding pixel capacitors and liquid crystal.
In each unit pixel of TFT-LCD device, be provided with an additional capacitor C who forms owing to TFT LDWith a capacitor C STO, and TFT is as unit pixel and is present in the switch element of the liquid crystal between the power-on and power-off pole plate.
When the TFT-LCD device work with above-mentioned layout, a gate signal voltage is selectively imposed on the switch element TFT of each unit pixel.When TFT received gate signal voltage, TFT was with regard to conducting, and the data voltage of pictorial information imposes on corresponding pixel capacitors by TFT and liquid crystal reaches 2 hours so that carry.
When data voltage imposes on the TFT of each unit pixel, the arrangement of liquid crystal molecule is changed, cause the change of optical characteristics.Finally demonstrate an image.
In order in the TFT-LCD device, to obtain high-quality image, be used for the display area of displayed image, promptly aperture ratio or aperture efficiency should be big, and then, as much as possible little from the leakage current of TFT.
In order to improve the aperture ratio, should be reduced to the occupied area of each unit pixel TFT.This is can not show any image because form the zone of each unit pixel TFT.
Impose on the pixel capacitors of each unit pixel and the data voltage of liquid crystal by corresponding TFT, even when not applying gate signal voltage, the also capacitor C that is provided by pixel capacitors and liquid crystal STOAnd C LCKeep one section preset time.
In ideal conditions, the total amount of electric charge in the electric capacity that is formed by pixel capacitors and liquid crystal is held next signal always and is applied in to the TFT that is under the off state.And in fact, in TFT, have leakage current.When this leakage current can not fully reduce, the distortion of liquid crystal voltage may take place, scintillation can appear in the result.
Thereby compare in the aperture and the minimizing leakage current for improving in order to be implemented in the structure that obtains high quality image TFT in the TFT-LCD device, is very important.
In other words, when increasing the number of pixel for obtain high definition and high-resolution in the TFT-LCD device, the size of each TFT should reduce.And leakage current should be little of ignoring.
Recently, did many researchs energetically for the leakage current that reduces small size TFT as far as possible.
The method of a kind of manufacturing TFT of routine is described below in conjunction with accompanying drawing 2a～2e.
This kind conventional method is used to make a kind of etching prevention type (etch stopper type) TFT.
According to the method, on an insulation transparent substrate 1, form the opaque metal level of making by Al, Ta or Cr, with preparation gate electrode 2, shown in Fig. 2 a.With plasma-reinforced chemical vapour deposition (PECVD) technology, deposit gate insulating film 3, amorphous silicon layer 4 and etch stopper 5 successively on the whole exposed surface of resulting structure.Then, carve coating photoresist film 9 on the trapping layer 5 in corrosion.
Subsequently, photoresist film 9 is cured post bake under 110 ℃ of temperature.Make mask with gate electrode 2, make the lower surface of resulting structures, adopt self-aligned technology to carry out exposure backlight, shown in Fig. 2 b at substrate 1.
In this exposure backlight, in the part of receiving beam, positive photoresist film 9 is developed the agent corrosion, simultaneously owing to gate electrode 2 is the opaque parts that do not have receiving beam that retain, that is, just be positioned at the part on the gate electrode 2, remain with the part of photoresist and form the photoresist pattern.
At this moment, because scattering and diffraction phenomena, oppositely incident beam is at the edge of gate electrode 2, to the refraction of the inboard of gate electrode 2.Therefore, the size of photoresist pattern is less than the size of gate electrode 2 figures.
Make mask with the photoresist film 9 that is carved into pattern, remove the exposed position of etch stopper 5 selectively, shown in Fig. 2 C.At this moment, the overlapping length Δ L of 5 of gate electrode 2 and etch stopper is proportional to the energy of incident light.For example, be 0.5J/cm at the incident light energy 2The time, overlapping length Δ L is less than 1 μ m.
Then, on the whole exposed surface of the structure of gained in succession deposit with a high concentration n type foreign ion doped amorphous silicon layer 6 and a metal level 7, shown in Fig. 2 d.
Remove the part that is positioned at etch stopper 5 tops of high concentration n type amorphous silicon layer 6 and metal level 7 selectively, so that formation source, drain electrode 7a and 7b, shown in Fig. 2 e.So just obtain a TFT.
To introduce the working condition of the TFT that makes according to conventional methods now.
When a voltage that is not less than threshold voltage was applied in gate electrode 2, the interface between amorphous silicon layer 4 and gate insulating film 3 formed a raceway groove, thereby, make the source and leak electric mutually the communication.
Yet there is following point in this conventional method.
In the LCD device, be used as among the TFT of switch element, as shown in Figure 3, generally on the interface of gate insulating film and amorphous silicon (a-si) interlayer, form a raceway groove.Its result under the situation about existing that do not overlap between gate electrode and source/drain electrode, forms deviate region, thereby TFT can not be worked between amorphous silicon layer and source electrode.On the contrary, when overlapping length is too big, the size of TFT can be strengthened, thereby the aperture can be caused than descending.In addition, between gate electrode and source/drain electrode, can there be parasitic capacitance.When TFT turn-offed, because the coupling of this electric capacity, this parasitic capacitance can influence the voltage of liquid crystal.Its result, liquid crystal voltage has the change of Δ V, thereby causes decrease in image quality.
So preferably selecting the overlapping length between gate electrode and source/drain electrode is 1～2 μ m.
In the manufacturing of according to conventional methods TFT, be formed at single gate insulating film 3, and gate electrode 2 is used as under the condition of mask, be to adopt self-aligned technology to implement oppositely exposure.In this kind oppositely exposed, as previously mentioned, because scattering of light and diffraction phenomena, at the edge of gate electrode 2, light beam was to gate electrode 2 inboard refractions.Its result is even the figure of photoresist 9 less than the figure of gate electrode 2, can not obtain being shorter than the overlapping length of 1 μ m.In order to increase overlapping length, should carry out time exposure with high energy.
Yet this exposure method can shorten the life-span of exposure sources, spins out the time of exposure technology step.Its result has reduced productivity ratio.
Therefore according to conventional methods, only corroded etch stopper, as the width of the amorphous silicon layer of TFT active layer width greater than gate electrode with self-aligned technology.Its result when backlight enters amorphous silicon layer and acts on TFT-LCD, has excited the electronics in the amorphous silicon layer.This will increase leakage current.
Particularly, when making the LCD that was used for top (over head) projector of conventional method, it requires the light quantity will be greatly to more than 40 times of light quantity of the LCD that is used for office automation, and then leakage current also will increase, and the ON/OFF of TFT is than reducing simultaneously.Scintillation appears in its result, causes the LCD performance decrease.
So, the problems referred to above that the objective of the invention is to solve in the prior art and run into, the method of a kind of TFT of making is provided, it adopts complete autoregistration, can regulate overlapping length to 2 μ m or more than, the width of semiconductor layer is reduced to the width of gate electrode or following, thus the performance of TFT-LCD can be improved, and simplify manufacture craft.
According to the present invention, this purpose can be by providing a kind of method of making thin-film transistor to be achieved, and the step that this method comprises is as follows: form gate electrode on an insulation transparent substrate; After forming said gate electrode, on the whole exposed surface of resulting structures, by the order of the diffusing rate of lower folding, stacked multi-layer gate dielectric film with different refraction coefficients; Then, after forming said gate insulating film, on the whole exposed surface of resulting structures, deposit semi-conductor layer successively, an etch stopper and photoresist film; Make mask with said gate electrode, resulting structures oppositely exposed, said photoresist film is developed make figure then, make gate electrode can with source electrode that in subsequent step, forms and the drain electrode predetermined overlapping length that respectively overlaps; Make mask with the said photoresist film that is carved into pattern, optionally the said etch stopper of etching; Remove the photoresist film that is carved into pattern, on the whole exposed surface of resulting structures, deposit a high concentration n type doping semiconductor layer and a metal level successively then; And optionally remove the said high concentration n type doping semiconductor layer that is positioned on the etch stopper that is carved into pattern and the corresponding site of said metal level, so that form said source electrode and said drain electrode.
With reference to accompanying drawing, more clearly understand other purpose of the present invention and scheme from following elaboration meeting to embodiment.
Fig. 1 a is the equivalent circuit diagram of general TFT-LCD array;
Fig. 1 b is the equivalent circuit diagram of the unit pixel of the array shown in Fig. 1 a;
Fig. 2 a～2e is respectively the profile of method of the manufacturing TFT of interpretation routine;
Fig. 3 is a schematic cross sectional view of explaining the problem of making TFT according to conventional methods and being run into;
Fig. 4 a～4f is respectively the method for TFT is made in explanation according to the first embodiment of the present invention a profile;
Fig. 5 shows that light passes through the principle schematic of the light path of different medium;
Fig. 6 is the table of the refractive index of the various insulating material of expression;
Fig. 7 is a profile of explaining the method for making TFT according to a second embodiment of the present invention;
Fig. 8 a～8d is the profile that illustrates respectively according to the method for the manufacturing TFT of the 3rd embodiment of the present invention;
Fig. 9 a～9d is respectively the profile that explanation the 4th embodiment according to the present invention makes the method for TFT; And
Figure 10 a～10f is respectively the profile that explanation the 5th embodiment according to the present invention makes the method for TFT.
Fig. 4 a～4f is respectively the profile of explanation according to the method for first embodiment of the present invention TFT.
According to first embodiment, on the substrate 11 of an insulation transparent, form the opaque metal layer that constitutes by Al, Cr, Ta or Ti, needle drawing then is to form a gate electrode 12, shown in Fig. 4 a.
On the whole exposed surface of resulting structures, deposit the first grid dielectric film 13 of high index of refraction and second gate insulating film 14 of low-refraction successively, shown in Fig. 4 b.Preferably, the refractive index of first grid dielectric film 13 is greater than 2, and the refractive index of second gate insulating film 14 is not more than 2.With reference to Fig. 6, it has listed the refractive index of several insulation materials, Ta 2O 5And T:O 2Refractive index greater than 2, can be used for first grid dielectric film 13, and Al 2O 3, SiO 2And SiO xN yCan be used as second gate insulating film 14.Because gate insulating film 13 and 14 has this difference on refractive index, then can obtain the overlapping length of about 2 μ m, as described later.
As the Ta that forms with anodic oxidation 2O 5When dielectric film constituted first grid dielectric film 13, according to used condition, its refractive index can be regulated in 2～2.7 scopes.
Subsequently, on second gate insulating film 14, deposit semi-conductor layer 15, an etch stopper 16 and a photoresist film 17 successively.Semiconductor layer 15 can be formed by many silicon or amorphous silicon.Etch stopper 16 is by SiN xMake.
Make mask with gate electrode 12, use self-aligned technology, resulting structures is oppositely exposed, shown in Fig. 4 C.By oppositely exposure of this kind, incident beam is to gate insulating film 13 and 14 inboard refractions.
Fig. 5 represents the light path of light by various medium.Has different refractivity n 1And n 2Two media in the light path that limits, according to the Snell law, available following equation is expressed:
n 1Sin θ 1=n 2Sin θ 2(1) wherein
θ 1: light passes through n 1The angle that disseminates of medium;
θ 2: light passes through n 2The angle of propagation of medium.
Work as n 1＞n 2The time, θ 1＜θ 20On the contrary, work as n 1＜n 2The time, θ 1＞θ 20
So, when first grid dielectric film 13 and grid two dielectric films 14 are made by high material of refractive index and the low material of refractive index respectively, as mentioned above, because refraction effect, the position " a " of first grid dielectric film 13 that is positioned at the edge of gate electrode 12 is located, refraction in gate electrode 12 in the reverse step of exposure of incident beam.Position, boundary " b " between the first grid dielectric film 13 and second gate insulating film 14 is located, and incident beam is reflected in the gate electrode 12 once more.Its result, photoresist film 17 is by the exposure of the incident light of this refraction, and the overlapping length that obtains increasing.
Then, the photoresist film 17 of the light that will expose to the sun develops to figure, only stays the glued membrane of gate electrode 12 tops, forms the photoresist film figure, shown in Fig. 4 d.Make mask with the photoresist film 17 of having carved figure, the position of the etch stopper 16 of being exposed after photoresist film 17 needle drawings is optionally removed, then, remove photoresist film 17 again.
On the whole exposed surface of resulting structures, deposit a semiconductor layer 18 and a metal level 19 of mixing with high concentration n type foreign ion in succession, shown in Fig. 4 e.
Optionally remove the semiconductor layer 18 and the metal level 19 of the high concentration n type doping that is positioned at etch stopper 16 tops, with formation source and drain electrode 19a and 19b, shown in Fig. 4 f.So just obtain a TFT.
On the other hand, Fig. 7 is a profile of explaining manufacturing TFT method according to a second embodiment of the present invention.This second embodiment is similar to first embodiment, has just adopted three layers of gate insulating film structure, comprises three layers of gate insulating film with different refractivity.In Fig. 7, be marked by identical label with corresponding those elements of Fig. 4 a～4f.
According to second embodiment, on insulating glass substrate 11, form by Al, the opaque metal level that Cr, Ta or Ti make, needle drawing forms a gate electrode 12 then.
On this gate electrode 12, form by refractive index greater than 2 TaO with anode oxidation process 5Or TiO 2The first grid dielectric film of making 20.On the whole exposed surface of resulting structures, deposit successively by the SiO that such as refractive index is 1～2 2And so on second gate insulating film 21 made of material and by three gate insulating film 22 of refractive index for constituting greater than 1 but less than a kind of material of second dielectric film.Subsequently, on the 3rd dielectric film 22, deposit semi-conductor layer 15, an etch stopper 16 and a photoresist film 17 in succession.Make mask with gate electrode 12, by the mode that Fig. 4 C is described, resulting structures is oppositely exposed with self-aligned technology.Then, develop, photoresist film 17 is carved into figure.Thereafter the step of manufacturing TFT is identical with the step of first embodiment.
Gate insulating film 20,21 and 22 thickness all are not less than 1000 .
Another program is, refractive index is can be less than 1000 greater than the thickness of 1 the 3rd gate insulating film 22, all is not less than 1000 and refractive index is the thickness of 1～2 second gate insulating film 21 greater than the thickness of 2 first grid dielectric film 20 and refractive index.Even under latter event, after oppositely exposing, can get the identical effect of the same a kind of situation.Under latter event, the most handy SiO 2Film is made second gate insulating film, and its refractive index is 1～2, and its thickness is not less than 1000 , and uses SiN xFilm is made the 3rd gate insulating film, and its refractive index is 1～2, and its thickness is less than 1,000 .
Fig. 8 a～8b is respectively a profile of explaining the method for making TFT according to a fifth embodiment of the invention.The method has adopted self-aligned technology, realizing reverse exposure, and has adopted lithography corrosion process, to realize simultaneously etch stopper and semiconductor layer being scribed figure.In Fig. 8 a～8d, be marked with identical label with the corresponding element of Fig. 4 a～4f.
According to the 3rd embodiment, on an insulation transparent substrate 11, form an opaque metal level, needle drawing forms a gate electrode 12 then, shown in Fig. 8 a.On the whole exposed surface of resulting structures, deposit the first grid dielectric film 13 of high index of refraction and second gate insulating film 14 of low-refraction in succession.Then, on second gate insulating film 14, deposit semi-conductor layer 15, an etch stopper 16 and a photoresist film 17 successively.Semiconductor layer 15 can be made with many silicon or amorphous silicon.Etch stopper 16 is by SiN xMake.Make mask with gate electrode 12, use self-aligned technology,, resulting structures is oppositely exposed by the mode that Fig. 4 C is described.Then, develop, with photoresist film 17 needle drawings, so that photoresist film 17 can be had enough overlappings.
Make mask with the photoresist film 17 of carving figure, carry out the oblique etching of selectivity,, shown in Fig. 8 b, can adopt the inclination angle that is not more than 20 ° to carry out etching to remove the position that is exposed by photoresist film 17 needle drawing after etching trapping layers 16 and semiconductor layer 15.Certainly, adopt vertical etching also can remove the exposed part of layer 15 and layer 16.In addition, remove photoresist film 17.
Use a kind of oxide etch agent (BOE) solution of buffering to lose this trapping layer 16, can realize oblique etching, use etching gas CF then with wet etching 4+ O 2Or C 2ClF 5+ O 2, with dry etching semiconductor layer 15.When semiconductor layer 15 is made up of amorphous silicon layer, use etching gas C 2ClF 5: O 2Can realize oblique etching at=5: 4, and the inclination angle is not more than 20 °.
Another kind of mode is to use dry method etch technology, and etch stopper 16 and semiconductor layer 15 are carried out needle drawing.When etch stopper 16 and semiconductor layer 15 respectively by SiN xWhen layer and amorphous silicon layer constitute, use C 2ClF 5: SF 6: O 2=6: 4: 3 etching gas can carry out oblique etching simultaneously to them.
After this, on the whole exposed surface of resulting structures, deposit a semiconductor layer 18 and a metal level 19 that high concentration n mixes successively, shown in Fig. 8 C.Selectivity is removed the semiconductor layer 18 and the metal level 19 of the high concentration n type doping of etch stopper 16 tops deposition, so that formation source and drain electrode 19a and 19b, shown in Fig. 8 b.So just obtained a TFT.
When making TFT, as the width of the semiconductor layer 15 of TFT active layer width less than gate electrode 12 according to the 3rd embodiment.
Fig. 9 a～9d is a profile of representing the method for a fourth embodiment in accordance with the invention manufacturing TFT respectively.According to this method, the oblique etching method shown in employing Fig. 8 a and Fig. 8 b is realized the needle drawing to etch stopper and semiconductor layer.With the exposed part of high concentration n type foreign ion injection semiconductor layer, to form the semiconductor layer that high concentration n type mixes.According to the method, between high concentration n type doping semiconductor layer that deposits successively and metal level, also form a silicide layer, separate resistance so that reduce connecing of interface.In Fig. 9 a～9d, be marked with identical label with components identical among Fig. 4 a～4f.
According to the 4th embodiment, on a dielectric substrate 11, form an opaque metal level, needle drawing forms a gate electrode 12 then, shown in Fig. 9 a.On the whole exposed surface of resulting structures, deposit the first grid dielectric film 13 of high index of refraction and second gate insulating film 14, semiconductor layer 15, etch stopper 16 and the photoresist film 17 of low-refraction successively.Make mask with gate electrode 12, resulting structures oppositely exposes with self-aligned technology subsequently.After this, develop and make photoresist film 17 be carved into figure.
Make mask with the photoresist film 17 that is carved into figure, selective corrosion etch stopper 16 and semiconductor layer 15.Remove photoresist film 17 then.
Be injected into the exposed both side surface of the semiconductor layer 15 of carving figure with high concentration n type foreign ion, to form the semiconductor layer 23 that high concentration n type mixes, shown in Fig. 9 b.Ion injects and need not adopt any formation technology to finish, and just adopts the etch stopper 16 that is carved into figure to make mask simply and gets final product.
Inject at ion, use PH 3Gas and H 2Gas injects phosphonium ion.
Then, on the whole exposed surface of resulting structures deposition by as have dystectic Cr or Mo constitutes high melting point metal layer 19, annealing then is shown in Fig. 9 C.In annealing steps, high melting point metal layer 19 reacts with high concentration n type doping semiconductor layer 23, forms silicide layer 24 at its interface respectively, shown in Fig. 9 d.When high melting point metal layer 19 was made of Cr, the silicide of generation was CrSi xForm.On the other hand, under the situation of using Mo, the silicide of formation is MoSi xForm.At last, optionally remove the high melting point metal layer 19 that is positioned on the etch stopper 16, with formation source and drain electrode 19a and 19b.This has just obtained TFT.
According to the 4th embodiment, etch stopper, semiconductor layer figure and high concentration n type doping semiconductor layer use up the fully self aligned technology and form.So, simplified manufacturing process.
Figure 10 a～10f is respectively a profile of explaining the method for making TFT according to a fifth embodiment of the invention.According to this method, etch stopper and semiconductor layer are carried out two independently needle drawing steps, replace above-mentioned needle drawing step of carrying out simultaneously.Carrying out ion injects and forms high concentration n type doping semiconductor layer.According to this method, also form one deck silicide.In Figure 10 a～10f, be marked with identical label with corresponding those elements among Fig. 4 a～4f.
According to the 5th embodiment, on the substrate 11 of an insulation transparent, form an opaque metal level, needle drawing forms a gate electrode 12 then, shown in Figure 10 a.On the whole exposed surface of resulting structures, deposit the first grid dielectric film 13 of a high index of refraction and second gate insulating film 14, semi-conductor layer 15, an etch stopper 16 and first photoresist film 17 of low-refraction in succession.
Make mask with gate electrode 12, use self-aligned technology, resulting structures is oppositely exposed.Then, developing carves the figure of first photoresist film 17, shown in Figure 10 b.Make mask with the photoresist film 17 that carves, selective corrosion etch stopper 16.Subsequently, remove first photoresist film 17.
On the whole exposed surface of resulting structures, deposit second photoresist film 25, shown in Figure 10 C.Make mask with gate electrode 12, adopt self-aligned technology, resulting structures is oppositely exposed.Then, develop and carve the figure of second photoresist film 25.Make mask with the photoresist film 25 that carves, selective etch semiconductor layer 15.
Finish after the needle drawing step, the width of the semiconductor layer 15 after the needle drawing should be greater than the width of etch stopper 16, but less than the width of gate electrode 12.For this reason, first photoresist film 17 is implemented the used energy of exposure and be higher than the energy (Power x time) used second photoresist film 25.Perhaps, linearly polarized photon is incided substrate 11 with 45, to 17 exposures of first photoresist film, to 90 ° of incidence angle exposures of cured 25 usefulness of second photoresist.Thereby photoresist film 17 can be carved the different figure of width with 25.Adopt the photoresist film 17 and 25 carve in a manner described, scribe the figure of semiconductor layer 15, its width is greater than etch stopper 16, but less than the width of gate electrode 12.
Then, remove second photoresist film 25, shown in Figure 10 d, make mask, high concentration n type foreign ion is injected into two exposed positions, outer end of the semiconductor layer 15 after the needle drawing, to form the semiconductor layer 23 that high concentration n type mixes with etch stopper 16.
Then, on resulting structures and whole exposed surface, the high melting point metal layer 19 that deposition is made of a kind of metal such as Cr or Mo is implemented annealing, then shown in Figure 10 e.In annealing steps, high melting point metal layer 19 reacts with semiconductor layer 15 and 23, thereby respectively in the zone that high melting point metal layer 19 and semiconductor layer 15 contact with 23, forms silicide layer 24.Each silicide layer 24 all is that its etching selectivity is higher than metal level 19 and semiconductor layer 15 and 23 from the product of metal level 19 and semiconductor layer 15 and 23 reactions.
At last, selective etch removes the high melting point metal layer 19 that is positioned at these etch stopper 16 tops, with formation source and drain electrode 19a and 19b.So just made TFT.
In order only to remove the part metals layer 19 that is positioned at etch stopper 16 tops, as mentioned above, available another photoresist film makes as the photoresist film mask metal level that is positioned at etch stopper 16 tops is partly exposed.Then, adopt the photoresist film mask, selectivity is removed the metal level part of being exposed.In the case, compare, a bigger tolerance is provided with photoetching process.This be because, both made when in the process that forms the photoresist film mask, a little misalignment occurring, just become etching stopping layer with the silicide layer 24 that semiconductor layer 15 and 23 interfaces form respectively at metal level 19.In the case, source and drain electrode 19a and 19b can be formed directly in, and need not form silicide layer 24.
Said method of the present invention has following effect:
The first, can obtain enough overlapping length, because adopt the difference of the refractive index of the different gate insulating film of two or three refractive index the overlapping length adjustment can be reached 2 μ m or longer.Its result can realize the improvement of productivity ratio;
The second, the leakage current that backlight causes is reduced to minimum value, because the width of semiconductor layer is less than the width of gate electrode.Owing between semiconductor and metal level, formed silicide layer, can reduce contact resistance, thereby improve Devices Characteristics;
The 3rd, realized the simplification of manufacturing process and improved productivity ratio, because adopt self-registered technology to form high concentration n type doping semiconductor layer by injecting n type foreign ion.
The 4th, when the TFT that makes according to one of said method is used as the switch element of LCD, can improve the image quality of LCD.
Though, for the purpose of explaining, having introduced the most preferred embodiment of invention, those skilled in the art should understand: under the situation that does not break away from the spirit of the present invention set forth as claims and category, can make various changes, replenish and replace.

Claims (22)

1.一种制造薄膜晶体管的方法，包括下列各步骤：1. A method for manufacturing a thin film transistor, comprising the following steps: 在一绝缘透明的衬底上形成一栅电极，其上形成有栅绝缘膜；forming a gate electrode on an insulating and transparent substrate, on which a gate insulating film is formed; 在所说的栅绝缘膜形成之后，在所得结构的整个裸露表面上，依次沉积一半导体层、一蚀刻阻止层和一光刻胶膜；After said gate insulating film is formed, on the entire exposed surface of the resulting structure, a semiconductor layer, an etching stopper layer and a photoresist film are sequentially deposited; 用所说的栅电极作掩模，使所得结构经反向曝光，然后显影，将所述光刻胶膜刻成图形；Using the gate electrode as a mask to reversely expose the resulting structure, and then develop it, and engrave the photoresist film into a pattern; 其特征在于：经所述反向曝光、显影，对所述光刻胶膜刻制图形，使栅电极可与每个在后续步骤形成的源电极和漏电极按预定的交叠长度交叠，还包括步骤：在所说的栅电极形成之后，在所得结构的整个裸露表面上，按折射率由大至小的顺序叠置多层具有不同折射率的栅绝缘膜；It is characterized in that: after the reverse exposure and development, the photoresist film is patterned, so that the gate electrode can overlap with each source electrode and drain electrode formed in the subsequent steps according to a predetermined overlapping length, It also includes the step of: after the formation of the gate electrode, on the entire exposed surface of the obtained structure, stack a plurality of gate insulating films with different refractive indices in descending order of the refractive index; 用所说的刻成图的光刻胶膜作掩模，选择性蚀刻所说的蚀刻阻止层；Using said patterned photoresist film as a mask, selectively etching said etch stop layer; 去掉刻成图的光刻胶膜，然后在所得结构的整个裸露表面上，依次沉积一高浓度n型掺杂半导体层和一金属层；以及removing the patterned photoresist film, and then sequentially depositing a high-concentration n-type doped semiconductor layer and a metal layer on the entire exposed surface of the resulting structure; and 选择性去掉位于刻成图的蚀刻阻止层上方的所说的高浓度n型掺杂半导体层和所说的金属层的相应部分，以形成所说的源电极和所说的漏电极。Selectively removing said highly concentrated n-type doped semiconductor layer and corresponding portions of said metal layer above the patterned etch stop layer to form said source electrode and said drain electrode. 2.一种根据权利要求1所述的方法，其中所说的栅绝缘膜由双层结构构成，包括折射率大于2的第一栅绝缘膜和折射率不大于2的第二栅绝缘膜。2. A method according to claim 1, wherein said gate insulating film is composed of a double-layer structure comprising a first gate insulating film having a refractive index greater than 2 and a second gate insulating film having a refractive index not greater than 2. 3.一种根据权利要求2所述的方法，其中所说的第一栅绝缘膜由Ta2O5或TiO2制成，而所说的第二栅绝缘膜由Al2O5、SiO2和SiOXNY中之一种构成。3. A method according to claim 2, wherein said first gate insulating film is made of Ta 2 O 5 or TiO 2 , and said second gate insulating film is made of Al 2 O 5 , SiO 2 and one of SiO X N Y. 4.一种根据权利要求1所述的方法，其中所说的栅绝缘膜由三层结构构成，包括折射率大于2的第一栅绝缘膜、折射率为1～2的第二栅绝缘膜以及折射率小于所述第二栅绝缘膜的折射率的第三栅绝缘膜。4. A method according to claim 1, wherein said gate insulating film is composed of a three-layer structure, comprising a first gate insulating film with a refractive index greater than 2, a second gate insulating film with a refractive index of 1-2 and a third gate insulating film having a refractive index lower than that of the second gate insulating film. 5.一种根据权利要求4所述的方法，其中所说的第一栅绝缘膜其厚度不小于1000，所说的第二栅绝缘膜其厚度不小于1000，而所说的第三栅绝缘膜其厚度小于1000。5. A method according to claim 4, wherein said first gate insulating film has a thickness of not less than 1000 Å, said second gate insulating film has a thickness of not less than 1000 Å, and said third gate insulating film has a thickness of not less than 1000 Å. The gate insulating film has a thickness of less than 1000 Å. 6.一种根据权利要求4所述的方法，其中所说的第二栅绝缘膜和所说的第三栅绝缘膜分别由SiO2和SiNx构成的。6. A method according to claim 4, wherein said second gate insulating film and said third gate insulating film are formed of SiO2 and SiNx , respectively. 7.一种根据权利要求1所述的方法，其中所说的形成栅电极和叠置多层栅绝缘膜的过程包括下列步骤：7. A method according to claim 1, wherein said process of forming a gate electrode and stacking a plurality of gate insulating films comprises the following steps: 用可阳极氧化的金属形成所说的栅电极；forming said gate electrode from an anodizable metal; 阳极氧化所述栅电极，在该栅电极的表面上形成第一栅绝缘膜；以及anodizing the gate electrode to form a first gate insulating film on a surface of the gate electrode; and 在所得结构的整个裸露表面上，依次形成折射率小于第一栅绝缘膜的第二栅绝缘膜，及折射率小于第二栅绝缘膜的第三栅绝缘膜。On the entire exposed surface of the resulting structure, a second gate insulating film having a lower refractive index than the first gate insulating film, and a third gate insulating film having a lower refractive index than the second gate insulating film are sequentially formed. 8.一种根据权利要求7所述的方法，其中所说的栅电极是由Ta或Ti制成的。8. A method according to claim 7, wherein said gate electrode is made of Ta or Ti. 9.一种根据权利要求1所述的方法，其中所说的预定交叠长度为1～2μm。9. A method according to claim 1, wherein said predetermined overlapping length is 1-2 [mu]m. 10.一种制造薄膜晶体管的方法，包括下列各步骤：10. A method of manufacturing a thin film transistor, comprising the steps of: 在一绝缘透明的衬底上形成一栅电极，其上形成有栅绝缘膜；forming a gate electrode on an insulating and transparent substrate, on which a gate insulating film is formed; 在所说的栅绝缘膜形成之后，在所得结构的整个裸露表面上，依次沉积一半导体层、一蚀刻阻止层和一光刻胶膜；After said gate insulating film is formed, on the entire exposed surface of the resulting structure, a semiconductor layer, an etching stopper layer and a photoresist film are sequentially deposited; 用所说的栅电极作掩模，使所得结构经反向曝光，然后显影，将所述光刻胶膜刻成图形；Using the gate electrode as a mask to expose the resulting structure in reverse, and then develop it to pattern the photoresist film; 其特征在于，还包括步骤：在所说的栅电极形成之后，在所得结构的整个裸露表面上，按折射率由大至小的顺序叠置多层具有不同折射率的栅绝缘膜；It is characterized in that it also includes the step of: after the formation of the gate electrode, on the entire exposed surface of the obtained structure, stack multiple gate insulating films with different refractive indices in order of refractive index from large to small; 用所说的刻成图的光刻胶膜作掩模，选择性蚀刻所说的蚀刻阻止层；Using said patterned photoresist film as a mask, selectively etching said etch stop layer; 所说的蚀刻为斜向蚀刻，在蚀刻该蚀刻阻止层的同时也蚀刻所说的半导体层；Said etching is oblique etching, and said semiconductor layer is also etched while etching the etching stopper layer; 去掉刻成图的光刻胶膜，然后在所得结构的整个裸露表面上，依次沉积一高浓度n型掺杂半导体层和一金属层；以及removing the patterned photoresist film, and then sequentially depositing a high-concentration n-type doped semiconductor layer and a metal layer on the entire exposed surface of the resulting structure; and 选择性去掉位于刻成图的蚀刻阻止层上方的所说的高浓度n型掺杂半导体层和所说的金属层的相应部分，以形成所说的源电极和所说的漏电极。Selectively removing said highly concentrated n-type doped semiconductor layer and corresponding portions of said metal layer above the patterned etch stop layer to form said source electrode and said drain electrode. 11.一种根据权利要求10所述的方法，其中所说的蚀刻阻止层和所说的半导体层，在所说的蚀刻阻止层和所说的半导体层的步骤中是有选择地竖直蚀刻的。11. A method according to claim 10, wherein said etch stop layer and said semiconductor layer are selectively vertically etched in the step of said etch stop layer and said semiconductor layer of. 12.一种根据权利要求10所述的方法，还包括继所说的蚀刻阻止层和所说的半导体层的步骤之后进行的下述步骤：12. A method according to claim 10, further comprising the step of following the steps of said etch stop layer and said semiconductor layer: 向刻成图的半导体层两侧的裸露表面注入高浓度n型杂质离子，以形成高浓度n型掺杂半导体层；以及Implanting high-concentration n-type impurity ions into the exposed surfaces on both sides of the patterned semiconductor layer to form a high-concentration n-type doped semiconductor layer; and 在所得结构的整个裸露表面上沉积高熔点金属层，并使所说的高熔点金属层退火，以在金属层和每个所说的高浓度n型掺杂半导体层间的界面形成一硅化物层。depositing a refractory metal layer over the entire exposed surface of the resulting structure, and annealing said refractory metal layer to form a silicide at the interface between the metal layer and each of said heavily n-type doped semiconductor layers layer. 13.一种根据权利要求12所述的方法，其中在所说的包括磷离子注入的高浓度n型杂质离子注入步骤中是用PH3气体和H2气体注入磷离子。13. A method according to claim 12, wherein in said high-concentration n-type impurity ion implantation step including phosphorus ion implantation, phosphorus ions are implanted with PH3 gas and H2 gas. 14.一种根据权利要求12所述的方法，所说的高熔点金属层是由Cr或Mo制成的。14. A method according to claim 12, said refractory metal layer is made of Cr or Mo. 15.一种根据权利要求10所述的方法，其中所说的蚀刻阻止层和所说的半导体层的步骤包括下列步骤：15. A method according to claim 10, wherein the step of etching the stop layer and the semiconductor layer comprises the steps of: 用刻成图的光刻胶膜作掩模，用缓冲氧化腐蚀剂溶液，湿法蚀刻所说的蚀刻阻止层；以及wet etching said etch stop layer with a buffered oxide etchant solution using the patterned photoresist film as a mask; and 在与所说的湿法蚀刻步骤相同的掩模条件下，用CF4＋O2或C2ClF5＋O2作蚀刻气体，干法蚀刻所说的半导体层。Under the same mask conditions as in the wet etching step, the semiconductor layer is dry etched using CF 4 +O 2 or C 2 ClF 5 +O 2 as an etching gas. 16.一种根据权利要求15所述的方法，其中半导体层由非晶硅制成，采用C2ClF5∶O2＝5∶4的蚀刻气体。16. A method according to claim 15, wherein the semiconductor layer is made of amorphous silicon, and an etching gas of C 2 ClF 5 :O 2 =5:4 is used. 17.一种根据权利要求10所述的方法，其中所说的蚀刻阻止层和所说的半导体层分别由SiNx和非晶硅制成，在所说的蚀刻阻止层和所说的半导体层的步骤中：用C2ClF5∶SF6∶O2＝6∶4∶3的蚀刻气体，同时对它们进行蚀刻。17. A method according to claim 10, wherein said etch stopper layer and said semiconductor layer are made of SiN x and amorphous silicon respectively, and said etch stopper layer and said semiconductor layer In the step: use the etching gas of C 2 ClF 5 :SF 6 :O 2 =6:4:3 to etch them at the same time. 18.一种根据权利要求10或12所述的方法，其中在所说的蚀刻阻止层和所说的半导体层的步骤中：进行的斜向蚀刻的倾角不大于20°。18. A method according to claim 10 or 12, wherein in the step of etching the stopper layer and the semiconductor layer: oblique etching is performed with an inclination angle of not more than 20°. 19.一种制造薄膜晶体管的方法，包括下列各步骤：19. A method of manufacturing a thin film transistor, comprising the steps of: 在一绝缘透明的衬底上形成一栅电极，其上形成有栅绝缘膜；forming a gate electrode on an insulating and transparent substrate, on which a gate insulating film is formed; 在所说的栅绝缘膜形成之后，在所得结构的整个裸露表面上，依次沉积一半导体层、一蚀刻阻止层和一第一光刻胶膜；After said gate insulating film is formed, on the entire exposed surface of the resulting structure, depositing a semiconductor layer, an etching stopper layer and a first photoresist film in sequence; 用所说的栅电极作掩模，对所得结构进行首次反向曝光，然后显影，将所述第一光刻胶膜刻成图形；Using the gate electrode as a mask, the first reverse exposure is carried out to the obtained structure, and then developing, and the first photoresist film is engraved into a pattern; 其特征在于：经所述首次反向曝光、显影，对所述第一光刻胶膜刻制图形，使刻成图的第一光刻胶膜的宽度小于栅电极的宽度，还包括步骤：It is characterized in that: after the first reverse exposure and development, the first photoresist film is patterned so that the width of the patterned first photoresist film is smaller than the width of the gate electrode, further comprising the steps of: 在所说的栅电极形成之后，在所得结构的整个裸露表面上，按折射率由大至小的顺序叠置多层具有不同折射率的栅绝缘膜；After said gate electrode is formed, on the entire exposed surface of the resulting structure, stack multiple gate insulating films with different refractive indices in descending order of refractive index; 用所说的刻成图的第一光刻胶膜作掩模，选择性蚀刻所说的蚀刻阻止层；Using said first photoresist film carved into a pattern as a mask, selectively etching said etch stop layer; 去掉该刻成图的第一光刻胶膜，在所得结构的整个裸露表面上，沉积一第二光刻胶膜，用栅电极作掩模，对所得结构进行再次反向曝光，然后显影，将所述第二光刻胶膜刻成图形，以使刻成图的第二光刻胶膜的宽度小于栅电极的宽度，但大于刻成图的蚀刻阻止层的宽度；removing the patterned first photoresist film, depositing a second photoresist film on the entire exposed surface of the resulting structure, using the gate electrode as a mask, performing reverse exposure on the resulting structure again, and then developing, Patterning the second photoresist film, so that the width of the patterned second photoresist film is smaller than the width of the gate electrode, but greater than the width of the patterned etch stop layer; 用所说的刻成图的第二光刻胶膜作掩模，选择性蚀刻所说的半导体层；Using said second photoresist film carved into a pattern as a mask, selectively etching said semiconductor layer; 去掉该刻成图的第二光刻胶膜，然后在所得结构的相应裸露表面上依次形成高浓度n型掺杂半导体层和金属层；removing the patterned second photoresist film, and then sequentially forming a high-concentration n-type doped semiconductor layer and a metal layer on the corresponding exposed surface of the resulting structure; 所说的高浓度n型半导体层的形成是以刻成图的蚀刻阻止层作掩模，向刻成图的半导体层的裸露的两外端部位注入高浓度n型杂质离子，然后在所得结构的整个裸露表面上沉积所述的金属层；The formation of the said high-concentration n-type semiconductor layer is to use the patterned etch stop layer as a mask, and implant high-concentration n-type impurity ions into the exposed two outer ends of the patterned semiconductor layer, and then form the resulting structure depositing said metal layer on the entire exposed surface of the 给所说的金属层退火，以在金属层和半导体层间的界面形成一硅化物层；以及annealing said metal layer to form a silicide layer at the interface between the metal layer and the semiconductor layer; and 选择性去掉位于刻成图的蚀刻阻止层上方的部分金属层，以形成所说的源电极和所说的漏电极。Portions of the metal layer overlying the patterned etch stop layer are selectively removed to form said source electrode and said drain electrode. 20.一种根据权利要求19所述的方法，其中所说的首次反向曝光和所说的再次反向曝光是在首次反向曝光所用光能大于再次反向曝光所用光能的条件下完成的，以使刻成图的半导体层的宽度可以大于所说的刻成图的蚀刻阻止层的宽度，但小于栅电极的宽度。20. A method according to claim 19, wherein said reverse exposure for the first time and said reverse exposure again are completed under the condition that the light energy used for the first reverse exposure is greater than the light energy used for the reverse exposure again so that the width of the patterned semiconductor layer can be greater than the width of the patterned etch stop layer but smaller than the width of the gate electrode. 21.一种根据权利要求19所述的方法，其中，线性偏振光在首次反向曝光中是以45°角入射到所说的衬底上的，在再次反向曝光中是以90°角入射到所说的衬底上的。21. A method according to claim 19, wherein linearly polarized light is incident on said substrate at an angle of 45° in the first reverse exposure and at an angle of 90° in the second reverse exposure incident on the substrate. 22.一种根据权利要求19所述的方法，其中，所说的源电极和漏电极的形成不需形成所说的硅化物层。22. A method according to claim 19, wherein said source and drain electrodes are formed without forming said silicide layer.
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