CN103311200A - Chip package - Google Patents
Chip package Download PDFInfo
- Publication number
- CN103311200A CN103311200A CN2012100574914A CN201210057491A CN103311200A CN 103311200 A CN103311200 A CN 103311200A CN 2012100574914 A CN2012100574914 A CN 2012100574914A CN 201210057491 A CN201210057491 A CN 201210057491A CN 103311200 A CN103311200 A CN 103311200A
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- Prior art keywords
- soldered ball
- solder balls
- row
- chip encapsulation
- distance
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Abstract
The invention relates to a chip package. The chip package comprises a substrate and solder balls, wherein the solder balls are distributed on the substrate in an array, the row spacing between the outmost row and the secondarily outmost row of the array type solder balls is smaller than the row spacing between other adjacent rows, and the column spacing between the outmost column and the secondarily outmost column of the array type solder balls is smaller than the column spacing between other adjacent columns. According to the chip package disclosed by the invention, by appropriately shortening the distance between the solder balls not requiring wiring and increasing the distance between the solder balls requiring wiring on the premise of not increasing the size of a chip, wire width is increased, product cost and processing difficulty are effectively reduced, and the qualified rate of products is significantly increased.
Description
Technical field
The present invention relates to the chip encapsulation field, relate in particular to a kind of chip BGA Package.
Background technology
Electronic product has entered SMT (Surface Mount Technology, surface mounting technology) epoch, at present along with electronic product develops to portable, miniaturization, the progressively miniaturization of export-oriented size of mount components, the mount components package pitch is to thin space more development, the especially BGA of 0.5mm and the following spacing of 0.5mm (Ball Grid Array, BGA Package), very high to the wiring required precision on the PCB (Printed Circuit Board, printed circuit board (PCB)), the wiring difficulty is big.
Fig. 1 is the chip-packaging structure schematic diagram of prior art, as shown in Figure 1, the chip length of side d1 of prior art is 4.0mm, spacing d2 between the adjacent solder balls is 0.5mm, because the restriction of spacing between the adjacent solder balls, the width of pcb board line when wiring is 0.075mm, because line makes that too carefully cost height, the difficulty of processing of product are big, and influences product percent of pass.
Summary of the invention
The objective of the invention is to propose the encapsulation of a kind of chip, be intended to solve the traditional die encapsulation, the big problem of cost height, difficulty of processing of the product that line that can only cloth 0.075mm width causes.
For achieving the above object, the invention provides a kind of chip encapsulation, described chip encapsulation comprises: substrate; Soldered ball, described soldered ball become array to be distributed on the described substrate, and the line space between described array soldered ball outermost row and time layman is less than the line space between other adjacent lines; Column pitch between described array soldered ball outermost row and time outer row is less than the column pitch between other adjacent columns.
The chip encapsulation that the present invention proposes, under the situation that does not increase chip size, by adopting the distance between the soldered ball that suitable shortening need not to connect up, increase the distance between the soldered ball that needs wiring, thereby increased the width of line, effectively reduce product cost and difficulty of processing, significantly increase the qualification rate of product.
Description of drawings
Fig. 1 is the chip-packaging structure schematic diagram of prior art;
Fig. 2 is the structural representation of the invention process spr chip encapsulation;
Fig. 3 is the wiring schematic diagram of pcb board of the chip encapsulation of the embodiment of the invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 2 is the structural representation of the invention process spr chip encapsulation, as shown in Figure 2, the chip encapsulation of the embodiment of the invention comprises substrate 201 and soldered ball 202, BGA Package is adopted in the chip encapsulation of the embodiment of the invention, 202 one-tenth arrays of soldered ball are distributed on the substrate 201, are distributed with number row and ordered series of numbers soldered ball 202 on the substrate 201.Substrate 201 is square, and its length of side D1 is 4.0mm; Each row is distributed with 8 soldered balls 202, and each row also is distributed with 8 soldered balls 202, and the diameter D2 of soldered ball 202 is 0.25mm; Matrix form soldered ball outermost row is 0.45mm to the line space D3 between time layman, and the column pitch D3 that outermost is listed as between the inferior outer row is 0.45mm.Space D 4 between other adjacent lines and the adjacent columns is 0.53mm.
It is in order to be easy to the wiring of pcb board that distance between the soldered ball of the invention process spr chip encapsulation adopts such design.On the pcb board of the chip of embodiment of the invention encapsulation, the diameter of soldered ball suitably can be reduced into 0.22mm, namely the D2 ' of soldered ball is 0.22mm on pcb board.When pcb board connects up, need not to connect up between the soldered ball of outermost four corners, thereby centre of sphere distance B 3 is for need not wiring between the soldered ball of 0.45mm, have only centre of sphere distance B 4 for connecting up between the soldered ball of 0.53mm, the distance that can calculate between the soldered ball that needs on the pcb board to connect up by formula (1) is:
L＝D4-D2′ (1)
Distance L between the soldered ball that the substitution data need to connect up as can be known is 0.31mm.Pcb board wiring the time should make minimum length 0.1mm between line and the soldered ball, cause line and ball to be sticked together in order to avoid line and ball distance is too near.It is 0.11mm that distance between the adjacent solder balls deducts the diameter that distance between line and the both sides soldered ball can get outlet.As can be seen, when the distance between the soldered ball was 0.53mm, the width that connects up on the pcb board can reach 0.1mm, was that 0.075mm compares with the width that connects up on the pcb board, can in the cost that effectively reduces product, reduce the processing of product, significantly promote the qualification rate of product.
The chip encapsulation of prior art, evenly distribute between the soldered ball, soldered ball ranks spacing is 0.5mm, then the distance between the soldered ball is 0.28mm, the width that connects up on the pcb board can only adopt the width of 0.075mm like this, and in the process of pcb board wiring, more fining-off technological requirement of line is more high, difficulty of processing is more big, and the cost of product is higher relatively.
Compare with the chip encapsulation of prior art, the chip encapsulation of the embodiment of the invention has changed the equally distributed pattern of traditional soldered ball, adopt the distance that suitably shortens between the soldered ball that need not to connect up, increase the distance between the soldered ball that needs wiring, thereby increased the width of wiring, effectively reduce product cost and difficulty of processing, significantly increased the qualification rate of product.
Fig. 3 is the wiring schematic diagram of pcb board of the chip encapsulation of the embodiment of the invention, and as shown in Figure 3, each soldered ball 202 can cloth holding wire 301 (being the line of mentioning in the preamble), links to each other with external devices by holding wire 301, realizes various functions.Holding wire 301 spaces of outermost layer soldered ball 202 need not to consider the influence to the width of line more greatly, the holding wire 301 of internal layer soldered ball 202 need pass from the space of two outer soldered balls 202, thereby the spacing size between two soldered balls 202 has directly influenced the width of holding wire 301.Again as shown in Figure 3, the chip encapsulation of the embodiment of the invention is suitably dwindled the distance between two soldered balls of corner, the distance between other two soldered balls is increased, thereby make the width D 5 of holding wire 301 can reach 0.1mm, can effectively reduce product cost, and significantly increase product percent of pass.
The chip encapsulation of the embodiment of the invention has changed the equally distributed pattern of traditional soldered ball, under the situation that does not change chip size, adopt the distance that suitably shortens between the soldered ball that need not to connect up, increase the distance between the soldered ball that needs wiring, thereby increase the width of line, effectively reduce product cost, reduce difficulty of processing, significantly increase the qualification rate of product.
Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is the specific embodiment of the present invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a chip encapsulation is characterized in that, described chip encapsulation comprises:
Substrate;
Soldered ball, described soldered ball become array to be distributed on the described substrate, and the line space between described array soldered ball outermost row and time layman is less than the line space between other adjacent lines; Column pitch between described array soldered ball outermost row and time outer row is less than the column pitch between other adjacent columns.
2. chip encapsulation as claimed in claim 1 is characterized in that, the line space between described array soldered ball outermost row and time layman is 0.45mm.
3. chip encapsulation as claimed in claim 2 is characterized in that the line space between described other adjacent lines of array soldered ball is 0.53mm.
4. chip encapsulation as claimed in claim 1 is characterized in that, the column pitch between described array soldered ball outermost row and time outer row is 0.45mm.
5. chip encapsulation as claimed in claim 4 is characterized in that the column pitch between described other adjacent columns of array soldered ball is 0.53mm.
6. chip encapsulation as claimed in claim 1 is characterized in that the diameter of described soldered ball is 0.25mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210057491.4A CN103311200B (en) | 2012-03-06 | 2012-03-06 | Chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210057491.4A CN103311200B (en) | 2012-03-06 | 2012-03-06 | Chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103311200A true CN103311200A (en) | 2013-09-18 |
| CN103311200B CN103311200B (en) | 2016-05-18 |
Family
ID=49136257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210057491.4A Active CN103311200B (en) | 2012-03-06 | 2012-03-06 | Chip package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103311200B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040067704A (en) * | 2003-01-24 | 2004-07-30 | 엘지전자 주식회사 | Method of manufacturing MCM ball grid array package |
| CN1983581A (en) * | 2005-12-12 | 2007-06-20 | 松下电器产业株式会社 | Semiconductor device |
| US20070200229A1 (en) * | 2006-02-27 | 2007-08-30 | Daubenspeck Timothy H | Chip underfill in flip-chip technologies |
| US20080217770A1 (en) * | 2007-03-09 | 2008-09-11 | Nec Corporation | Mounting configuration of electronic component |
-
2012
- 2012-03-06 CN CN201210057491.4A patent/CN103311200B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040067704A (en) * | 2003-01-24 | 2004-07-30 | 엘지전자 주식회사 | Method of manufacturing MCM ball grid array package |
| CN1983581A (en) * | 2005-12-12 | 2007-06-20 | 松下电器产业株式会社 | Semiconductor device |
| US20070200229A1 (en) * | 2006-02-27 | 2007-08-30 | Daubenspeck Timothy H | Chip underfill in flip-chip technologies |
| US20080217770A1 (en) * | 2007-03-09 | 2008-09-11 | Nec Corporation | Mounting configuration of electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103311200B (en) | 2016-05-18 |
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