CN103296070A - NAND memory based on nanocrystalline and manufacturing method thereof - Google Patents
NAND memory based on nanocrystalline and manufacturing method thereof Download PDFInfo
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- CN103296070A CN103296070A CN2012100485785A CN201210048578A CN103296070A CN 103296070 A CN103296070 A CN 103296070A CN 2012100485785 A CN2012100485785 A CN 2012100485785A CN 201210048578 A CN201210048578 A CN 201210048578A CN 103296070 A CN103296070 A CN 103296070A
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Abstract
The invention relates to a nanocrystalline-based NAND memory and a manufacturing method thereof. The nanocrystalline storage unit comprises a silicon substrate, a source conduction region and a drain conduction region which are positioned on two sides in the silicon substrate, a tunneling dielectric layer covered on a carrier channel between the source conduction region and the drain conduction region, a nanocrystalline charge storage layer covered on the tunneling dielectric layer, a control gate dielectric layer covered on the nanocrystalline charge storage layer, and a gate electrode material layer covered on the control gate dielectric layer. The selection transistor comprises a silicon substrate, a source conduction region and a drain conduction region which are positioned on two sides in the silicon substrate, a dielectric layer covered on a carrier channel between the source conduction region and the drain conduction region, and a gate electrode material layer covered on the dielectric layer. The invention can reduce the area of the chip in a large scale, and simultaneously can save 1 to 2 photomasks because the source-drain junction in the middle part of the memory unit is saved, thereby saving the cost and preparing for the next generation of storage.
Description
Technical field
The present invention relates to nano electron device and technical field of nano-processing, be specifically related to a kind of based on nanocrystalline nand memory and preparation method thereof.
Background technology
In recent years, the growth rate of memory has surpassed logical circuit in the integrated circuit, the ratio that memory accounts for chip area by 1999 20% increase to nearly 80% in 2007, logical circuit then by 1999 66% drop to 2007 14%.In memory product, the market demand is fastest-rising to be nonvolatile memory.Flash memory (Flash Memory) has been widely used in the multiple hand-held mobile storage electronic products such as USB flash disk, MP3 player and mobile phone at present as the typical device of nonvolatile memory.Yet at present extensively by flash memory device structure that industrial quarters adopted in the nanometer feature sizes development, be faced with stern challenge at aspects such as memory time and power consumptions.
Based on the nano-crystal floating gate nonvolatile memory cell of nanocrystalline structure be utilize nanocrystalline as charge storage media, each nano-crystalline granule is with crystal grain insulation on every side and only store a small amount of several electrons, thereby realize discrete charge storage, reduced the harm that the defective on the tunneling medium layer forms fatal discharge channel, only can cause local electric charge on nanocrystalline to leak, make the maintenance of electric charge more stable.Following nano-crystal floating gate nonvolatile memory cell is potential to provide higher integration density, lower write/erase voltage, write/erase speed, higher tolerance, stronger data retention characteristics and the ability of multidigit storage faster for application memory equipment.
Traditional nand memory, the flush memory device of its memory cell for separating, this just requires to have between each device knot to link together, thus area is very big.And based on the enable nand gate of nano-crystal memory since nanocrystalline be to separate storage, it has realized the isolation between each device natively, even if a monoblock, electronics can not flow to another unit from a unit yet.Thereby realized reducing of area based on nanocrystalline nand memory, for next generation's storage provides possibility.
Summary of the invention
(1) technical problem that will solve
The object of the present invention is to provide a kind ofly based on nanocrystalline nand memory, reduce the area of traditional nand memory.
Another object of the present invention is to provide a kind of manufacture method based on nanocrystalline nand memory, to simplify manufacture craft.
(2) technical scheme
In order to solve the problems of the technologies described above, the invention provides a kind ofly based on nanocrystalline nand memory, comprise memory cell and transistor, described memory cell comprises: silicon substrate; At the source conduction region of the both sides of described silicon substrate with leak conduction region; The tunneling medium layer that carrier channels between source conduction region and leakage conduction region covers; Cover the nanocrystalline charge storage layer on the tunneling medium layer; Cover the control gate dielectric layer on the nanocrystalline charge storage layer; Cover the layer of gate electrode material on the control gate dielectric layer.
According to a kind of optimal way of the present invention, the material of described control gate dielectric layer is nitride, Al
2O
3, HfO
2, ZrO
2, a kind of or its combination among the HfSiO, thickness is 5nm～15nm.
According to a kind of optimal way of the present invention, the material of described tunneling medium layer is SiO
2, thickness is 4nm～7nm.
According to a kind of optimal way of the present invention, the material of described nanocrystalline charge storage layer is that metallic nano crystal, compound nano crystalline substance, semiconductor nano or Heterogeneous Composite are nanocrystalline, and nanocrystalline diameter is 1nm～10nm, and density is 1 * 10
11/ cm
-2～1 * 10
12/ cm
-2
According to a kind of optimal way of the present invention, the material of described metallic nano crystal is a kind of among metal W, Al, Ni, Co, Cr, Pt, Ru, Sn, Ti, Au and the Ag; The material of described compound nano crystalline substance is HfO
2, WN, CdSe, CoSi
2, NiSi, TaSi
2, WSi
2A kind of with among the HfSiO; The material of described semiconductor nano is a kind of among Si, Ge and the CdS; The nanocrystalline material of described Heterogeneous Composite is Si/Ge, TiSi
2A kind of among the/Si.
According to a kind of optimal way of the present invention, described layer of gate electrode material is polysilicon gate or metal gate, and described polysilicon gate is the N-type doped polycrystalline silicon, and described metal gate comprises TaN, IrO
2Or metal silicide; The thickness of the layer of gate electrode material of described polysilicon gate or metal gate is 100nm.
Also invention also provides a kind of method of making nand memory, comprises the steps: step 1: select silicon substrate; Step 2: described silicon substrate is mixed; Step 3: in the described silicon substrate tunneling medium layer of growing; Step 4: growing nano-crystal on described tunneling medium layer, as nanocrystalline charge storage layer; Step 5: at described nanocrystalline charge storage layer deposition control gate dielectric layer; Step 6: deposit layer of gate electrode material at the control gate dielectric layer; Step 7: carry out photoetching in nanocrystalline charge storage layer both sides to etch away layer of gate electrode material, control gate dielectric layer, nanocrystalline charge storage layer and tunneling medium layer, form the grid pile structure of memory cell; Step 8: the zone line at nanocrystalline charge storage layer carries out photoetching to etch away electrode material layer, control gate dielectric layer, forms and selects transistorized grid pile structure; Step 9: source conduction region and leakage conductance electricity area is carried out carrying out ion in photoetching, the silicon substrate to the source conduction region that forms after the photoetching and the graphics field of leaking conduction region inject, form the source conduction region and leak conduction region; Step 10: realize the interconnection of memory device, and the memory device of preparation is tested and encapsulated.
According to a kind of optimal way of the present invention, in step 2, adopt As that described silicon substrate is carried out trap doping, anti-penetration doping and threshold voltage adjustments respectively and mix.
According to a kind of optimal way of the present invention, in step 4, utilize grow on the tunneling medium layer surface film of layer of metal, compound or Si, Ge of the method for sputter or evaporation, short annealing again, thus make film form nano-crystalline granule at the tunneling medium layer surface crystallization.
According to a kind of optimal way of the present invention, described annealing time is 5 seconds to 90 seconds.
(3) beneficial effect
Compared with prior art, the beneficial effect of technical solution of the present invention generation is:
1, provided by the invention based on nanocrystalline nand memory, its area reduces several times;
2, provided by the invention nanocrystalline as the floating boom material owing to having adopted based on nanocrystalline nand memory, the performance of memory device is improved, and particularly memory properties such as memory window, program/erase (P/E) speed, data retention characteristics obtain comprehensive raising;
3, nanocrystalline nonvolatile memory manufacture method provided by the invention is very simple, and compatible fully with traditional cmos process.
Description of drawings
Fig. 1 is the structural representation based on nanocrystalline nand memory according to the embodiment of the invention;
Fig. 2 is the schematic diagram based on the nanocrystalline memory cell of nanocrystalline nand memory according to the embodiment of the invention;
Fig. 3 be according to the embodiment of the invention based on the nanocrystalline schematic diagram in the nanocrystalline memory cell;
Fig. 4 is the manufacture method flow chart based on the nanocrystalline nonvolatile memory of strained silicon according to the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
Fig. 1 is according to an embodiment of the invention based on nanocrystalline nand memory schematic diagram.As shown in Figure 1, should comprise nanocrystalline memory cell and select two parts of transistor based on nanocrystalline nand memory.
Fig. 2 is the schematic diagram based on the nanocrystalline memory cell of nanocrystalline nand memory according to the embodiment of the invention.As shown in Figure 2, nanocrystalline memory cell comprises silicon substrate 1, have source conduction region 6 in the both sides of silicon substrate 1 and leak conduction region 7, the tunneling medium layer 2 that covers on the carrier channels between source conduction region 6 and the leakage conduction region 7, cover the nanocrystalline charge storage layer 3 on the tunneling medium layer 2, cover the control gate dielectric layer 4 on the nanocrystalline charge storage layer 3, cover the layer of gate electrode material 5 on the control gate dielectric layer 4.
The material of the control gate dielectric layer 4 of described memory cell can be nitride, Al
2O
3, HfO
2, ZrO
2, a kind of or its combination among the HfSiO.The thickness of described control gate dielectric layer is 5nm～15nm.
The material of the tunneling medium layer 4 of described memory cell is SiO
2, thickness is 4nm～7nm.
It is nanocrystalline that the material of the nanocrystalline charge storage layer of described memory cell can be metallic nano crystal, compound nano crystalline substance, semiconductor nano or Heterogeneous Composite; Described nanocrystalline diameter is 1nm～10nm, and density is 1 * 10
11/ cm
-2～1 * 10
12/ cm
-2Fig. 3 be according to the embodiment of the invention based on the nanocrystalline schematic diagram in the nanocrystalline memory cell.As shown in Figure 3, the described nanocrystalline graininess that is, and all be relatively independent.
The material of described metallic nano crystal is any one among metal W, Al, Ni, Co, Cr, Pt, Ru, Sn, Ti, Au and the Ag; The material of described compound nano crystalline substance is HfO
2, WN, CdSe, CoSi
2, NiSi, TaSi
2, WSi
2With among the HfSiO any one; The material of described semiconductor nano is any one among Si, Ge and the CdS; The nanocrystalline material of described Heterogeneous Composite is Si/Ge, TiSi
2A kind of among the/Si.
The layer of gate electrode material of described memory cell is polysilicon gate or metal gate, and described polysilicon gate is the N-type doped polycrystalline silicon, and described metal gate comprises TaN, IrO
2Or metal silicide; The thickness of the layer of gate electrode material of described polysilicon gate or metal gate is 100nm.
Selecting transistor is the prior art transistor, comprise silicon substrate, be arranged in the source conduction region of silicon substrate both sides and leak conduction region, also comprise the dielectric layer that covers on the carrier channels between source conduction region and the leakage conduction region, cover the layer of gate electrode material on the dielectric layer.
Fig. 4 is the manufacture method flow chart based on the nanocrystalline nonvolatile memory of strained silicon according to the embodiment of the invention.As shown in Figure 4, this method may further comprise the steps:
Step 1: select silicon substrate 1;
Step 2: described silicon substrate 1 is mixed;
Step 3: in described silicon substrate growth tunneling medium layer 2;
Step 4: growing nano-crystal on described tunneling medium layer 2, as nanocrystalline charge storage layer 3;
Step 5: at described nanocrystalline charge storage layer 3 deposition control gate dielectric layers 4;
Step 6: in control gate dielectric layer 4 deposition layer of gate electrode material 5;
Step 7: carry out photoetching in nanocrystalline charge storage layer 3 both sides to etch away layer of gate electrode material 5, control gate dielectric layer 4, nanocrystalline charge storage layer 3 and tunneling medium layer 2, form the grid pile structure of memory cell;
Step 8: the zone line at nanocrystalline charge storage layer 3 carries out photoetching to etch away electrode material layer 5, control gate dielectric layer 4, forms and selects transistorized grid pile structure;
Step 9: to source conduction region 6 with leak conduction region 7 zones and carry out carrying out ion in photoetching, the silicon substrate 1 to the source conduction region 6 that forms after the photoetching and the graphics field of leaking conduction region 7 and inject, form source conduction region 6 and leak conduction region 7;
Step 10: realize the interconnection of memory device, and the memory device of preparation is tested and encapsulated.
Specifically describe the preferred version based on each step of the manufacture method of the nanocrystalline nonvolatile memory of strained silicon of this embodiment of the present invention below:
In above-mentioned steps one, can select the low-resistance silicon substrate 1 of P type, described P type low-resistance silicon substrate 1 can adopt (100) crystal orientation.
In above-mentioned steps two, described silicon substrate 1 is mixed, can adopt As that described silicon substrate 1 is carried out three times and mix, be respectively trap doping, anti-penetration doping and threshold voltage adjustments and mix.Described doping order is unrestricted.
In above-mentioned steps three, in described silicon substrate 1 growth tunneling medium layer 2, the material of described tunneling medium layer 2 can be SiO
2Purpose in described silicon substrate 1 growth one deck tunneling medium layer is the nanocrystalline charge storage layer 3 of isolating silicon substrate 1 and being used as storage medium.The method of described growth tunneling medium layer is thermal oxidation, ald ALD, chemical vapor deposition CVD, electron beam evaporation or magnetron sputtering.The thickness of described tunneling medium layer 2 can be 4nm～7nm, is preferably 4nm.
In above-mentioned steps four, growing nano-crystal on described tunneling medium layer 2 is as nanocrystalline charge storage layer 3.Be as charge storage media in the nanocrystalline purpose of described tunneling medium layer 2 growth one decks.The nanocrystalline method of described formation is: utilize the method for sputter or evaporation at metal, compound or Si, the Ge film of tunneling medium layer 2 surfaces growth one deck 1～10nm thickness, again according to the hot properties of different thin-film materials, corresponding different temperature short annealing 5 seconds to 90 seconds, thereby make thin-film material form nano-crystalline granule at tunneling medium layer 2 surface crystallizations.
In above-mentioned steps five, at described nanocrystalline charge storage layer 3 deposition control gate dielectric layers 4, the material of described control gate dielectric layer 4 can be nitride, Al
2O
3, HfO
2, ZrO
2, a kind of or its combination among the HfSiO, can be chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering in the method for nanocrystalline charge storage layer 3 deposition control gate dielectric layers 4; The thickness of the control gate dielectric layer 4 of described deposition can be 5nm～15nm, is preferably 10nm.
In above-mentioned steps six, remove and select the nanocrystalline of transistor area, in control gate dielectric layer 4 deposition layer of gate electrode material 5.Use the method for photoetching to protect nanocrystalline storage area, select the nanocrystalline of territory, area under control and remove with the method for dry etching, with methods such as chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputterings at control gate dielectric layer 4 film surfaces growth one deck polysilicon or metallic film as layer of gate electrode material 5; The thickness of described layer of gate electrode material 5 is at least 100nm.
In above-mentioned steps seven, carry out photoetching in nanocrystalline both sides to etch away unnecessary layer of gate electrode material 5, control gate dielectric layer 4, nanocrystalline charge storage layer 3 and tunneling medium layer 2, form the grid pile structure of memory cell.Specifically, in nanocrystalline charge storage layer two side areas, layer of gate electrode material 5 surface applied one deck negative resists and before baking, to coated negative resist expose, development and photographic fixing formation gate electrode figure.
Be mask etching layer of gate electrode material 5 with the gate electrode figure, control gate dielectric layer 4, nanocrystalline charge storage layer 3 and tunneling medium layer 2, etching stopping arrives silicon substrate 1 surface to form the grid pile structure of memory cell, concrete steps comprise: at layer of gate electrode material 5 surface coverage AZ5214 negativity optics resist or SAL601 negative electronic erosion-resisting agents, as mask, adopt high density inductively coupled plasma ICP lithographic method or reactive ion etching RIE method to etch away described layer of gate electrode material 5 successively it, described control gate dielectric layer 4, described nanocrystalline charge storage layer 3 and described tunneling medium layer 2.The method that then adopts wet method to remove photoresist is removed AZ5214 negativity optics resist or SAL601 negative electronic erosion-resisting agent, and it is exactly to adopt dense H that so-called wet method is removed photoresist
2SO
4+ H
2O
2Boil glue.
In above-mentioned steps eight, carry out photoetching to etch away layer of gate electrode material 5, control gate dielectric layer 4 at the zone line of nanocrystalline charge storage layer 3, form and select transistorized grid pile structure.Zone line at nanocrystalline charge storage layer 3, dry resist is handled in baking at layer of gate electrode material 5 surface applied one deck negative resists and before carrying out, to coated negative resist expose, development and photographic fixing select transistorized gate electrode figure to form.
Be mask etching layer of gate electrode material 5 with the gate electrode figure, control gate dielectric layer 4, etching stopping is to nanocrystalline charge storage layer 3, form and select transistorized grid pile structure, concrete steps comprise: cover AZ5214 negativity optics resist or SAL601 negative electronic erosion-resisting agent gate electrode figure on layer of gate electrode material 5 surfaces, with it as mask, adopt high density inductively coupled plasma ICP lithographic method or reactive ion etching RIE method etching layer of gate electrode material 5 successively, control gate dielectric layer 4, the method that then adopts wet method to remove photoresist is removed AZ5214 negativity optics resist or SAL601 negative electronic erosion-resisting agent, and it is exactly to adopt dense H that so-called wet method is removed photoresist
2SO
4+ H
2O
2Boil glue.
In above-mentioned steps nine, can coated AZ9912 positivity optics resist be carried out optical exposure, development and photographic fixing form the source conduction region, leak the conduction region figure at silicon substrate 1 coating one deck AZ9912 positivity optics resist; Inject P in the silicon substrate 1 to source conduction region 6, leakage conduction region 7 zones
31 +Ion, the injection energy is 50keV, implantation dosage is 1 * 10
18Cm
-2, again at dense H
2SO
4+ H
2O
2In boil glue and remove photoresist; Then under 1100 ℃ of temperature at N
2Short annealing is 10 seconds in the atmosphere, thus the source of formation conduction region 6 and leakage conduction region 7.
In above-mentioned steps ten, realize the interconnection of memory device, and interconnection is tested and encapsulated to the memory device of preparation.Described interconnection process comprise adopt sputter, chemical vapor deposition, photoetching, etching, etc. technology form dielectric layer, contact hole, through hole and passivation layer etc.
Test described in the above-mentioned steps ten, encapsulation specifically refer to encapsulation is tested and finished to the device finished product.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; be understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a nand memory comprises memory cell and transistor, and described memory cell comprises:
Silicon substrate (1);
At the source conduction region (6) of the both sides of described silicon substrate (1) with leak conduction region (7);
The tunneling medium layer (2) that carrier channels between source conduction region (6) and leakage conduction region (7) covers;
It is characterized in that described memory cell also comprises:
Cover the nanocrystalline charge storage layer (3) on the tunneling medium layer (2);
Cover the control gate dielectric layer (4) on the nanocrystalline charge storage layer (3);
Cover the layer of gate electrode material (5) on the control gate dielectric layer (4).
2. nand memory as claimed in claim 1 is characterized in that:
The material of described control gate dielectric layer (4) is nitride, Al
2O
3, HfO
2, ZrO
2, a kind of or its combination among the HfSiO, thickness is 5nm～15nm.
3. nand memory as claimed in claim 1, it is characterized in that: the material of described tunneling medium layer (4) is SiO
2, thickness is 4nm～7nm.
4. nand memory as claimed in claim 1, it is characterized in that: the material of described nanocrystalline charge storage layer (3) is that metallic nano crystal, compound nano crystalline substance, semiconductor nano or Heterogeneous Composite are nanocrystalline, nanocrystalline diameter is 1nm～10nm, and density is 1 * 10
11/ cm
-2～1 * 10
12/ cm
-2
5. nand memory as claimed in claim 4 is characterized in that: the material of described metallic nano crystal is a kind of among metal W, Al, Ni, Co, Cr, Pt, Ru, Sn, Ti, Au and the Ag; The material of described compound nano crystalline substance is HfO
2, WN, CdSe, CoSi
2, NiSi, TaSi
2, WSi
2A kind of with among the HfSiO; The material of described semiconductor nano is a kind of among Si, Ge and the CdS; The nanocrystalline material of described Heterogeneous Composite is Si/Ge, TiSi
2A kind of among the/Si.
6. nand memory as claimed in claim 1 is characterized in that: described layer of gate electrode material (5) is polysilicon gate or metal gate, and described polysilicon gate is the N-type doped polycrystalline silicon, and described metal gate comprises TaN, IrO
2Or metal silicide; The thickness of the layer of gate electrode material of described polysilicon gate or metal gate is 100nm.
7. a method of making nand memory comprises the steps:
Step 1: select silicon substrate (1);
Step 2: described silicon substrate (1) is mixed;
Step 3: in described silicon substrate (1) growth tunneling medium layer (2);
Step 4: go up growing nano-crystal in described tunneling medium layer (2), as nanocrystalline charge storage layer (3);
Step 5: at described nanocrystalline charge storage layer (3) deposition control gate dielectric layer (4);
Step 6: in control gate dielectric layer (4) deposition layer of gate electrode material (5);
Step 7: carry out photoetching in nanocrystalline charge storage layer (3) both sides to etch away layer of gate electrode material (5), control gate dielectric layer (4), nanocrystalline charge storage layer (3) and tunneling medium layer (2), form the grid pile structure of memory cell;
Step 8: the zone line at nanocrystalline charge storage layer (3) carries out photoetching to etch away electrode material layer (5), control gate dielectric layer (4), forms and selects transistorized grid pile structure;
Step 9: to source conduction region (6) with leak conduction region (7) zone and carry out carrying out ion in photoetching, the silicon substrate (1) to the source conduction region (6) that forms after the photoetching and the graphics field of leaking conduction region (7) and inject, form source conduction region (6) and leakage conduction region (7);
Step 10: realize the interconnection of memory device, and the memory device of preparation is tested and encapsulated.
8. method as claimed in claim 7 is characterized in that: in step 2, adopt As that described silicon substrate (1) is carried out trap doping, anti-penetration doping and threshold voltage adjustments respectively and mix.
9. method as claimed in claim 7 is characterized in that:
In step 4, utilize the method for sputter or evaporation at the film of tunneling medium layer (2) surface growth layer of metal, compound or Si, Ge, short annealing again makes film in tunneling medium layer (2) thereby surface crystallization forms nano-crystalline granule.
10. method as claimed in claim 9 is characterized in that:
Described annealing time is 5 seconds to 90 seconds.
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| CN106782639A (en) * | 2017-01-22 | 2017-05-31 | 南京大学 | A kind of CoPtxNano composite structure electromagnetic storage part and preparation method |
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|---|---|---|---|---|
| CN101494225A (en) * | 2009-02-23 | 2009-07-29 | 中国科学院微电子研究所 | Memory and manufacturing method thereof |
| CN102117812A (en) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | Nanocrystalline non-volatile memory based on strained silicon and manufacturing method thereof |
| KR20120008132A (en) * | 2010-07-16 | 2012-01-30 | 경희대학교 산학협력단 | A nonvolatile memory device using charge traps formed in hfo2 by nb ion doping and a manufacturing method thereof |
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| CN101494225A (en) * | 2009-02-23 | 2009-07-29 | 中国科学院微电子研究所 | Memory and manufacturing method thereof |
| CN102117812A (en) * | 2009-12-31 | 2011-07-06 | 中国科学院微电子研究所 | Nanocrystalline non-volatile memory based on strained silicon and manufacturing method thereof |
| KR20120008132A (en) * | 2010-07-16 | 2012-01-30 | 경희대학교 산학협력단 | A nonvolatile memory device using charge traps formed in hfo2 by nb ion doping and a manufacturing method thereof |
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| CN106782639A (en) * | 2017-01-22 | 2017-05-31 | 南京大学 | A kind of CoPtxNano composite structure electromagnetic storage part and preparation method |
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