CN103268879B - A kind of array base palte - Google Patents
A kind of array base palte Download PDFInfo
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- CN103268879B CN103268879B CN201210579283.0A CN201210579283A CN103268879B CN 103268879 B CN103268879 B CN 103268879B CN 201210579283 A CN201210579283 A CN 201210579283A CN 103268879 B CN103268879 B CN 103268879B
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Abstract
The invention discloses a kind of array base palte, comprise substrate and be positioned at the pel array on substrate, described pel array comprise many grid lines, with many grid lines many data wires that intersect that insulate, and be positioned at the pixel cell of grid line and data wire infall, pixel cell comprises TFT and pixel electrode. The capable pixel cell of P of pel array periphery is virtual pixel, and array base palte also comprises M first kind calibrating terminal and N Equations of The Second Kind calibrating terminal, and P, M, N are the integer that is more than or equal to 1; In virtual pixel, the grid of TFT is electrically connected with first kind calibrating terminal; In virtual pixel, the drain/source of TFT is electrically connected with Equations of The Second Kind calibrating terminal. The array base palte that the embodiment of the present invention provides, uses virtual pixel to replace short bar, has saved panel space. Cancelling the panel space that saves of short bar can be for design test circuit, thereby makes design test circuit on narrow frame be easy to realize.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of array base palte.
Background technology
Test for the viewing area to display unit, on the array base palte of display unit, be provided with shortRoad rod, sends to the grid line/data on array base palte by short bar by the test signal of test circuit outputLine, tests with the viewing area to pixel array region.
Along with the development of technology, display unit is just towards narrow frame future development. That is to say, at array baseOutside the pixel array region of plate, the region of leaving test circuit for is more and more narrow, causes test circuit to be difficult to designRealize.
Summary of the invention
The object of this invention is to provide a kind of array base palte, to solve the problems of the technologies described above.
The object of the invention is to be achieved through the following technical solutions:
A kind of array base palte, comprises substrate and is positioned at the pel array on described substrate, described pixel battle arrayRow comprise many grid lines, with described many grid lines many data wires that intersect that insulate, and be positioned at described grid lineWith the pixel cell of described data wire infall, described pixel cell comprises thin film transistor (TFT) TFT and pixelElectrode,
The capable pixel cell of P of described pel array periphery is virtual pixel;
Described array base palte also comprises M first kind calibrating terminal and N Equations of The Second Kind calibrating terminal, P,M, N are the integer that is more than or equal to 1;
In described virtual pixel, the grid of TFT is electrically connected with described first kind calibrating terminal; Described virtual representationIn element, the drain/source of TFT is electrically connected with described Equations of The Second Kind calibrating terminal.
The array base palte that the embodiment of the present invention provides, uses virtual pixel to replace short bar, has saved panelSpace. Cancelling the panel space that saves of short bar can be for design test circuit, thereby makes narrowOn frame, design test circuit is easy to realize.
Brief description of the drawings
The array base-plate structure schematic diagram that Fig. 1 provides for first embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 2 provides for second embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 3 provides for third embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 4 provides for four embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 5 provides for fifth embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 6 provides for sixth embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 7 provides for seventh embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 8 provides for eighth embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 9 provides for ninth embodiment of the invention;
The array base-plate structure schematic diagram that Figure 10 provides for tenth embodiment of the invention;
The array base-plate structure schematic diagram that Figure 11 provides for eleventh embodiment of the invention.
Detailed description of the invention
The embodiment of the present invention provides a kind of array base palte, comprises substrate, is positioned at the pixel battle array on this substrateRow, a M first kind calibrating terminal and N Equations of The Second Kind calibrating terminal. Wherein, pel array comprises manyBar grid line, with many grid lines many data wires that intersect that insulate, and be positioned at grid line and data wire infallPixel cell. The capable pixel cell of P of pel array periphery is virtual pixel, and P, M, N are and are greater than etc.In 1 integer.
Pixel cell comprises TFT(thin film transistor (TFT)) and pixel electrode. Wherein, TFT in pixel cellGrid and the electrical connection of corresponding grid line, the source/drain of TFT and corresponding data wire electricity in pixel cellConnect, in pixel cell, the drain/source of TFT is connected with the pixel electrode in same pixel cell. SeparatelyOutward, in virtual pixel, the grid of TFT is electrically connected with first kind calibrating terminal; The leakage of TFT in virtual pixelThe utmost point/source electrode is electrically connected with Equations of The Second Kind calibrating terminal.
In the embodiment of the present invention, pel array can be divided into viewing area and dummy pixel areas. Battle arrayRow substrate forms after display unit, and the pixel that participates in image demonstration is display pixel, does not participate in image aobviousThe pixel of showing is virtual pixel, and virtual pixel is covered by black matrix conventionally. In display unit, virtual representationElement is usually located at pel array periphery, and is covered by black matrix", and virtual pixel just can not participate in like thisShow. The pixel of so-called pel array periphery refers to the pixel that is positioned at pel array edge, Ke YishiA line or multirow pixel can be also row or multiple row pixel.
In the embodiment of the present invention, first kind calibrating terminal and Equations of The Second Kind calibrating terminal can but be not limited only to byLiner (PAD) is realized.
The array base palte that the embodiment of the present invention provides, uses virtual pixel to replace short bar, has saved panelSpace. Cancelling the panel space that saves of short bar can be for design test circuit, thereby makes narrowOn frame, design test circuit is easy to realize.
Below in conjunction with accompanying drawing, the array base palte that the invention process is provided is described in detail.
In each embodiment of the present invention, array base palte includes substrate, is positioned at the pixel battle array on this substrateRow, a M first kind calibrating terminal and N Equations of The Second Kind calibrating terminal. Wherein, pel array comprises manyBar grid line, with these many grid lines many data wires that intersect that insulate, and be positioned at grid line and data wire infallPixel cell. Pixel cell comprises TFT and pixel electrode. In pixel cell, the grid of TFT is with correspondingGrid line electrical connection, in pixel cell, the source/drain of TFT is electrically connected with corresponding data wire, pixel listIn unit, the drain/source of TFT is connected with the pixel electrode in same pixel cell. Each enforcement belowIn example, will repeat no more.
Figure 1 shows that the array base-plate structure schematic diagram that first embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 1.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101. Wherein, this rowIn virtual pixel 101, the grid of TFT shares corresponding grid line 102, and TFT in this row virtual pixel 101Grid be electrically connected with same first kind calibrating terminal 104. The source electrode of TFT in this row virtual pixel 101/ drain electrode is electrically connected with corresponding data wire 103. In this row virtual pixel 101, the drain/source of TFT is with samePixel electrode 1011 in one virtual pixel 101 is electrically connected. The drain electrode of TFT in this row virtual pixel 101/Source electrode is also electrically connected with same Equations of The Second Kind calibrating terminal 105.
Figure 2 shows that the array base-plate structure schematic diagram that second embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 2.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101. Wherein, this rowIn virtual pixel 101, the grid of TFT shares corresponding grid line 102, and TFT in this row virtual pixel 101Grid be electrically connected with same first kind calibrating terminal 104. The source electrode of TFT in this row virtual pixel 101/ drain electrode is electrically connected with corresponding data wire 103. In this row virtual pixel 101, the drain/source of TFT is with samePixel electrode 1011 in one virtual pixel 101 is electrically connected. This row virtual pixel is divided into and is positioned at pel arrayOne group of odd column and be positioned at a group of pel array even column. Wherein, be positioned at pel array odd columnIn one group of virtual pixel 101, the drain/source of TFT is electrically connected with an Equations of The Second Kind calibrating terminal 1051; PositionIn one group of virtual pixel 101 of pel array even column, the drain/source of TFT and another Equations of The Second Kind are surveyedExamination terminal 1052 is electrically connected.
Array base palte shown in Fig. 2, can realize odd column pixel cell and even column picture to pixel regionThe test respectively of element unit.
Figure 3 shows that the array base-plate structure schematic diagram that third embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 3.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101. Wherein, this rowIn virtual pixel 101, the grid of TFT shares corresponding grid line 102, and TFT in this row virtual pixel 101Grid be electrically connected with same first kind calibrating terminal 104. The source electrode of TFT in this row virtual pixel 101/ drain electrode is electrically connected with corresponding data wire 103. In this row virtual pixel 101, the drain/source of TFT is with samePixel electrode electrical connection in one virtual pixel 101. This row virtual pixel 101 is according to the color of pixel electrodeBe divided into three groups, one group of virtual pixel 101 comprises red pixel electrode 1011R, and one group of virtual pixel 101 wrapsDraw together green pixel electrode 1011G, one group of virtual pixel 101 comprises blue pixel electrode 1011B. Wherein,Comprise the drain/source of TFT in one group of virtual pixel 101 of red pixel electrode 1011R and one secondClass testing terminal 1053 is electrically connected; Comprise in one group of virtual pixel 101 of green pixel electrode 1011GThe drain/source of TFT is electrically connected with another Equations of The Second Kind calibrating terminal 1054; Comprise blue pixel electrodeThe drain/source of TFT and another Equations of The Second Kind calibrating terminal 1055 in one group of virtual pixel 101 of 1011BElectrical connection.
Array base palte shown in Fig. 3, can realize the pixel for different colours pixel electrode in pixel regionUnit is tested respectively.
It should be pointed out that except virtual pixel is divided into groups according to above-mentioned two embodiment, alsoCan virtual pixel be divided into N group according to actual testing requirement, the drain/source of TFT in every group of virtual pixelExtremely respectively be electrically connected with an Equations of The Second Kind calibrating terminal, N is more than or equal to 2 integer.
Figure 4 shows that the array base-plate structure schematic diagram that four embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 4.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101. Wherein, this rowVirtual pixel 101 is divided into one group that is positioned at a group of pel array odd column and is positioned at pel array even column.The grid that is arranged in one group of virtual pixel 101 TFT of pel array odd column shares corresponding grid line 102,And in this row virtual pixel 101, the grid of TFT is electrically connected with a first kind calibrating terminal 1041; Be positioned atIn one group of virtual pixel 101 of pel array even column, the grid of TFT shares corresponding grid line 102, and emptyThe grid of intending TFT in pixel 101 is electrically connected with another first kind calibrating terminal 1042. This row virtual representationIn element 101, the source/drain of TFT is electrically connected with corresponding data wire 103. In this row virtual pixel 101The drain/source of TFT is electrically connected with the pixel electrode 1011 in same virtual pixel 101. In addition, this rowIn virtual pixel 101, the drain/source of TFT is electrically connected with an Equations of The Second Kind calibrating terminal 105.
It should be pointed out that shown in Fig. 4 to the packet mode of virtual pixel 101 be only a kind of for example,In application, can also divide into groups to virtual pixel 101 according to testing requirement.
In addition, not only virtual pixel 101 can be divided into two groups, can also be according to testing requirement by virtual representationElement 101 is divided into M group, in every group of virtual pixel the grid of TFT respectively with a first kind calibrating terminal electricityConnect, M is more than or equal to 2 integer.
Figure 5 shows that the array base-plate structure schematic diagram that fifth embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 5.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101. Wherein, this rowVirtual pixel 101 is divided into one group that is positioned at a group of pel array odd column and is positioned at pel array even column.The grid that is arranged in one group of virtual pixel 101 TFT of pel array odd column shares corresponding grid line 102,And in virtual pixel 101, the grid of TFT is electrically connected with a first kind calibrating terminal 1041; Be positioned at pixelIn one group of virtual pixel 101 of Array Pairs ordered series of numbers, the grid of TFT shares corresponding grid line 102, and virtual representationIn element 101, the grid of TFT is electrically connected with another first kind calibrating terminal 1042. Be positioned at pel array strangeIn one group of virtual pixel 101 of ordered series of numbers, the drain/source of TFT and an Equations of The Second Kind calibrating terminal 1051 are electrically connectedConnect; Be arranged in pel array even column one group of virtual pixel 101 TFT drain/source also with anotherEquations of The Second Kind calibrating terminal 1052 is electrically connected. In this row virtual pixel 101, the source/drain of TFT is with correspondingData wire 103 is electrically connected. The drain/source of TFT and same virtual pixel 101 in this row virtual pixel 101In pixel electrode 1011 be electrically connected.
It should be pointed out that shown in Fig. 5 to the packet mode of virtual pixel 101 be only a kind of for example,In application, can also divide into groups to virtual pixel 101 according to testing requirement.
In addition, not only virtual pixel 101 can be divided into two groups, can also be according to testing requirement by virtual representationElement 101 is divided into M group, in every group of virtual pixel the grid of TFT respectively with a first kind calibrating terminal electricityConnect, M is more than or equal to 2 integer; In every group of virtual pixel, the drain/source of TFT is respectively with oneIndividual Equations of The Second Kind calibrating terminal electrical connection.
Figure 6 shows that the array base-plate structure schematic diagram that sixth embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 6.
Two row pixel cells of the pel array outermost of array base palte are virtual pixel 101. Wherein, this twoIn row virtual pixel 101, the grid of TFT shares corresponding grid line 102, and TFT in virtual pixel 101Grid be electrically connected with same first kind calibrating terminal 104. The source of TFT in this two row virtual pixel 101The utmost point/drain electrode is electrically connected with corresponding data wire 103. The drain/source of TFT in this two row virtual pixel 101Be electrically connected with the pixel electrode 1011 in same virtual pixel 101. Wherein a line virtual pixel 101 metasThe drain/source of TFT and an Equations of The Second Kind test in one group of virtual pixel 101 of pel array odd columnTerminal 1051 is electrically connected; In another row virtual pixel 101, be positioned at one group of virtual representation of pel array even columnIn element 101, the drain/source of TFT is electrically connected with another Equations of The Second Kind calibrating terminal 1052.
Array base palte shown in Fig. 6, can realize odd column pixel cell and even column picture to pixel regionThe test respectively of element unit.
It should be pointed out that the array base palte shown in Fig. 6 is just for example a kind of and non-limiting. Not only can be byVirtual pixel is divided according to odd column and even column, in application, and can also be according to testing requirement by virtualPixel is divided into two groups, connects respectively an Equations of The Second Kind calibrating terminal and tests.
In addition, can also be by virtual pixel being divided into three groups even more groups, every group of virtual pixel dividesDo not connect an Equations of The Second Kind calibrating terminal and realize grouping test. For example, wherein a line virtual pixel comprisesIn one group of virtual pixel of red pixel electrode, the drain/source of TFT and an Equations of The Second Kind calibrating terminal are electrically connectedConnect, the drain/source that this row virtual pixel comprises TFT in one group of virtual pixel of green pixel electrode withAnother Equations of The Second Kind calibrating terminal electrical connection, another row virtual pixel comprises a group of blue pixel electrodeIn virtual pixel, the drain/source of TFT is electrically connected with another Equations of The Second Kind calibrating terminal. Other structures connectRelation can be with reference to shown in Fig. 6.
Figure 7 shows that the array base-plate structure schematic diagram that seventh embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 7.
Two row pixel cells of the pel array outermost of array base palte are virtual pixel 101. Wherein, eachIn row virtual pixel 101, the grid of TFT shares corresponding grid line 102, and TFT in virtual pixel 101Grid be electrically connected with a first kind calibrating terminal (1041,1042) respectively. This two row virtual pixel 101The source/drain of middle TFT is electrically connected with corresponding data wire 103. TFT in this two row virtual pixel 101Drain/source be electrically connected with the pixel electrode 1011 in same virtual pixel 101. Wherein a line virtual representationElement is arranged in the drain/source of one group of virtual pixel 101 TFT of pel array odd column and one in 101Equations of The Second Kind calibrating terminal 1051 is electrically connected; In another row virtual pixel 101, be positioned at pel array even columnIn one group of virtual pixel 101, the drain/source of TFT is electrically connected with another Equations of The Second Kind calibrating terminal 1052.
Array base palte shown in Fig. 7, can realize odd column pixel cell and even column picture to pixel regionThe test respectively of element unit.
It should be pointed out that the array base palte shown in Fig. 7 is just for example a kind of and non-limiting. Not only can be byVirtual pixel is divided according to odd column and even column, in application, and can also be according to testing requirement by virtualPixel is divided into two groups, connects respectively an Equations of The Second Kind calibrating terminal and tests.
In addition, can also be by virtual pixel being divided into three groups even more groups, every group of virtual pixel dividesDo not connect an Equations of The Second Kind calibrating terminal and realize grouping test. For example, wherein a line virtual pixel comprisesIn one group of virtual pixel of red pixel electrode, the drain/source of TFT and an Equations of The Second Kind calibrating terminal are electrically connectedConnect, the drain/source that this row virtual pixel comprises TFT in one group of virtual pixel of green pixel electrode withAnother Equations of The Second Kind calibrating terminal electrical connection, another row virtual pixel comprises a group of blue pixel electrodeIn virtual pixel, the drain/source of TFT is electrically connected with another Equations of The Second Kind calibrating terminal. Other structures connectRelation can be with reference to shown in Fig. 7.
Figure 8 shows that the array base-plate structure schematic diagram that eighth embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 8.
Two row pixel cells of the pel array outermost of array base palte are virtual pixel 101. Wherein, a lineIn virtual pixel 101, be arranged in pel array odd column one group of virtual pixel 101 TFT grid share rightThe grid line 102 of answering, and grid and a first kind calibrating terminal 1041 of TFT in this row virtual pixel 101Electrical connection; In another row virtual pixel 101, be arranged in one group of virtual pixel 101 of pel array even columnThe grid of TFT shares corresponding grid line 102, and the grid of TFT and another in this row virtual pixel 101First kind calibrating terminal 1042 is electrically connected. In this two row virtual pixel 101, the source/drain of TFT is with correspondingData wire 103 be electrically connected. Drain/source and the same virtual representation of TFT in this two row virtual pixel 101Pixel electrode 1011 in element 101 is electrically connected. In this two row virtual pixel 101, the drain/source of TFT alsoBe electrically connected with same Equations of The Second Kind calibrating terminal 105.
Array base palte shown in Fig. 8, can realize odd column pixel cell and even column picture to pixel regionThe test respectively of element unit.
It should be pointed out that the array base palte shown in Fig. 8 is just for example a kind of and non-limiting, also for example, theThe all grids of a line virtual pixel are connected to a first kind calibrating terminal, and the second row virtual pixel is allGrid be connected to another first kind calibrating terminal. And, not only can be by virtual pixel according to odd columnDivide with even column, in application, can also virtual pixel be divided into two groups according to testing requirement, everyOne group of virtual pixel in row connects respectively a first kind calibrating terminal to be tested.
In addition, can also be by virtual pixel being divided into three groups even more groups, every group of virtual pixel dividesDo not connect a first kind calibrating terminal and realize grouping test. For example, a line virtual pixel comprises rednessIn one group of virtual pixel of pixel electrode, the grid of TFT is electrically connected with a first kind calibrating terminal, this rowVirtual pixel comprises grid and another first kind of TFT in one group of virtual pixel of green pixel electrodeCalibrating terminal electrical connection, another row virtual pixel comprises in one group of virtual pixel of blue pixel electrodeThe grid of TFT is electrically connected with another first kind calibrating terminal. Other structure annexations can be with reference to Fig. 8 instituteShow.
Figure 9 shows that the array base-plate structure schematic diagram that ninth embodiment of the invention provides. Array base palteSubstrate is not shown in Fig. 9.
Three row pixel cells of the pel array outermost of array base palte are virtual pixel 101. Wherein, this threeIn row virtual pixel 101, the grid of TFT shares corresponding grid line 102, and in this three row virtual pixel 101The grid of TFT is electrically connected with same first kind calibrating terminal 104. TFT in this three row virtual pixel 101Source/drain be electrically connected with corresponding data wire 103. The drain electrode of TFT in this three row virtual pixel 101/Source electrode is electrically connected with the pixel electrode in same virtual pixel 101. Wherein bag in the first row virtual pixel 101Draw together drain/source and an Equations of The Second Kind of TFT in one group of virtual pixel 101 of red pixel electrode 1011RCalibrating terminal 1053 is electrically connected; The second row virtual pixel 101 comprises one of green pixel electrode 1011GIn group virtual pixel 101, the drain/source of TFT is electrically connected with an Equations of The Second Kind calibrating terminal 1054; The 3rdRow virtual pixel 101 comprises the leakage of TFT in one group of virtual pixel 101 of blue pixel electrode 1011BThe utmost point/source electrode is electrically connected with an Equations of The Second Kind calibrating terminal 1055.
Array base palte shown in Fig. 9, can realize the pixel for different colours pixel electrode in pixel regionUnit is tested respectively.
It should be pointed out that the array base-plate structure shown in Fig. 9 is only for example a kind of and non-limiting. For example,Can also survey the pixel cell that comprises green or blue pixel electrode by the first row virtual pixelExamination, surveys the pixel cell that comprises redness or blue pixel electrode by the second row virtual pixelExamination, surveys the pixel cell that comprises redness or green pixel electrode by the third line virtual pixelExamination.
In addition, not only virtual pixel can be divided according to the color of pixel electrode, can also basisActual testing requirement is divided into three groups to virtual pixel and tests.
Figure 10 shows that the array base-plate structure schematic diagram that tenth embodiment of the invention provides. Array base palteSubstrate not shown in Figure 10.
Three row pixel cells of the pel array outermost of array base palte are virtual pixel 101. Wherein, eachIn row virtual pixel 101, the grid of TFT shares corresponding grid line 102, and in every a line virtual pixel 101The grid of TFT is electrically connected with a first kind calibrating terminal (1043,1044,1045) respectively. This three rowIn virtual pixel 101, the source/drain of TFT is electrically connected with corresponding data wire 103. This three row virtual representationIn element 101, the drain/source of TFT is electrically connected with the pixel electrode in same virtual pixel 101. WhereinA line virtual pixel 101 comprises TFT's in one group of virtual pixel 101 of red pixel electrode 1011RDrain/source is electrically connected with an Equations of The Second Kind calibrating terminal 1053; The second row virtual pixel 101 comprises greenThe drain/source of TFT and an Equations of The Second Kind test in one group of virtual pixel 101 of color pixel electrode 1011GTerminal 1054 is electrically connected; The third line virtual pixel 101 comprises one group of void of blue pixel electrode 1011BThe drain/source of intending TFT in pixel 101 is electrically connected with an Equations of The Second Kind calibrating terminal 1055.
Array base palte shown in Figure 10, can realize the picture for different colours pixel electrode in pixel regionElement unit is tested respectively.
It should be pointed out that the array base-plate structure shown in Figure 10 is only for example a kind of and non-limiting. ExampleAs, can also enter the pixel cell that comprises green or blue pixel electrode by the first row virtual pixelRow test, carries out the pixel cell that comprises redness or blue pixel electrode by the second row virtual pixelTest, surveys the pixel cell that comprises redness or green pixel electrode by the third line virtual pixelExamination, also for example, all grids of the first row virtual pixel are connected to a first kind calibrating terminal, secondThe all grids of row virtual pixel are connected to an another first kind calibrating terminal, and the third line virtual pixel is allGrid is connected to another first kind calibrating terminal.
In addition, not only virtual pixel can be divided according to the color of pixel electrode, can also basisActual testing requirement is divided into three groups to virtual pixel and tests.
Figure 11 shows that the array base-plate structure schematic diagram that eleventh embodiment of the invention provides. Array baseThe substrate of plate is not shown in Figure 11.
Three row pixel cells of the pel array outermost of array base palte are virtual pixel 101. Wherein, firstRow virtual pixel 101 comprises the grid of TFT in one group of virtual pixel 101 of red pixel electrode 1011RExtremely share corresponding grid line 102, and in this row virtual pixel 101, grid and a first kind of TFT testedTerminal 1043 is electrically connected; The second row virtual pixel 101 comprises that a group of green pixel electrode 1011G is virtualIn pixel 101, the grid of TFT shares corresponding grid line 102, and the grid of TFT in this row virtual pixel 101The utmost point is electrically connected with a first kind calibrating terminal 1044; The third line virtual pixel 101 comprises blue pixel electricityIn one group of virtual pixel 101 of utmost point 1011B, the grid of TFT shares corresponding grid line 102, and this row is virtualIn pixel 101, the grid of TFT is electrically connected with a first kind calibrating terminal 1045. This three row virtual pixelIn 101, the source/drain of TFT is electrically connected with corresponding data wire 103. In this three row virtual pixel 101The drain/source of TFT is electrically connected with the pixel electrode 1011 in same virtual pixel 101. This three row is virtualIn pixel 101, the drain/source of TFT is electrically connected with same Equations of The Second Kind calibrating terminal 105.
Array base palte shown in Figure 11, can realize the picture for different colours pixel electrode in pixel regionElement unit is tested respectively. Therefore, in Figure 11, only illustrate that the first row virtual pixel 101 comprises red pixelAnnexation between one group of virtual pixel 101 and the Equations of The Second Kind calibrating terminal 105 of electrode 1011R, secondRow virtual pixel 101 comprises the one group of virtual pixel 101 and Equations of The Second Kind test of green pixel electrode 1011GAnnexation between terminal 105, and the third line virtual pixel 101 comprises blue pixel electrode 1011BOne group of virtual pixel 101 and Equations of The Second Kind calibrating terminal 105 between annexation. Not shown in Figure 11Annexation between other virtual pixels 101 and Equations of The Second Kind calibrating terminal 105.
It should be pointed out that the array base-plate structure shown in Figure 11 is only for example a kind of and non-limiting. ExampleAs, can also enter the pixel cell that comprises green or blue pixel electrode by the first row virtual pixelRow test, carries out the pixel cell that comprises redness or blue pixel electrode by the second row virtual pixelTest, surveys the pixel cell that comprises redness or green pixel electrode by the third line virtual pixelExamination. Again for example, can also comprise three Equations of The Second Kind calibrating terminals, the above-mentioned one group of virtual representation in every a lineIn element, the drain/source of TFT is electrically connected with an Equations of The Second Kind calibrating terminal respectively.
In addition, not only virtual pixel can be divided according to the color of pixel electrode, can also basisActual testing requirement is divided into three groups to virtual pixel and tests.
In Fig. 1 ~ Figure 11 corresponding to the embodiment of the present invention, first kind calibrating terminal all connects with corresponding grid lineConnect, Equations of The Second Kind calibrating terminal is all connected with corresponding pixel electrode. It should be pointed out that due to TFT'sGrid is electrically connected with grid line, and therefore, first kind calibrating terminal is connected with grid line, is equivalent to first kind testTerminal is connected with the grid of TFT. Because the drain/source of TFT is connected with pixel electrode, therefore, secondClass testing terminal is connected with pixel electrode, and the drain/source that is equivalent to Equations of The Second Kind calibrating terminal and TFT connectsConnect.
In array base palte described in each embodiment of the invention described above, the grid of TFT and in virtual pixelOne class testing terminal connects by the first wire, and this first wire and grid line are positioned at same layer; Certainly this firstWire also can be made up of multistage, between each section, connect by via hole, wherein each section all can with grid line, sourceAny in the utmost point and drain electrode, pixel electrode is positioned at same layer, adopts identical material. In virtual pixelThe drain/source of TFT is connected by the second wire with Equations of The Second Kind calibrating terminal, this second wire and grid line positionIn same layer, or with data line bit in same layer, or be positioned at same layer with pixel electrode; Same,This first wire also can be made up of multistage, between each section, connect by via hole, wherein each section all can with gridAny in line, source electrode and drain electrode, pixel electrode is positioned at same layer, adopts identical material.
Obviously, those skilled in the art can carry out various changes and modification and not depart from this present inventionBright spirit and scope. Like this, if of the present invention these amendment and modification belong to the claims in the present invention andWithin the scope of its equivalent technologies, the present invention be also intended to comprise these change and modification interior.
Claims (20)
1. an array base palte, comprises substrate and is positioned at the pel array on described substrate, described pixelArray comprise many grid lines, with described many grid lines many data wires that intersect that insulate, and be positioned at described gridThe pixel cell of line and described data wire infall, described pixel cell comprises thin film transistor (TFT) TFT and pictureElement electrode, is characterized in that,
The capable pixel cell of P of described pel array periphery is virtual pixel;
Described array base palte also comprises M first kind calibrating terminal and N Equations of The Second Kind calibrating terminal, P,M, N are the integer that is more than or equal to 1;
In described virtual pixel, the grid of TFT is electrically connected with described first kind calibrating terminal; Described virtual representationIn element, the drain/source of TFT is electrically connected with described Equations of The Second Kind calibrating terminal, concrete, described virtual pixelThe grid of middle TFT is connected by the first wire with described first kind calibrating terminal, described the first wire and instituteState grid line and be positioned at same layer; The drain/source of TFT and described Equations of The Second Kind calibrating terminal in described virtual pixelConnect by the second wire, described the second wire and described grid line or data wire or pixel electrode are positioned at sameLayer.
2. array base palte according to claim 1, is characterized in that, P=1, described pel arrayPeripheral one-row pixels unit is virtual pixel.
3. array base palte according to claim 2, is characterized in that, M=1, described virtual pixelThe grid of middle TFT is all electrically connected to same described first kind calibrating terminal.
4. array base palte according to claim 3, is characterized in that, N=1, described virtual pixelThe drain/source of middle TFT is all electrically connected with described same Equations of The Second Kind calibrating terminal.
5. array base palte according to claim 3, is characterized in that, N >=2, described virtual pixelBe divided into N group, corresponding being electrically connected of drain/source of each Equations of The Second Kind calibrating terminal and TFT in one group of virtual pixelConnect.
6. array base palte according to claim 5, is characterized in that, N=2, described virtual pixelBe divided into one group that is positioned at a group of described pel array odd column and is positioned at described pel array even column, positionBe arranged in the drain/source of the odd column of one group of virtual pixel TFT of described pel array in described virtual pixelThe utmost point is electrically connected with one of them of described Equations of The Second Kind calibrating terminal, is positioned at one of described pel array even columnIn group virtual pixel, TFT drain/source is electrically connected with another in described Equations of The Second Kind calibrating terminal.
7. array base palte according to claim 5, is characterized in that, N=3, described virtual pixelBe divided into and comprise one group of red pixel electrode, comprise a group of green pixel electrode and comprise blue pixelOne group of electrode, comprises the drain/source of TFT in one group of virtual pixel of red pixel electrode and oneTwo class testing terminals electrical connections, comprise the drain/source of TFT in one group of virtual pixel of green pixel electrodeBe electrically connected with another Equations of The Second Kind calibrating terminal, comprise TFT in one group of virtual pixel of blue pixel electrodeDrain/source be electrically connected with another Equations of The Second Kind calibrating terminal.
8. array base palte according to claim 2, is characterized in that, M >=2, described virtual pixelBe divided into M group, corresponding being electrically connected of grid of first kind calibrating terminal and TFT in one group of virtual pixel described in eachConnect.
9. array base palte according to claim 8, is characterized in that, N=1, described virtual pixelThe drain/source of middle TFT is all electrically connected with same Equations of The Second Kind calibrating terminal.
10. array base palte according to claim 8, is characterized in that, N >=2, every group of virtual representationIn element, the drain/source of TFT is electrically connected with an Equations of The Second Kind calibrating terminal respectively.
11. array base paltes according to claim 1, is characterized in that, P=2, described pel arrayTwo peripheral row pixel cells are virtual pixel.
12. array base paltes according to claim 11, is characterized in that, M=1, described virtual representationIn element, the grid of TFT is all electrically connected with same first kind calibrating terminal; Or M=2, described in every a lineThe grid of TFT electrical connection corresponding to first kind calibrating terminal described in respectively in virtual pixel.
13. array base paltes according to claim 12, is characterized in that, N=2, described in the first rowIn virtual pixel, be arranged in the drain/source and of one group of virtual pixel TFT of described pel array odd columnIndividual Equations of The Second Kind calibrating terminal electrical connection; Described in the second row, in virtual pixel, be positioned at described pel array even columnOne group of virtual pixel in the drain/source of TFT be electrically connected with another Equations of The Second Kind calibrating terminal.
14. array base paltes according to claim 11, is characterized in that, M=2 is empty described in a lineIntend being arranged in pixel one group of virtual pixel TFT grid and a first kind of described pel array odd columnCalibrating terminal electrical connection; In another row virtual pixel, be positioned at one group of virtual representation of described pel array even columnIn element, the grid of TFT is electrically connected with another first kind calibrating terminal.
15. array base paltes according to claim 14, is characterized in that, N=1, described virtual representationIn element, the drain/source of TFT is all electrically connected with same described Equations of The Second Kind calibrating terminal.
16. array base paltes according to claim 1, is characterized in that, P=3, described pel arrayThree peripheral row pixel cells are virtual pixel.
17. array base paltes according to claim 16, is characterized in that, M=1, described virtual representationIn element, the grid of TFT is all electrically connected with same first kind calibrating terminal; Or M=3, described in every a lineIn virtual pixel, the grid of TFT is electrically connected with a first kind calibrating terminal respectively.
18. array base paltes according to claim 17, is characterized in that, N=3, described in the first rowVirtual pixel comprises the drain/source of TFT in one group of virtual pixel of red pixel electrode and one secondThe electrical connection of class testing terminal; Described in the second row, virtual pixel comprises one group of virtual representation of green pixel electrodeIn element, the drain/source of TFT is electrically connected with another Equations of The Second Kind calibrating terminal; Virtual pixel described in the third lineComprise drain/source and the test of another Equations of The Second Kind of TFT in one group of virtual pixel of blue pixel electrodeTerminal electrical connection.
19. array base paltes according to claim 16, is characterized in that, M=3, described in the first rowVirtual pixel comprises that the grid of TFT in one group of virtual pixel of red pixel electrode and a first kind surveyThe electrical connection of examination terminal; Described in the second row, virtual pixel comprises in one group of virtual pixel of green pixel electrodeThe grid of TFT is electrically connected with another first kind calibrating terminal; Described in the third line, virtual pixel comprises indigo plantIn one group of virtual pixel of color pixel electrode, the grid of TFT is electrically connected with another first kind calibrating terminal.
20. array base paltes according to claim 19, is characterized in that, N=1, described virtual representationIn element, the drain/source of TFT is all electrically connected with same Equations of The Second Kind calibrating terminal.
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| CN104898342A (en) * | 2015-06-16 | 2015-09-09 | 京东方科技集团股份有限公司 | Array substrate mother plate and manufacture method thereof |
| CN110928018B (en) * | 2016-12-20 | 2021-05-11 | 武汉华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN106601162B (en) * | 2016-12-23 | 2019-09-24 | 上海天马有机发光显示技术有限公司 | Display panel and display device comprising it |
| JP7098346B2 (en) * | 2018-02-13 | 2022-07-11 | ソニーセミコンダクタソリューションズ株式会社 | Imaging device and imaging system |
| CN110119225B (en) * | 2019-05-20 | 2022-05-10 | 业成科技（成都）有限公司 | Touch panel |
| CN110190106B (en) | 2019-06-13 | 2022-01-28 | 京东方科技集团股份有限公司 | Display panel, preparation method and detection method thereof, and display device |
| CN110649045B (en) * | 2019-10-31 | 2022-08-26 | 京东方科技集团股份有限公司 | Organic light emitting display panel and display device |
| CN112349230B (en) | 2020-12-04 | 2022-06-21 | 厦门天马微电子有限公司 | Display panel, detection method thereof and display device |
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