CN103268879A - Array substrate - Google Patents
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- CN103268879A CN103268879A CN2012105792830A CN201210579283A CN103268879A CN 103268879 A CN103268879 A CN 103268879A CN 2012105792830 A CN2012105792830 A CN 2012105792830A CN 201210579283 A CN201210579283 A CN 201210579283A CN 103268879 A CN103268879 A CN 103268879A
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Abstract
The invention discloses an array substrate. The array substrate comprises a substrate and a pixel array positioned on the substrate; the pixel array comprises a plurality of grid lines, a plurality of data lines which are crossed in insulating form with the plurality of grid lines, and pixel units arranged at the crossing parts of the grid lines and the data lines; each pixel unit comprises a TFT (thin film transistor) and a pixel electrode; the pixel units of the P row of the periphery of the pixel array are virtual pixels; the array substrate further comprises M first testing terminals and N second testing terminals; P, M and N are all integers equal to or greater than 1; the grids of the TFTs in the virtual pixels are electrically connected with the first testing terminals; and the drain electrode /source electrode of the TFTs in the virtual pixels are electrically connected with the second testing terminals. In the array substrate disclosed by the embodiment of the invention, by replacing a shorting bar by the virtual pixels, the space of a panel is saved; the space of the panel saved by eliminating the shorting bar can be used for placing a testing circuit, and therefore the testing circuit is easy to be designed on a narrow frame.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of array base palte.
Background technology
In order to test the viewing area to display unit, the array base palte of display unit is provided with short bar, by short bar the test signal of test circuit output is sent to grid line/data wire on the array base palte, test with the viewing area to pixel array region.
Along with the development of technology, display unit just develops towards narrow frame direction.That is to say, outside the pixel array region of array base palte, leave the regional more and more narrow of test circuit for, cause test circuit to be difficult to design and realize.
Summary of the invention
The purpose of this invention is to provide a kind of array base palte, to solve the problems of the technologies described above.
The objective of the invention is to be achieved through the following technical solutions:
A kind of array base palte, comprise substrate and be positioned at pel array on the described substrate, many the data wires that described pel array comprises many grid lines, intersects with described many grid lines insulation, with the pixel cell that is positioned at described grid line and described data wire infall, described pixel cell comprises thin-film transistor TFT and pixel electrode
The capable pixel cell of P of described pel array periphery is virtual pixel;
Described array base palte also comprises M first kind calibrating terminal and N the second class testing terminal, and P, M, N are the integer more than or equal to 1;
The grid of TFT is electrically connected with described first kind calibrating terminal in the described virtual pixel; The drain/source of TFT is electrically connected with the described second class testing terminal in the described virtual pixel.
The array base palte that the embodiment of the invention provides uses virtual pixel to replace short bar, has saved panel space.The panel space that the cancellation short bar saves can be used for the design test circuit, thereby makes that the design test circuit is easy to realize on narrow frame.
Description of drawings
The array base-plate structure schematic diagram that Fig. 1 provides for first embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 2 provides for second embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 3 provides for third embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 4 provides for four embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 5 provides for fifth embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 6 provides for sixth embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 7 provides for seventh embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 8 provides for eighth embodiment of the invention;
The array base-plate structure schematic diagram that Fig. 9 provides for ninth embodiment of the invention;
The array base-plate structure schematic diagram that Figure 10 provides for tenth embodiment of the invention;
The array base-plate structure schematic diagram that Figure 11 provides for eleventh embodiment of the invention.
Embodiment
The embodiment of the invention provides a kind of array base palte, comprises substrate, is positioned at pel array, a M first kind calibrating terminal and N the second class testing terminal on this substrate.Wherein, pel array comprise many grid lines, many data wires intersecting with the insulation of many grid lines and be positioned at grid line and the pixel cell of data wire infall.The capable pixel cell of the P of pel array periphery is virtual pixel, and P, M, N are the integer more than or equal to 1.
Pixel cell comprises the TFT(thin-film transistor) and pixel electrode.Wherein, the grid of TFT is electrically connected with corresponding grid line in the pixel cell, and the source/drain of TFT is electrically connected with corresponding data line in the pixel cell, and the drain/source of TFT is connected with pixel electrode in the same pixel cell in the pixel cell.In addition, the grid of TFT is electrically connected with first kind calibrating terminal in the virtual pixel; The drain/source of TFT is electrically connected with the second class testing terminal in the virtual pixel.
In the embodiment of the invention, pel array can be divided into viewing area and dummy pixel areas.After array base palte formed display unit, the pixel that participates in the image demonstration was display pixel, and the pixel that does not participate in the image demonstration is virtual pixel, and common virtual pixel is deceived matrix and covered.In display unit, virtual pixel is usually located at the pel array periphery, and is covered by black matrix", and virtual pixel just can not participate in showing like this.The pixel of so-called pel array periphery namely refers to be positioned at the pixel at pel array edge, can be delegation or multirow pixel, also can be row or a multiple row pixel.
In the embodiment of the invention, first kind calibrating terminal and the second class testing terminal can but be not limited only to be realized by liner (PAD).
The array base palte that the embodiment of the invention provides uses virtual pixel to replace short bar, has saved panel space.The panel space that the cancellation short bar saves can be used for the design test circuit, thereby makes that the design test circuit is easy to realize on narrow frame.
Below in conjunction with accompanying drawing, the array base palte that the invention process is provided is described in detail.
Among each embodiment of the present invention, array base palte includes substrate, is positioned at pel array, a M first kind calibrating terminal and N the second class testing terminal on this substrate.Wherein, pel array comprise many grid lines, many data wires intersecting with this many grid lines insulation and be positioned at grid line and the pixel cell of data wire infall.Pixel cell comprises TFT and pixel electrode.The grid of TFT is electrically connected with corresponding grid line in the pixel cell, and the source/drain of TFT is electrically connected with corresponding data line in the pixel cell, and the drain/source of TFT is connected with pixel electrode in the same pixel cell in the pixel cell.To repeat no more among each embodiment below.
Figure 1 shows that the array base-plate structure schematic diagram that first embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 1.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in this row virtual pixel 101, and the grid of TFT is electrically connected with same first kind calibrating terminal 104 in this row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this row virtual pixel 101.The drain/source of TFT also is electrically connected with the same second class testing terminal 105 in this row virtual pixel 101.
Figure 2 shows that the array base-plate structure schematic diagram that second embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 2.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in this row virtual pixel 101, and the grid of TFT is electrically connected with same first kind calibrating terminal 104 in this row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this row virtual pixel 101.This row virtual pixel is divided into a group of being positioned at the pel array odd column and is positioned at a group of pel array even column.Wherein, the drain/source that is arranged in one group of virtual pixel 101 TFT of pel array odd column is electrically connected with second a class testing terminal 1051; The drain/source that is arranged in one group of virtual pixel 101 TFT of pel array even column is electrically connected with another second class testing terminal 1052.
Array base palte shown in Figure 2 can be realized the test respectively to odd column pixel cell and the even column pixel cell of pixel region.
Figure 3 shows that the array base-plate structure schematic diagram that third embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 3.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in this row virtual pixel 101, and the grid of TFT is electrically connected with same first kind calibrating terminal 104 in this row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode in the same virtual pixel 101 in this row virtual pixel 101.This row virtual pixel 101 is divided into three groups according to the color of pixel electrode, and one group of virtual pixel 101 comprises red pixel electrode 1011R, and one group of virtual pixel 101 comprises green pixel electrode 1011G, and one group of virtual pixel 101 comprises blue pixel electrode 1011B.Wherein, the drain/source that comprises TFT in one group of virtual pixel 101 of red pixel electrode 1011R is electrically connected with second a class testing terminal 1053; The drain/source that comprises TFT in one group of virtual pixel 101 of green pixel electrode 1011G is electrically connected with another second class testing terminal 1054; The drain/source that comprises TFT in one group of virtual pixel 101 of blue pixel electrode 1011B is electrically connected with another second class testing terminal 1055.
Array base palte shown in Figure 3 can be realized testing respectively at the pixel cell of different colours pixel electrode in the pixel region.
Should be noted that, except virtual pixel is divided into groups according to above-mentioned two embodiment, can also virtual pixel be divided into N group according to actual testing requirement, in every group of virtual pixel the drain/source of TFT each be electrically connected with second a class testing terminal, N is the integer more than or equal to 2.
Figure 4 shows that the array base-plate structure schematic diagram that four embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 4.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101.Wherein, this row virtual pixel 101 is divided into a group of being positioned at the pel array odd column and is positioned at a group of pel array even column.The grid that is arranged in one group of virtual pixel 101 TFT of pel array odd column shares corresponding grid line 102, and the grid of TFT is electrically connected with a first kind calibrating terminal 1041 in this row virtual pixel 101; The grid that is arranged in one group of virtual pixel 101 TFT of pel array even column shares corresponding grid line 102, and the grid of TFT is electrically connected with another first kind calibrating terminal 1042 in the virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this row virtual pixel 101.In addition, the drain/source of TFT is electrically connected with second a class testing terminal 105 in this row virtual pixel 101.
Should be pointed out that the packet mode to virtual pixel 101 shown in Figure 4 only is a kind of giving an example, and in application, can also divide into groups to virtual pixel 101 according to testing requirement.
In addition, not only virtual pixel 101 can be divided into two groups, can also virtual pixel 101 be divided into M group according to testing requirement, the grid of TFT is electrically connected with a first kind calibrating terminal respectively in every group of virtual pixel, and M is the integer more than or equal to 2.
Figure 5 shows that the array base-plate structure schematic diagram that fifth embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 5.
The one-row pixels unit of the pel array outermost of array base palte is virtual pixel 101.Wherein, this row virtual pixel 101 is divided into a group of being positioned at the pel array odd column and is positioned at a group of pel array even column.The grid that is arranged in one group of virtual pixel 101 TFT of pel array odd column shares corresponding grid line 102, and the grid of TFT is electrically connected with a first kind calibrating terminal 1041 in the virtual pixel 101; The grid that is arranged in one group of virtual pixel 101 TFT of pel array even column shares corresponding grid line 102, and the grid of TFT is electrically connected with another first kind calibrating terminal 1042 in the virtual pixel 101.The drain/source that is arranged in one group of virtual pixel 101 TFT of pel array odd column is electrically connected with second a class testing terminal 1051; The drain/source that is arranged in one group of virtual pixel 101 TFT of pel array even column also is electrically connected with another second class testing terminal 1052.The source/drain of TFT is electrically connected with corresponding data line 103 in this row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this row virtual pixel 101.
Should be pointed out that the packet mode to virtual pixel 101 shown in Figure 5 only is a kind of giving an example, and in application, can also divide into groups to virtual pixel 101 according to testing requirement.
In addition, not only virtual pixel 101 can be divided into two groups, can also virtual pixel 101 be divided into M group according to testing requirement, the grid of TFT is electrically connected with a first kind calibrating terminal respectively in every group of virtual pixel, and M is the integer more than or equal to 2; The drain/source of TFT is electrically connected with second a class testing terminal respectively in every group of virtual pixel.
Figure 6 shows that the array base-plate structure schematic diagram that sixth embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 6.
Two row pixel cells of the pel array outermost of array base palte are virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in this two row virtual pixel 101, and the grid of TFT is electrically connected with same first kind calibrating terminal 104 in the virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this two row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this two row virtual pixel 101.The drain/source that wherein is arranged in one group of virtual pixel 101 TFT of pel array odd column in delegation's virtual pixel 101 is electrically connected with second a class testing terminal 1051; The drain/source that is arranged in one group of virtual pixel 101 TFT of pel array even column in another row virtual pixel 101 is electrically connected with another second class testing terminal 1052.
Array base palte shown in Figure 6 can be realized the test respectively to odd column pixel cell and the even column pixel cell of pixel region.
Should be pointed out that array base palte shown in Figure 6 be a kind of for example and non-limiting.Not only virtual pixel can be divided according to odd column and even column, in application, can also virtual pixel be divided into two groups according to testing requirement, connect second a class testing terminal respectively and test.
In addition, can also be by virtual pixel being divided into three groups even more groups, every group of virtual pixel connects second a class testing terminal respectively and realizes the grouping test.For example, the drain/source that wherein comprises TFT in one group of virtual pixel of red pixel electrode in delegation's virtual pixel is electrically connected with second a class testing terminal, the drain/source that comprises TFT in one group of virtual pixel of green pixel electrode in this row virtual pixel is electrically connected with another second class testing terminal, comprises in another row virtual pixel that the drain/source of TFT in one group of virtual pixel of blue pixel electrode is electrically connected with another second class testing terminal.Other structure annexations can be with reference to shown in Figure 6.
Figure 7 shows that the array base-plate structure schematic diagram that seventh embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 7.
Two row pixel cells of the pel array outermost of array base palte are virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in each row virtual pixel 101, and the grid of TFT is electrically connected with a first kind calibrating terminal (1041,1042) respectively in the virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this two row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this two row virtual pixel 101.The drain/source that wherein is arranged in one group of virtual pixel 101 TFT of pel array odd column in delegation's virtual pixel 101 is electrically connected with second a class testing terminal 1051; The drain/source that is arranged in one group of virtual pixel 101 TFT of pel array even column in another row virtual pixel 101 is electrically connected with another second class testing terminal 1052.
Array base palte shown in Figure 7 can be realized the test respectively to odd column pixel cell and the even column pixel cell of pixel region.
Should be pointed out that array base palte shown in Figure 7 be a kind of for example and non-limiting.Not only virtual pixel can be divided according to odd column and even column, in application, can also virtual pixel be divided into two groups according to testing requirement, connect second a class testing terminal respectively and test.
In addition, can also be by virtual pixel being divided into three groups even more groups, every group of virtual pixel connects second a class testing terminal respectively and realizes the grouping test.For example, the drain/source that wherein comprises TFT in one group of virtual pixel of red pixel electrode in delegation's virtual pixel is electrically connected with second a class testing terminal, the drain/source that comprises TFT in one group of virtual pixel of green pixel electrode in this row virtual pixel is electrically connected with another second class testing terminal, comprises in another row virtual pixel that the drain/source of TFT in one group of virtual pixel of blue pixel electrode is electrically connected with another second class testing terminal.Other structure annexations can be with reference to shown in Figure 7.
Figure 8 shows that the array base-plate structure schematic diagram that eighth embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 8.
Two row pixel cells of the pel array outermost of array base palte are virtual pixel 101.Wherein, the grid that is arranged in one group of virtual pixel 101 TFT of pel array odd column in delegation's virtual pixel 101 shares corresponding grid line 102, and the grid of TFT is electrically connected with a first kind calibrating terminal 1041 in this row virtual pixel 101; The grid that is arranged in one group of virtual pixel 101 TFT of pel array even column in another row virtual pixel 101 shares corresponding grid line 102, and the grid of TFT is electrically connected with another first kind calibrating terminal 1042 in this row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this two row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this two row virtual pixel 101.The drain/source of TFT also is electrically connected with the same second class testing terminal 105 in this two row virtual pixel 101.
Array base palte shown in Figure 8 can be realized the test respectively to odd column pixel cell and the even column pixel cell of pixel region.
Should be pointed out that array base palte shown in Figure 8 is that a kind of also for example, all grids of the first row virtual pixel are connected to a first kind calibrating terminal for example and non-limiting, all grids of the second row virtual pixel are connected to other first kind calibrating terminal.And, not only virtual pixel can be divided according to odd column and even column, in application, can also virtual pixel be divided into two groups according to testing requirement, one group of virtual pixel in every row connects a first kind calibrating terminal respectively to be tested.
In addition, can also be by virtual pixel being divided into three groups even more groups, every group of virtual pixel connects a first kind calibrating terminal respectively and realizes the grouping test.For example, the grid that comprises TFT in one group of virtual pixel of red pixel electrode in delegation's virtual pixel is electrically connected with a first kind calibrating terminal, the grid that comprises TFT in one group of virtual pixel of green pixel electrode in this row virtual pixel is electrically connected with another first kind calibrating terminal, comprises in another row virtual pixel that the grid of TFT in one group of virtual pixel of blue pixel electrode is electrically connected with another first kind calibrating terminal.Other structure annexations can be with reference to shown in Figure 8.
Figure 9 shows that the array base-plate structure schematic diagram that ninth embodiment of the invention provides.The substrate of array base palte is not shown in Fig. 9.
The triplex row pixel cell of the pel array outermost of array base palte is virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in this triplex row virtual pixel 101, and the grid of TFT is electrically connected with same first kind calibrating terminal 104 in this triplex row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this triplex row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode in the same virtual pixel 101 in this triplex row virtual pixel 101.Wherein first row comprises that the drain/source of TFT in one group of virtual pixel 101 of red pixel electrode 1011R is electrically connected with second a class testing terminal 1053 in the virtual pixel 101; Second row comprises that the drain/source of TFT in one group of virtual pixel 101 of green pixel electrode 1011G is electrically connected with second a class testing terminal 1054 in the virtual pixel 101; The drain/source that comprises TFT in one group of virtual pixel 101 of blue pixel electrode 1011B in the third line virtual pixel 101 is electrically connected with second a class testing terminal 1055.
Array base palte shown in Figure 9 can be realized testing respectively at the pixel cell of different colours pixel electrode in the pixel region.
Should be pointed out that array base-plate structure shown in Figure 9 only be a kind of for example and non-limiting.For example, can also test the pixel cell that comprises green or blue pixel electrode by the first row virtual pixel, by the second row virtual pixel pixel cell that comprises redness or blue pixel electrode is tested, by the third line virtual pixel the pixel cell that comprises redness or green pixel electrode is tested.
In addition, not only virtual pixel can be divided according to the color of pixel electrode, can also be divided into three groups to virtual pixel according to actual testing requirement and test.
Figure 10 shows that the array base-plate structure schematic diagram that tenth embodiment of the invention provides.The substrate of array base palte is not shown in Figure 10.
The triplex row pixel cell of the pel array outermost of array base palte is virtual pixel 101.Wherein, the grid of TFT shares corresponding grid line 102 in each row virtual pixel 101, and the grid of TFT is electrically connected with a first kind calibrating terminal (1043,1044,1045) respectively in each row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this triplex row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode in the same virtual pixel 101 in this triplex row virtual pixel 101.Wherein first row comprises that the drain/source of TFT in one group of virtual pixel 101 of red pixel electrode 1011R is electrically connected with second a class testing terminal 1053 in the virtual pixel 101; Second row comprises that the drain/source of TFT in one group of virtual pixel 101 of green pixel electrode 1011G is electrically connected with second a class testing terminal 1054 in the virtual pixel 101; The drain/source that comprises TFT in one group of virtual pixel 101 of blue pixel electrode 1011B in the third line virtual pixel 101 is electrically connected with second a class testing terminal 1055.
Array base palte shown in Figure 10 can be realized testing respectively at the pixel cell of different colours pixel electrode in the pixel region.
Should be pointed out that array base-plate structure shown in Figure 10 only be a kind of for example and non-limiting.For example, can also test the pixel cell that comprises green or blue pixel electrode by the first row virtual pixel, by the second row virtual pixel pixel cell that comprises redness or blue pixel electrode is tested, by the third line virtual pixel the pixel cell that comprises redness or green pixel electrode is tested, also for example, the all grids of the first row virtual pixel are connected to a first kind calibrating terminal, the all grids of the second row virtual pixel are connected to other first kind calibrating terminal, and all grids of the third line virtual pixel are connected to another first kind calibrating terminal.
In addition, not only virtual pixel can be divided according to the color of pixel electrode, can also be divided into three groups to virtual pixel according to actual testing requirement and test.
Figure 11 shows that the array base-plate structure schematic diagram that eleventh embodiment of the invention provides.The substrate of array base palte is not shown in Figure 11.
The triplex row pixel cell of the pel array outermost of array base palte is virtual pixel 101.Wherein, first row comprises that the grid of TFT in one group of virtual pixel 101 of red pixel electrode 1011R shares corresponding grid line 102 in the virtual pixel 101, and the grid of TFT is electrically connected with a first kind calibrating terminal 1043 in this row virtual pixel 101; The second row virtual pixel 101 comprises that the grid of TFT in one group of virtual pixel 101 of green pixel electrode 1011G shares corresponding grid line 102, and the grid of TFT is electrically connected with a first kind calibrating terminal 1044 in this row virtual pixel 101; The third line virtual pixel 101 comprises that the grid of TFT in one group of virtual pixel 101 of blue pixel electrode 1011B shares corresponding grid line 102, and the grid of TFT is electrically connected with a first kind calibrating terminal 1045 in this row virtual pixel 101.The source/drain of TFT is electrically connected with corresponding data line 103 in this triplex row virtual pixel 101.The drain/source of TFT is electrically connected with pixel electrode 1011 in the same virtual pixel 101 in this triplex row virtual pixel 101.The drain/source of TFT is electrically connected with the same second class testing terminal 105 in this triplex row virtual pixel 101.
Array base palte shown in Figure 11 can be realized testing respectively at the pixel cell of different colours pixel electrode in the pixel region.Therefore, first row only is shown among Figure 11 comprises one group of virtual pixel 101 of red pixel electrode 1011R and the annexation between the second class testing terminal 105 in the virtual pixel 101, annexation between one group of virtual pixel 101 that second row comprises green pixel electrode 1011G in the virtual pixel 101 and the second class testing terminal 105 reaches one group of virtual pixel 101 comprising blue pixel electrode 1011B in the third line virtual pixel 101 and the annexation between the second class testing terminal 105.Annexation among Figure 11 between not shown other virtual pixels 101 and the second class testing terminal 105.
Should be pointed out that array base-plate structure shown in Figure 11 only be a kind of for example and non-limiting.For example, can also test the pixel cell that comprises green or blue pixel electrode by the first row virtual pixel, by the second row virtual pixel pixel cell that comprises redness or blue pixel electrode is tested, by the third line virtual pixel the pixel cell that comprises redness or green pixel electrode is tested.Again for example, can also comprise three second class testing terminals, the drain/source of TFT is electrically connected with second a class testing terminal respectively in the above-mentioned one group of virtual pixel in each row.
In addition, not only virtual pixel can be divided according to the color of pixel electrode, can also be divided into three groups to virtual pixel according to actual testing requirement and test.
Among Fig. 1 ~ Figure 11 of embodiment of the invention correspondence, first kind calibrating terminal all is connected with corresponding grid line, and the second class testing terminal all is connected with corresponding pixel electrode.Should be pointed out that therefore, first kind calibrating terminal is connected with grid line, is equivalent to first kind calibrating terminal and is connected with the grid of TFT because the grid of TFT is electrically connected with grid line.Because the drain/source of TFT is connected with pixel electrode, therefore, the second class testing terminal is connected with pixel electrode, is equivalent to the second class testing terminal and is connected with the drain/source of TFT.
In the described array base palte of each embodiment of the invention described above, the grid of TFT is connected by first lead with first kind calibrating terminal in the virtual pixel, and this first lead and grid line are positioned at same one deck; Certainly this first lead also can be made of multistage, connect by via hole between each section, wherein each section all can with grid line, source electrode and drain electrode, pixel electrode in any be positioned at same one deck, the employing identical materials.The drain/source of TFT is connected by second lead with the second class testing terminal in the virtual pixel, and this second lead and grid line are positioned at same one deck, perhaps with data line bit in same one deck, perhaps be positioned at same one deck with pixel electrode; Same, this first lead also can be made of multistage, connect by via hole between each section, wherein each section all can with grid line, source electrode and drain electrode, pixel electrode in any be positioned at same one deck, the employing identical materials.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (21)
1. array base palte, comprise substrate and be positioned at pel array on the described substrate, many the data wires that described pel array comprises many grid lines, intersects with described many grid lines insulation, with the pixel cell that is positioned at described grid line and described data wire infall, described pixel cell comprises thin-film transistor TFT and pixel electrode, it is characterized in that
The capable pixel cell of P of described pel array periphery is virtual pixel;
Described array base palte also comprises M first kind calibrating terminal and N the second class testing terminal, and P, M, N are the integer more than or equal to 1;
The grid of TFT is electrically connected with described first kind calibrating terminal in the described virtual pixel; The drain/source of TFT is electrically connected with the described second class testing terminal in the described virtual pixel.
2. array base palte according to claim 1 is characterized in that, P=1, and the one-row pixels unit of described pel array periphery is virtual pixel.
3. array base palte according to claim 2 is characterized in that, M=1, and the grid of TFT all is electrically connected to same described first kind calibrating terminal in the described virtual pixel.
4. array base palte according to claim 3 is characterized in that, N=1, and the drain/source of TFT all is electrically connected with the described same second class testing terminal in the described virtual pixel.
5. array base palte according to claim 3 is characterized in that, N 〉=2, and described virtual pixel is divided into N group, the corresponding electrical connection of drain/source of TFT in each second class testing terminal and the one group of virtual pixel.
6. array base palte according to claim 5, it is characterized in that, N=2, described virtual pixel is divided into a group of being positioned at described pel array odd column and is positioned at a group of described pel array even column, be arranged in one of them of drain/source and the described second class testing terminal of odd column that described virtual pixel is positioned at one group of virtual pixel TFT of described pel array and be electrically connected, another of the one group of virtual pixel TFT drain/source that is arranged in described pel array even column and the described second class testing terminal is electrically connected.
7. array base palte according to claim 5, it is characterized in that, N=3, described virtual pixel is divided into one group that comprises the red pixel electrode, comprise a group of green pixel electrode, with comprise a group of blue pixel electrode, the drain/source that comprises TFT in one group of virtual pixel of red pixel electrode is electrically connected with second a class testing terminal, the drain/source that comprises TFT in one group of virtual pixel of green pixel electrode is electrically connected with another second class testing terminal, comprises that the drain/source of TFT in one group of virtual pixel of blue pixel electrode is electrically connected with another second class testing terminal.
8. array base palte according to claim 2 is characterized in that, M 〉=2, and described virtual pixel is divided into M group, the corresponding electrical connection of grid of TFT in each described first kind calibrating terminal and the one group of virtual pixel.
9. array base palte according to claim 8 is characterized in that, N=1, and the drain/source of TFT all is electrically connected with the same second class testing terminal in the described virtual pixel.
10. array base palte according to claim 8 is characterized in that, N 〉=2, and the drain/source of TFT is electrically connected with second a class testing terminal respectively in every group of virtual pixel.
11. array base palte according to claim 1 is characterized in that, P=2, and two row pixel cells of described pel array periphery are virtual pixel.
12. array base palte according to claim 11 is characterized in that, M=1, and the grid of TFT all is electrically connected with same first kind calibrating terminal in the described virtual pixel; Perhaps M=2, in the described virtual pixel of each row the grid of TFT respectively with the corresponding electrical connection of a described first kind calibrating terminal.
13. array base palte according to claim 12 is characterized in that, N=2, and the drain/source that is arranged in one group of virtual pixel TFT of described pel array odd column in the described first row virtual pixel is electrically connected with second a class testing terminal; The drain/source that is arranged in one group of virtual pixel TFT of described pel array even column in the described second row virtual pixel is electrically connected with another second class testing terminal.
14. array base palte according to claim 11 is characterized in that, M=2, and the one group of virtual pixel TFT grid that is arranged in described pel array odd column in the described delegation virtual pixel is electrically connected with a first kind calibrating terminal; The grid that is arranged in one group of virtual pixel TFT of described pel array even column in another row virtual pixel is electrically connected with another first kind calibrating terminal.
15. array base palte according to claim 14 is characterized in that, N=1, and the drain/source of TFT all is electrically connected with the same described second class testing terminal in the described virtual pixel.
16. array base palte according to claim 1 is characterized in that, P=3, and the triplex row pixel cell of described pel array periphery is virtual pixel.
17. array base palte according to claim 16 is characterized in that, M=1, and the grid of TFT all is electrically connected with same first kind calibrating terminal in the described virtual pixel; Perhaps M=3, the grid of TFT is electrically connected with a first kind calibrating terminal respectively in the described virtual pixel of each row.
18. array base palte according to claim 17 is characterized in that, N=3, described first row comprise that the drain/source of TFT in one group of virtual pixel of red pixel electrode is electrically connected with second a class testing terminal in the virtual pixel; Described second row comprises that the drain/source of TFT in one group of virtual pixel of green pixel electrode is electrically connected with another second class testing terminal in the virtual pixel; The drain/source that comprises TFT in one group of virtual pixel of blue pixel electrode in described the third line virtual pixel is electrically connected with another second class testing terminal.
19. array base palte according to claim 16 is characterized in that, M=3, described first row comprise that the grid of TFT in one group of virtual pixel of red pixel electrode is electrically connected with a first kind calibrating terminal in the virtual pixel; Described second row comprises that the grid of TFT in one group of virtual pixel of green pixel electrode is electrically connected with another first kind calibrating terminal in the virtual pixel; The grid that comprises TFT in one group of virtual pixel of blue pixel electrode in described the third line virtual pixel is electrically connected with another first kind calibrating terminal.
20. array base palte according to claim 19 is characterized in that, N=1, and the drain/source of TFT all is electrically connected with the same second class testing terminal in the described virtual pixel.
21., it is characterized in that the grid of TFT is connected by first lead with described first kind calibrating terminal in the described virtual pixel according to each described array base palte of claim 1 ~ 20, described first lead and described grid line are positioned at same one deck; The drain/source of TFT is connected by second lead with the described second class testing terminal in the described virtual pixel, and described second lead and described grid line or data wire or pixel electrode are positioned at same one deck.
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