CN103258824B - The memory cell of flash memory and formation method - Google Patents
The memory cell of flash memory and formation method Download PDFInfo
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Abstract
A kind of memory cell of flash memory and formation method, wherein, a kind of memory cell of flash memory comprises: Semiconductor substrate, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is in both sides, array area; Be positioned at the separator of semiconductor substrate surface successively, bottom selects grid and underlying dielectric layer; Be positioned at the control grid layer on described underlying dielectric layer surface, described control grid layer also comprises: some layers of polysilicon layer and the some interlayer dielectric layers being positioned at each layer polysilicon layer surface; Run through the memory connector array of the control grid layer thickness of described array area; Be positioned at some layers of polysilicon layer of the control grid layer of stepped region, successively to successively decrease formation ladder from the bottom to most top layer, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region.The memory cell of the flash memory that the embodiment of the present invention provides makes the bit density of flash memory improve, and position cost reduces.
Description
Technical field
The present invention relates to semiconductor device and forming method thereof, particularly a kind of memory cell of flash memory and formation method.
Background technology
In recent years, the development of flash memory (flashmemory) is particularly rapid.The main feature of flash memory is the information that can keep for a long time when not powering up storing; And have that integrated level is high, access speed is fast, be easy to the advantages such as erasing and rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.
In order to improve flash memory bit density (bitdensity) further, reduce position cost (bitcost) simultaneously, a kind of low cost three-dimensional multilayer structure (Bit-CostScalable of flash memory, being called for short BiCS) technology obtains further development, please refer to Fig. 1, for the cross-sectional view of the memory cell of existing flash memory BiCS structure, comprising:
Semiconductor substrate 100, described Semiconductor substrate 100 comprises array area 101 and stepped region 102, and described stepped region 102 is in both sides, array area 101; Be positioned at the separator 103 on described Semiconductor substrate 100 surface; Grid 104 selected by the bottom being positioned at separator 103 surface; Be positioned at the underlying dielectric layer 105 that grid 104 surface selected by bottom, grid connector array 106 selected by the bottom running through the separator 103 of described array area 101, bottom selection grid 104 and underlying dielectric layer 105 thickness;
Be positioned at the control grid layer 107 on described underlying dielectric layer 105 and bottom selection grid connector array 106 surface, described control grid layer also comprises: some layers of polysilicon layer 121, and the interlayer dielectric layer 122 of each layer polysilicon layer 121 surface coverage; Run through the memory connector array 108 of control grid layer 107 thickness of described array area 101, select connector array 106 one_to_one corresponding with bottom;
The top layer being positioned at control grid layer 107 surface of described array area 101 selects grid 109, be positioned at the top layer dielectric layer 110 that described top layer selects grid 109 surface, be positioned at the bit line 111 on described top layer dielectric layer 110 surface, running through described top layer dielectric layer 110 and top layer selects the top layer of grid 109 thickness to select connector array 112, and with memory connector array 108 one_to_one corresponding;
Be positioned at the insulating barrier 114 on control grid layer 107 surface of described stepped region 102, be positioned at some connecting lines 113 on described insulating barrier 114 surface; Run through some attachment plugs 115 of described insulating barrier 114 thickness, described some attachment plugs 115 make some connecting lines 113 be connected respectively with the some layers of polysilicon layer 121 in control grid layer 107.
Please refer to Fig. 2, Fig. 2 is that Fig. 1 is along AA ' direction, ignore the vertical view of insulating barrier 114 and interlayer dielectric layer 122 (please refer to Fig. 1), polysilicon layer 121 in the control grid layer 107 of described stepped region, successively increase progressively same size by the superiors' polysilicon layer to orlop polysilicon layer to the outside away from array area 101 by the position of next-door neighbour array area, formed stepped; Described attachment plug 115 projection on a semiconductor substrate 100, relative to the boundary oblique that array area 101 connects with stepped region 102.
Be can also find memory cell of more flash memory and forming method thereof in the U.S. patent documents of US2011/0073935A1 at publication number.
But, the BiCS structure Existential Space waste of existing flash memory, the bit density causing flash memory reduces, the volume of flush memory device becomes large, the also corresponding reduction of position cost, institute's rheme cost often manufactures the manufacturing cost required for the memory space of a data position in the manufacturing process of memory device, is the feature embodying memory device cost.
Summary of the invention
The problem that the present invention solves is the area reducing flash memory control grid layer, thus improves the bit density of flash memory, reduces the position cost of flash memory.
For solving the problem, embodiments providing a kind of memory cell of flash memory, comprising:
Semiconductor substrate, described Semiconductor substrate comprises array area and stepped region, and described stepped region is in both sides, array area; Be positioned at the separator of semiconductor substrate surface; Grid selected by the bottom being positioned at insulation surface; Be positioned at the underlying dielectric layer that grid surface selected by bottom;
Grid connector array selected by the bottom running through the separator of described array area, bottom selection grid and underlying dielectric layer thickness;
Be positioned at the control grid layer of described underlying dielectric layer and bottom selection grid connector array surface, described control grid layer also comprises: some layers of polysilicon layer and the interlayer dielectric layer being positioned at each layer polysilicon layer surface, wherein, run through the memory connector array of the control grid layer thickness of described array area, and connector array one_to_one corresponding selected by described memory connector array and bottom;
Be positioned at the size of some layers of polysilicon layer of the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region;
Be positioned at the insulating barrier on the control grid layer surface of described stepped region, be positioned at some connecting lines of described surface of insulating layer, described some connecting lines are connected with some layers of polysilicon layer in control grid layer respectively respectively by running through some attachment plugs of described thickness of insulating layer, the projection arrangement on a semiconductor substrate of described some attachment plugs is linear, and described linear parallel with the border that array area contacts with stepped region.
Optionally, also comprise: the some top layers being positioned at the control grid layer surface of described array area select grid; Be positioned at the top layer dielectric layer that some top layers select grid surface; Be positioned at some bit lines of top layer dielectric layer surface; The top layer running through described top layer dielectric layer and top layer selection grid thickness selects connector array, and described top layer selects connector array and memory connector array one_to_one corresponding, and is connected with bit line.
Optionally, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.
Optionally, described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
Optionally, the size of some layers of polysilicon layer in the control grid layer of described stepped region, the polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases, and every one deck polysilicon layer relatively reduce with lower one deck polysilicon layer measure-alike.
Optionally, described separator comprises oxide layer, catches charge layer and barrier oxide layer, described in catch charge layer be positioned at described oxide layer surface, catch charge layer surface described in described barrier oxide layer is positioned at.
Optionally, the material of described oxide layer is silica, described in catch charge layer material be silicon nitride, the material oxidation silicon of described barrier oxide layer or aluminium oxide.
The embodiment of the present invention also provides a kind of formation method of memory cell of flash memory, comprising:
There is provided Semiconductor substrate, semiconductor substrate surface has separator successively, bottom selects grid, underlying dielectric layer and control grid layer, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is positioned at both sides, array area; Grid connector array selected by the bottom running through the separator of described array area, bottom selection grid and underlying dielectric layer thickness; Described control grid layer comprises: some layers of polysilicon layer and the interlayer dielectric layer being positioned at each layer polysilicon layer surface, and wherein, run through the memory connector array of the control grid layer thickness of described array area, connector array one_to_one corresponding selected by described memory connector array and bottom;
Hard mask layer is formed on control grid layer surface;
The first photoresist layer is formed, with the first photoresist layer for the control grid layer beyond mask removal array area and stepped region and hard mask layer on described hard mask layer surface;
Remove the first photoresist layer of stepped region and hard mask layer till exposing the first interlayer dielectric layer, described first interlayer dielectric layer is the interlayer dielectric layer of most top layer in control grid layer, removes the first photoresist layer of array area;
Between hard mask layer and ground floor, dielectric layer surface forms the second photoresist layer;
Repeatedly etch interlayer dielectric layer and polysilicon layer and thinning second photoresist layer several times, make the size of some layers of polysilicon layer in the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder from the bottom to top, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region;
Control grid layer surface in stepped region forms insulating barrier, forms the some attachment plugs running through described thickness of insulating layer, is connected respectively with some layers of polysilicon layer;
Form some connecting lines at insulating barrier and attachment plug surface, described some connecting lines are connected with some polysilicon layers respectively by some attachment plugs.
Optionally, also comprise step: the control grid layer surface in array area forms some top layers and selects grid, select grid surface to form top layer dielectric layer at some top layers; Formed and run through the top layer selection connector array that grid and top layer thickness of dielectric layers are selected in described top, described top layer selects connector array and memory connector array one_to_one corresponding; Form some bit lines at described top layer dielectric layer surface, described bit line and top layer select connector array to be connected.
Optionally, described between hard mask layer and ground floor dielectric layer surface form the second photoresist layer, and repeatedly etch interlayer dielectric layer and polysilicon layer and the method for thinning second photoresist layer several times, also comprise step: dielectric layer surface forms the second photoresist layer between hard mask layer and ground floor, and the first step district exposed in stepped region, described first step district is the region in stepped region corresponding to bottom step; With the second photoresist layer and hard mask layer for mask, dielectric layer and the first polysilicon layer between etching of first layer, and expose the second interlayer dielectric layer, described first polysilicon layer is the polysilicon layer of most top layer in control grid layer, and described second interlayer dielectric layer is the interlayer dielectric layer of one deck under the first interlayer dielectric layer; Thinning second photoresist layer also exposes the second step district of the first interlayer dielectric layer in stepped region, and described second step district is region corresponding on upper level step place first interlayer dielectric layer of bottom step; With the second photoresist layer and hard mask layer for mask, dielectric layer and the first polysilicon layer between second step district etching of first layer, dielectric layer and the second polysilicon layer between first step district etching of second layer, described second polysilicon layer is the polysilicon layer of one deck under the first polysilicon layer; Thinning second photoresist layer also exposes the 3rd stepped region of the first interlayer dielectric layer, and described 3rd stepped region is region corresponding on the interlayer dielectric layer of upper level step place first, second step district.
Optionally, the technique of described thinning photoresist is dry etching.
Optionally, the technique of described etching interlayer dielectric layer and polysilicon layer is reactive ion etching method.
Optionally, described interlayer dielectric layer is 1 ~ 50 for the etching selection ratio of hard mask layer, and described polysilicon layer is 5 ~ 200 for the etching selection ratio of hard mask layer.
Optionally, described hard mask layer is that one or more in insulation material layer, metal level or amorphous carbon layer overlap.
Optionally, described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
Optionally, the material of described metal level is one or more the alloy in copper, tungsten, aluminium.
Optionally, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.
Optionally, described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
Optionally, described hard mask layer is not identical with the material of interlayer dielectric layer.
Optionally, the size of some layers of polysilicon layer in the control grid layer of described stepped region, the polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases, and every one deck polysilicon layer relatively reduce with lower one deck polysilicon layer measure-alike.
Optionally, described separator successively by oxide layer, catch charge layer and barrier oxide layer is stacking forms;
Optionally, the material of described oxide layer is silica, described in catch charge layer material be silicon nitride, the material oxidation silicon of described barrier oxide layer or aluminium oxide.
Compared with prior art, the embodiment of the present invention has the following advantages:
The memory cell of the flash memory that embodiments of the invention provide, while the stacked structure not changing some layers of polysilicon layer in prior art in control grid layer, some layers of polysilicon layer in control grid layer on stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and it is described linear parallel with the sideline that array area contacts with stepped region, can solve in the BiCS structure of existing control grid layer, the space waste problem of control grid layer on the stepped region of Semiconductor substrate.Make, while retaining the polysilicon layer multilayer lamination structure in control grid layer, to reduce the area of control grid layer, thus improve the bit density of flash memory, and reduce the position cost of flash memory.
The memory cell formation method of the flash memory that embodiments of the invention provide, by thinning second photoresist layer repeatedly and etching interlayer dielectric layer and polysilicon layer, make polysilicon layer in control grid layer at stepped region forming station scalariform, described formation method can with less processing step, accurate forming station scalariform, there is simple process, the advantage that shaping accuracy is high.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the memory cell of existing flash memory BiCS structure;
Fig. 2 is for Fig. 1 to ignore the vertical view of insulating barrier and interlayer dielectric layer along AA ' direction;
Fig. 3 is the process chart of the formation method of the memory cell of the flash memory of the embodiment of the present invention;
Fig. 4 to Figure 18 is the structural representation of the formation method of the memory cell of the flash memory of the embodiment of the present invention;
Figure 19 be Figure 17 along CC ' direction, ignore the vertical view of some interlayer dielectric layers in insulating barrier, memory connector array and control grid layer;
Figure 20 is the equivalent circuit diagram of the memory cell of the flash memory of the embodiment of the present invention.
Embodiment
Inventor finds, in the BiCS structure of existing flash memory, some layers of polysilicon layer in the control grid layer of flash memory are on Semiconductor substrate stepped region, by the position of next-door neighbour array area from top to bottom successively to increase progressively to the outside away from array area formed stepped, and cause the space waste of the memory cell of flash memory, and then add the area of memory cell, thus reduce the bit density of flash memory, add the position cost of flash memory.
In order to reduce the area of the memory cell of flash memory, thus improving the bit density of flash memory, reducing the position cost of flash memory, inventor providing a kind of memory cell of flash memory, comprising:
Semiconductor substrate, described Semiconductor substrate comprises array area and stepped region, and described stepped region is in both sides, array area; Be positioned at the separator of semiconductor substrate surface; Grid selected by the bottom being positioned at insulation surface; Be positioned at the underlying dielectric layer that grid surface selected by bottom; Grid connector array selected by the bottom running through the separator of described array area, bottom selection grid and underlying dielectric layer thickness; Be positioned at the control grid layer of described underlying dielectric layer and bottom selection grid connector array surface, described control grid layer also comprises: some layers of polysilicon layer and the some interlayer dielectric layers being positioned at each layer polysilicon layer surface; Wherein, run through the memory connector array of the control grid layer thickness of described array area, and connector array one_to_one corresponding selected by described memory connector array and bottom; Be positioned at some layers of polysilicon layer of the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region; Be positioned at the insulating barrier on the control grid layer surface of described stepped region, be positioned at some connecting lines of described surface of insulating layer, described some connecting lines are connected with some layers of polysilicon layer in control grid layer respectively respectively by running through some attachment plugs of described thickness of insulating layer, the projection arrangement on a semiconductor substrate of described some attachment plugs is linear, and described linear parallel with the sideline that array area contacts with stepped region;
The some top layers being positioned at the control grid layer surface of described array area select grid; Be positioned at the top layer dielectric layer that some top layers select grid surface; Be positioned at some bit lines of top layer dielectric layer surface; The top layer running through described top layer dielectric layer and top layer selection grid thickness selects connector array, and described top layer selects connector array and memory connector array one_to_one corresponding, and is connected with bit line.
The memory cell of the flash memory that inventor provides, do not change flash memory in prior art control grid layer some layers of polysilicon layer stacked structure while, by making some layers of polysilicon layer in the control grid layer on Semiconductor substrate stepped region, on the direction of the same row of next-door neighbour Semiconductor substrate array area, successively successively decreased to the superiors by orlop, form stair-stepping method, to solve in the BiCS structure of existing control grid layer, some layers of polysilicon layer in control grid layer successively increase progressively same size by the position being close to array area from top to bottom to the outside away from array area, form stepped and space waste problem that is that cause, make while retaining the polysilicon layer multilayer lamination structure in control grid layer, reduce the area of the memory cell of flash memory, thus improve the bit density of flash memory, and reduce the position cost of flash memory.
In order to form the memory cell of described flash memory, inventor additionally provides a kind of formation method of memory cell of flash memory, is described in detail, please refer to Fig. 3 below with reference to specific embodiment, and the formation method of the memory cell of flash memory, comprises step:
Step S101, provides Semiconductor substrate, and semiconductor substrate surface has separator successively, bottom selects grid, underlying dielectric layer and control grid layer, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is positioned at both sides, array area; Grid connector array selected by the bottom running through the separator of described array area, bottom selection grid and underlying dielectric layer thickness; Described control grid layer comprises: some layers of polysilicon layer and the interlayer dielectric layer being positioned at each layer polysilicon layer surface, wherein, run through the memory connector array of the control grid layer thickness of described array area, connector array one_to_one corresponding selected by described memory connector array and bottom.
Step S102, forms hard mask layer on control grid layer surface.
Step S103, forms the first photoresist layer on described hard mask layer surface, with the first photoresist layer for the control grid layer beyond mask removal array area and stepped region and hard mask layer.
Step S104, removes the first photoresist layer of stepped region and hard mask layer till exposing the first interlayer dielectric layer, and described first interlayer dielectric layer is the interlayer dielectric layer of most top layer in control grid layer, removes the first photoresist layer of array area.
Step S105, between hard mask layer and ground floor, dielectric layer surface forms the second photoresist layer.
Step S106, repeatedly etch interlayer dielectric layer and polysilicon layer, and thinning second photoresist layer several times, make the size of some layers of polysilicon layer in the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder from the bottom to top, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region.
Step S107, the control grid layer surface in stepped region forms insulating barrier, forms the attachment plug running through described thickness of insulating layer, is connected respectively respectively with some layers of polysilicon layer.
Step S108, form some connecting lines at insulating barrier and attachment plug surface, described some connecting lines are connected with some polysilicon layers respectively by some attachment plugs.
The memory cell formation method of the flash memory that embodiments of the invention provide, by thinning second photoresist layer repeatedly and etching interlayer dielectric layer and polysilicon layer, make polysilicon layer in control grid layer at stepped region forming station scalariform, described formation method can with less processing step, accurate forming station scalariform, there is simple process, the advantage that shaping accuracy is high.
Fig. 4 to Figure 18 is the structural representation of the formation method of the memory cell of embodiment of the present invention flash memory.
Please refer to Fig. 4, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 comprises array area 201 and stepped region 202, described stepped region 202 is in both sides, array area 201, Semiconductor substrate 200 surface has separator 210, separator 210 surface has bottom and selects grid 220, bottom selects grid 220 surface to have underlying dielectric layer 221, underlying dielectric layer 221 surface has control grid layer 230, run through the separator 210 of described array area 201, bottom selects the bottom of the thickness of grid 220 and underlying dielectric layer 221 to select connector array 222, described control grid layer 230 also comprises: the interlayer dielectric layer (not shown) of some layers of polysilicon layer (not shown) and each polysilicon layer surface coverage, wherein, run through the memory connector array 231 of the thickness of the control grid layer 230 of described array area 201, described memory connector array 231 selects connector array 222 one_to_one corresponding with bottom.
The material of described Semiconductor substrate 200 is silicon or silicon-on-insulator, and effect is for subsequent technique provides workbench.
Described separator 210 successively by oxide layer 211, catch charge layer 212 and barrier oxide layer 213 is stacking forms, the material of described oxide layer 211 is silica, described material of catching charge layer 212 is silicon nitride, the material oxidation silicon of described barrier oxide layer 213 or aluminium oxide.
Wherein, described in catch charge layer 212 effect be store electrons, instead of the effect of the floating boom in existing technique, further can reduce the size of memory cell.
Described bottom selects the material of grid 220 to be polysilicon, the material of described underlying dielectric layer 221 is silicon nitride, the material of the interlayer dielectric layer in described control grid layer 230 is insulating material or amorphous carbon, and described insulating material is the multiple-level stack of silica, silicon nitride or silica and silicon nitride.
Described separator 210, bottom select the formation process of grid 220 and underlying dielectric layer 221 to be sedimentation, preferably chemical vapour deposition technique, form separator 210 successively, bottom selects grid 220 and underlying dielectric layer 221 at Semiconductor substrate 200 surface deposition.
The formation process of bottom selection grid connector array 222 is: also graphical at underlying dielectric layer 221 surface-coated photoresist, take photoresist as mask etching underlying dielectric layer 221, bottom selects grid 220 and separator 210 to form some openings until expose Semiconductor substrate 200, preferably dry etching, form silicon oxide layer at the sidewall of described opening and expose Semiconductor substrate 200, the technique forming described silicon oxide layer can be chemical vapour deposition technique, polysilicon is filled until flush with underlying dielectric layer 221 surface in the Semiconductor substrate 200 of open bottom and silicon oxide layer surface, form bottom and select grid connector array 222.
The surperficial formation control gate layer 230 of grid connector array 222 is selected at described underlying dielectric layer 221 and bottom, the formation process of described control grid layer 230 is: the surface deposition polysilicon layer selecting grid connector array 222 at underlying dielectric layer 221 and bottom, interlayer dielectric layer is formed at described polysilicon layer surface deposition, the material of described interlayer dielectric layer is insulating material or amorphous carbon, described insulating material is silica, silicon nitride, silicon oxynitride, deposition of polysilicon layer and interlayer dielectric layer several times are successively continued, formation control gate layer 230 on described interlayer dielectric layer surface.
The formation process of described memory connector array 231 is: also graphical at control grid layer 230 surface-coated photoresist, be that some polysilicon layers in mask etching control grid layer 230 and interlayer dielectric layer form the opening running through control grid layer 230 thickness with photoresist, form silicon nitride layer at the sidewall of described opening and expose bottom and select grid connector array 222 surface, bottom in opening is selected to fill polysilicon until flush with control grid layer 230 surface in grid connector array 222 and silicon nitride layer surface, forms memory connector array 231.
Please refer to Fig. 5, hard mask layer 240 is formed on control grid layer 230 surface, the first photoresist layer 241 is formed on described hard mask layer 240 surface, with the first photoresist layer 241 for the control grid layer 230 beyond mask removal array area 201 and stepped region 202 and hard mask layer 240, and separator 210, bottom selection grid 220 and underlying dielectric layer 221.
Described hard mask layer 240 is by insulating material, one or more in metal or amorphous carbon overlap, described insulating material is silica, the multiple-level stack of silicon nitride or silica and silicon nitride, metal is copper, tungsten, one or more alloy in aluminium, the material of hard mask layer 240 is different from the material of the interlayer dielectric layer in control grid layer 230, formation process is sedimentation, preferably chemical vapour deposition technique, described hard mask layer 240 is different from the material of interlayer dielectric layer, can be used for the mask as subsequent etching interlayer dielectric layer and polysilicon layer, do not react with etching gas.
Apply photoresist and image conversion, form the first photoresist layer 241, described first photoresist layer 241 covers array area 201 and stepped region 202 correspondence position of hard mask layer 240, with the first photoresist layer 241 for mask, removed the hard mask layer 240 outside array area 201 and stepped region 202, control grid layer 230, separator 210, bottom selection grid 220 and underlying dielectric layer 221 by etching, described etching technics is dry etching or wet etching.
Please refer to Fig. 6, remove the first photoresist layer 241 of stepped region 202 and hard mask layer 240 till exposing the first interlayer dielectric layer 232, described first interlayer dielectric layer 232 is the interlayer dielectric layer of most top layer in control grid layer 230.
The first photoresist layer 241 of stepped region 202 is removed by dry etching, described etching gas is one or more in nitrogen, oxygen, fluorocarbon gases and hydrocarbon gas, with the first photoresist layer 241 for mask, dry etching or wet etching remove the hard mask layer 240 of stepped region 202, until expose interlayer dielectric layer 232.
Please refer to Fig. 7 and Fig. 8, Fig. 8 is the end view of Fig. 7 on BB ' direction, remove the first photoresist layer 241 (please refer to Fig. 6) of array area 201, the second photoresist layer 242 is formed at hard mask layer 240 and the first interlayer dielectric layer 232 surface, and the first step district 203 exposed in stepped region 202, the region of described first step district 203 corresponding to the bottom step of ladder that formed in the inherent subsequent technique in stepped region 202.
The technique removing the first photoresist layer 241 is dry etching or wet etching, graphical at hard mask layer 240 and the first interlayer dielectric layer 232 surface-coated photoresist, expose the hard mask layer 240 of first step district 203 and the array area folded by first step district 203 201.
Please refer to Fig. 9 and Figure 10, Figure 10 is the end view of Fig. 9 on BB ' direction, with the second photoresist layer 242 with hard mask layer 240 for mask, dielectric layer 232 and the first polysilicon layer 233 between etching of first layer, and expose the second interlayer dielectric layer 234, described first polysilicon layer 233 is the polysilicon layer of most top layer in control grid layer 230, and described second interlayer dielectric layer 234 is the interlayer dielectric layer of the first interlayer dielectric layer 232 times one decks.
Described etching technics is reactive ion etching method, the advantage that reactive ion is sent out is that anisotropy and selectivity are good, can form smooth step, do not damage hard mask layer 240 and the second photoresist layer 242, the etching gas etching the first polysilicon layer 233 is Cl simultaneously
2, HBr or Cl
2with the mist of HBr, because the first interlayer dielectric layer 232 is different from the material of hard mask layer 240, therefore the first interlayer dielectric layer 232 and the first polysilicon layer 233 have selectivity respectively for hard mask layer 240, polysilicon layer is 5 ~ 200 for the etching selection ratio of hard mask layer 240, interlayer dielectric layer is 1 ~ 50 for the etching selection ratio of hard mask layer 240, while so then thoroughly can removing the first interlayer dielectric layer 232 and the first polysilicon layer 233, on hard mask layer 240 without impact.
Please refer to Fig. 9 and Figure 11, Figure 11 is the end view of Fig. 9 on BB ' direction, thinning second photoresist layer 242 also exposes the second step district 204 of the first interlayer dielectric layer 232 in stepped region 202, and described second step district 204 is region corresponding on upper level step place first, first step district 203 interlayer dielectric layer 232.
Described thinning second photoresist layer 242 technique is dry etching, dry etching can make the second photoresist layer 242 accurately be thinned to expose second step district 204, and the gas of described dry etching is one or more mixing in inert gas, nitrogen, oxygen, fluorocarbon gases and hydrocarbon gas.
Please refer to Figure 12 and Figure 13, Figure 13 is the end view of Figure 12 on BB ' direction, with the second photoresist layer 242 with hard mask layer 240 for mask, dielectric layer 232 and the first polysilicon layer 233 between second step district 204 etching of first layer, dielectric layer 234 and the second polysilicon layer 235 between first step district 203 etching of second layer, described second polysilicon layer 235 is the polysilicon layer of the first polysilicon layer 233 times one decks.
Described etching technics is reactive ion etching method, and the technique of concrete reactive ion etching method is consistent with the present embodiment Fig. 9 and Figure 10, and is well known to those skilled in the art, and therefore not to repeat here.
Please refer to Figure 12 and Figure 14, Figure 14 is the end view of Figure 12 on BB ' direction, thinning second photoresist layer 242 also exposes the 3rd stepped region 205 of the first interlayer dielectric layer 234, and described 3rd stepped region 205 is region corresponding on upper level step place first, second step district 204 interlayer dielectric layer 232.
The technique of described thinning second photoresist layer 242 is consistent with described in the present embodiment Fig. 9 and Figure 11, and is well known to those skilled in the art, and therefore not to repeat here.
Please refer to Figure 15 and Figure 16, Figure 16 is the end view of Figure 15 on BB ' direction, repeatedly state etching interlayer dielectric layer and polysilicon layer, and thinning second photoresist layer 242 (please refer to Figure 14) several times, make the size of some layers of polysilicon layer in the control grid layer 230 of stepped region 202, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder from the bottom to top, the steps at different levels projection arrangement on semiconductor substrate 200 of described ladder is linear, and described linear parallel with the border that stepped region 202 contacts with array area 201.
The technique of etching interlayer dielectric layer and polysilicon layer is reactive ion etching method, often remove one deck interlayer dielectric layer and one deck polysilicon layer, then with the second photoresist layer 242 of the thinning certain size of dry etching, several times are until the second photoresist layer 242 is completely removed repeatedly, and the ladder that the polysilicon layer in control grid layer 230 is formed in stepped region 202, each layer step relative to lower one deck step reduce measure-alike.
Please refer to Figure 17 and Figure 18, Figure 18 is the end view of Figure 17 on BB ' direction, remove hard mask layer 240 (please refer to Figure 15), control grid layer 230 surface in stepped region 202 forms insulating barrier 250, in described insulating barrier 250, form the some attachment plugs 251 running through its thickness be connected respectively with some layers of polysilicon layer, form some connecting lines 252 at insulating barrier 250 and attachment plug 251 surface, described some connecting lines 252 select grid 220 to be connected respectively by attachment plug 251 with some polysilicon layers and bottom.
The technique of described removal hard mask layer 240 is dry etching or wet etching.
The material of described insulating barrier 250 is silica or silicon nitride, and the material of described articulamentum 252 is polysilicon, and the formation process of insulating barrier 250 and articulamentum 252 is sedimentation, preferably chemical vapour deposition technique.
The formation process of described attachment plug 251 is: at described insulating barrier 250 surface-coated photoresist, and exposure imaging is graphical, take photoresist as mask etching insulating barrier 250, form the opening of some attachment plugs 251, and expose the surface of the polysilicon layer that each attachment plug 251 connects, fill polysilicon in said opening, form attachment plug 251.
Further, please refer to Figure 17, in the formation method of the memory cell of flash memory, also comprise step: control grid layer 230 surface in array area 201 forms some top layers and selects grid 260, select grid 260 surface to form top layer dielectric layer 261 at described top layer; Formed and run through the top layer selection connector array 262 that top layer selects grid 260 and top layer dielectric layer 261 thickness, described top layer selects connector array 262 and memory connector array 231 one_to_one corresponding; Form some bit lines 263 on described top layer dielectric layer 261 surface, described bit line 263 and top layer select connector array 262 to be connected.
Described some top layers select grid 260, the same row's top layer connected on first direction selects the connector in connector array 262, material is polysilicon, formation process is form top layer at control grid layer 230 surface deposition to select gate layer (not shown), gate layer surface-coated photoresist is selected at described top layer, and exposure imaging is graphical, select gate layer using photoresist as mask etching top layer, form top layer and select grid 260.
Select grid 260 surface deposition top layer dielectric layer 261 at top layer, the material of described top layer dielectric layer 261 is silica or silicon nitride, and described top layer dielectric layer 261 surface flushes with insulating barrier 250 surface.
Described top layer selects the formation process of connector array 262 to select the formation process of connector array 222 consistent with bottom described in Fig. 4, and is well known to those skilled in the art, and therefore not to repeat here.
Described some bit lines 263 same row's top layer connected in second direction selects the connector in connector array 262, described second direction and first direction perpendicular, bit line 263 surface flushes with the surface of articulamentum 252, formation process selects the technique of grid 260 identical with formation top layer, and be well known to those skilled in the art, therefore not to repeat here.
The formation method of the flash memory control grid layer of the embodiment of the present invention, by repeatedly etching interlayer dielectric layer and polysilicon layer, and thinning second photoresist layer 242, make the some polysilicon layers in control grid layer 230, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder from the bottom to top, the steps at different levels projection arrangement on semiconductor substrate 200 of described ladder is linear, and it is described linear parallel with the border that stepped region 202 contacts with array area 201, described formation method can with less processing step, accurate forming station scalariform, there is simple process, the advantage that shaping accuracy is high.
The memory cell of the flash memory that the formation method of the memory cell of the present embodiment flash memory is formed, please refer to Figure 17 and Figure 18, Figure 18 is the end view of Figure 17 on BB ' direction, comprising:
Semiconductor substrate 200, described Semiconductor substrate 200 comprises array area 201 and stepped region 202, and described stepped region 202 is in both sides, array area 201;
Be positioned at the separator 210 on Semiconductor substrate 200 surface; Grid 220 selected by the bottom being positioned at separator 210 surface; Be positioned at the underlying dielectric layer 221 that grid 220 surface selected by bottom; Grid connector array 222 selected by the bottom running through the separator 210 of described array area 201, bottom selection grid 220 and underlying dielectric layer 221;
Be positioned at the control grid layer 230 on described underlying dielectric layer 221 and bottom selection grid connector array 222 surface, described control grid layer 230 also comprises: some layers of polysilicon layer and the interlayer dielectric layer being positioned at each layer polysilicon layer surface, wherein, run through the memory connector array 231 of control grid layer 230 thickness of described array area 201, described memory connector array 231 selects connector array 222 one_to_one corresponding with bottom;
Be positioned at the size of some layers of polysilicon layer of the control grid layer 230 of stepped region 202, the polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder;
Be positioned at the insulating barrier 250 on control grid layer 230 surface of stepped region 202, be positioned at some connecting lines 252 on described insulating barrier 250 surface, described some connecting lines 252 are connected with some layers of polysilicon layer in control grid layer 230 respectively respectively by running through described some attachment plugs 251 of insulating barrier 250 thickness;
The memory cell of described flash memory also comprises: the some top layers being positioned at control grid layer 230 surface of described array area 201 select grid 260, be positioned at the top layer dielectric layer 261 that described top layer selects grid 260 surface, and be positioned at some bit lines 263 on described top layer dielectric layer 261 surface; The top layer running through described top layer dielectric layer 261 thickness selects connector array 262, and described top layer selects connector array 262 and memory connector 231 array one_to_one corresponding.
Same row's top layer that described some top layers select grid 260 to connect respectively on first direction selects connector array 262, described some bit lines 263 same row's top layer connected in second direction selects the connector in connector array 262, and described second direction and first direction perpendicular.
Please refer to Figure 19, the memory cell that Figure 19 is flash memory shown in Figure 17 is along CC ' direction, ignore the vertical view of some interlayer dielectric layers in insulating barrier 250, memory connector array 231 and control grid layer 230, the steps at different levels projection arrangement on semiconductor substrate 200 of described ladder is linear, and described linear parallel with the border that stepped region 202 contacts with array area 201.
It should be noted that, the size of some layers of polysilicon layer in the control grid layer 230 of described stepped region 202, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases, and every one deck polysilicon layer relatively reduce with lower one deck polysilicon layer measure-alike.
The projection arrangement on a semiconductor substrate of described some attachment plugs 251 is linear, and described linear parallel with the border that stepped region 202 contacts with array area 201.
Please refer to Figure 20, for the equivalent circuit diagram of the memory cell of embodiment of the present invention flash memory, because some bit lines 263 and some top layers select grid 260 mutually vertical, when giving a bit line 263 and a certain bias voltage of top layer selection grid 260, then this bit line 263 and this top layer select grid 260 to have selected connector in a connector array, and this connector from top to bottom comprises: top layer is selected connector, remembered connector and bottom selection connector; Select grid 220 to add another bias voltage at bottom, then form bias current in this connector; Now when giving a certain polysilicon layer in control grid layer 230 certain bias voltage, then by the polysilicon layer in this control grid layer 230, the connector chosen is controlled, the function achieving reading, write and wipe.
The memory cell of the flash memory that embodiments of the invention provide, while not changing the stacked structure of some layers of polysilicon layer in control grid layer in prior art, by making some layers of polysilicon layer in the control grid layer 230 on the stepped region 202 of Semiconductor substrate 200, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder, the steps at different levels projection arrangement on semiconductor substrate 200 of described ladder is linear, and it is described linear parallel with the sideline that stepped region 202 contacts with array area 201, solve in the BiCS structure of existing control grid layer, the space waste problem of control grid layer on the stepped region of Semiconductor substrate.Make, while retaining the polysilicon layer multilayer lamination structure in control grid layer 230, to reduce the area of control grid layer 230, thus improve the bit density of flash memory, and reduce the position cost of flash memory.
In sum, the memory cell of the flash memory that embodiments of the invention provide, while the stacked structure not changing some layers of polysilicon layer in prior art in control grid layer, some layers of polysilicon layer in control grid layer on stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and it is described linear parallel with the sideline that array area contacts with stepped region, can solve in the BiCS structure of existing control grid layer, the space waste problem of control grid layer on the stepped region of Semiconductor substrate.Make, while retaining the polysilicon layer multilayer lamination structure in control grid layer, to reduce the area of control grid layer, thus improve the bit density of flash memory, and reduce the position cost of flash memory.
The memory cell formation method of the flash memory that embodiments of the invention provide, by thinning second photoresist layer repeatedly and etching interlayer dielectric layer and polysilicon layer, make polysilicon layer in control grid layer at stepped region forming station scalariform, described formation method can with less processing step, accurate forming station scalariform, there is simple process, the advantage that shaping accuracy is high.
Further, the formation method of the flash memory control grid layer of embodiments of the invention is passed through repeatedly thinning second photoresist layer and etches interlayer dielectric layer and polysilicon layer, make polysilicon layer in control grid layer at stepped region forming station scalariform, described formation method can with less processing step, accurate forming station scalariform, there is simple process, the advantage that shaping accuracy is high.
Although the embodiment of the present invention is described above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (18)
1. a memory cell for flash memory, is characterized in that, comprising:
Semiconductor substrate, described Semiconductor substrate comprises array area and stepped region, and described stepped region is in both sides, array area; Be positioned at the separator of semiconductor substrate surface; Grid selected by the bottom being positioned at insulation surface; Be positioned at the underlying dielectric layer that grid surface selected by bottom;
Described separator comprises oxide layer, catches charge layer and barrier oxide layer, described in catch charge layer be positioned at described oxide layer surface, catch charge layer surface described in described barrier oxide layer is positioned at, described in catch charge layer for store electrons;
The material of described oxide layer is silica, described in catch charge layer material be silicon nitride, the material oxidation silicon of described barrier oxide layer or aluminium oxide;
Grid connector array selected by the bottom running through the separator of described array area, bottom selection grid and underlying dielectric layer thickness;
Be positioned at the control grid layer of described underlying dielectric layer and bottom selection grid connector array surface, described control grid layer also comprises: some layers of polysilicon layer and the interlayer dielectric layer being positioned at each layer polysilicon layer surface, wherein, run through the memory connector array of the control grid layer thickness of described array area, and connector array one_to_one corresponding selected by described memory connector array and bottom;
Be positioned at the size of some layers of polysilicon layer of the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region;
Be positioned at the insulating barrier on the control grid layer surface of described stepped region, be positioned at some connecting lines of described surface of insulating layer, described some connecting lines are connected with some layers of polysilicon layer in control grid layer respectively respectively by running through some attachment plugs of described thickness of insulating layer, the projection arrangement on a semiconductor substrate of described some attachment plugs is linear, and described linear parallel with the border that array area contacts with stepped region.
2. the memory cell of flash memory according to claim 1, is characterized in that, also comprise: the some top layers being positioned at the control grid layer surface of described array area select grid; Be positioned at the top layer dielectric layer that some top layers select grid surface; Be positioned at some bit lines of top layer dielectric layer surface; The top layer running through described top layer dielectric layer and top layer selection grid thickness selects connector array, and described top layer selects connector array and memory connector array one_to_one corresponding, and is connected with bit line.
3. the memory cell of flash memory according to claim 1, it is characterized in that, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.
4. the memory cell of flash memory according to claim 3, it is characterized in that, described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
5. the memory cell of flash memory according to claim 1, it is characterized in that, the size of some layers of polysilicon layer in the control grid layer of described stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases, and every one deck polysilicon layer relatively reduce with lower one deck polysilicon layer measure-alike.
6. a formation method for the memory cell of flash memory, is characterized in that, comprising:
There is provided Semiconductor substrate, semiconductor substrate surface has separator successively, bottom selects grid, underlying dielectric layer and control grid layer, and described Semiconductor substrate comprises array area and stepped region, and described stepped region is positioned at both sides, array area; Grid connector array selected by the bottom running through the separator of described array area, bottom selection grid and underlying dielectric layer thickness; Described control grid layer comprises: some layers of polysilicon layer and the interlayer dielectric layer being positioned at each layer polysilicon layer surface, and wherein, run through the memory connector array of the control grid layer thickness of described array area, connector array one_to_one corresponding selected by described memory connector array and bottom;
Described separator successively by oxide layer, catch charge layer and barrier oxide layer is stacking forms, described in catch charge layer for store electrons;
The material of described oxide layer is silica, described in catch charge layer material be silicon nitride, the material oxidation silicon of described barrier oxide layer or aluminium oxide;
Hard mask layer is formed on control grid layer surface;
The first photoresist layer is formed, with the first photoresist layer for the control grid layer beyond mask removal array area and stepped region and hard mask layer on described hard mask layer surface;
Remove the first photoresist layer of stepped region and hard mask layer till exposing the first interlayer dielectric layer, described first interlayer dielectric layer is the interlayer dielectric layer of most top layer in control grid layer, removes the first photoresist layer of array area;
Between hard mask layer and ground floor, dielectric layer surface forms the second photoresist layer;
Repeatedly etch interlayer dielectric layer and polysilicon layer and thinning second photoresist layer several times, make the size of some layers of polysilicon layer in the control grid layer of stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases formation ladder from the bottom to top, the steps at different levels projection arrangement on a semiconductor substrate of described ladder is linear, and described linear parallel with the border that array area contacts with stepped region;
Control grid layer surface in stepped region forms insulating barrier, forms the some attachment plugs running through described thickness of insulating layer, is connected respectively with some layers of polysilicon layer;
Form some connecting lines at insulating barrier and attachment plug surface, described some connecting lines are connected with some polysilicon layers respectively by some attachment plugs.
7. the formation method of the memory cell of flash memory according to claim 6, is characterized in that, also comprise step: the control grid layer surface in array area forms some top layers and selects grid, selects grid surface to form top layer dielectric layer at some top layers; Formed and run through the top layer selection connector array that described top layer selects grid and top layer thickness of dielectric layers, described top layer selects connector array and memory connector array one_to_one corresponding; Form some bit lines at described top layer dielectric layer surface, described bit line and top layer select connector array to be connected.
8. the formation method of the memory cell of flash memory according to claim 6, it is characterized in that, described between hard mask layer and ground floor dielectric layer surface form the second photoresist layer, and repeatedly etch interlayer dielectric layer and polysilicon layer and the method for thinning second photoresist layer several times, also comprise step:
Between hard mask layer and ground floor, dielectric layer surface forms the second photoresist layer, and exposes the first step district in stepped region, and described first step district is the region in stepped region corresponding to bottom step;
With the second photoresist layer and hard mask layer for mask, dielectric layer and the first polysilicon layer between etching of first layer, and expose the second interlayer dielectric layer, described first polysilicon layer is the polysilicon layer of most top layer in control grid layer, and described second interlayer dielectric layer is the interlayer dielectric layer of one deck under the first interlayer dielectric layer;
Thinning second photoresist layer also exposes the second step district of the first interlayer dielectric layer in stepped region, and described second step district is region corresponding on upper level step place first interlayer dielectric layer of bottom step;
With the second photoresist layer and hard mask layer for mask, dielectric layer and the first polysilicon layer between second step district etching of first layer, dielectric layer and the second polysilicon layer between first step district etching of second layer, described second polysilicon layer is the polysilicon layer of one deck under the first polysilicon layer;
Thinning second photoresist layer also exposes the 3rd stepped region of the first interlayer dielectric layer, and described 3rd stepped region is region corresponding on the interlayer dielectric layer of upper level step place first, second step district.
9. the formation method of the memory cell of flash memory according to claim 6, it is characterized in that, the technique of described thinning photoresist is dry etching.
10. the formation method of the memory cell of flash memory according to claim 6, it is characterized in that, the technique of described etching interlayer dielectric layer and polysilicon layer is reactive ion etching method.
The formation method of 11. memory cell of flash memory according to claim 10, it is characterized in that, described interlayer dielectric layer is 1 ~ 50 for the etching selection ratio of hard mask layer, and described polysilicon layer is 5 ~ 200 for the etching selection ratio of hard mask layer.
The formation method of 12. memory cell of flash memory according to claim 6, is characterized in that, described hard mask layer is that one or more in insulation material layer, metal level or amorphous carbon layer overlap.
13. according to the formation method of the memory cell of flash memory described in claim 12, and it is characterized in that, described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
14. according to the formation method of the memory cell of flash memory described in claim 12, and it is characterized in that, the material of described metal level is one or more the alloy in copper, tungsten, aluminium.
The formation method of 15. memory cell of flash memory according to claim 6, it is characterized in that, described interlayer dielectric layer is insulation material layer or amorphous carbon layer.
16. according to the formation method of the memory cell of flash memory described in claim 15, and it is characterized in that, described insulation material layer is the multiple-level stack of silicon oxide layer, silicon nitride layer or silica and silicon nitride.
The formation method of 17. memory cell of flash memory according to claim 6, it is characterized in that, described hard mask layer is not identical with the material of interlayer dielectric layer.
The formation method of 18. memory cell of flash memory according to claim 6, it is characterized in that, the size of some layers of polysilicon layer in the control grid layer of described stepped region, polysilicon layer from the polysilicon layer of the bottom to most top layer successively successively decreases, and every one deck polysilicon layer relatively reduce with lower one deck polysilicon layer measure-alike.
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