CN103257942B - A kind of method of SOC (system on a chip) shared bus request process and device - Google Patents
A kind of method of SOC (system on a chip) shared bus request process and device Download PDFInfo
- Publication number
- CN103257942B CN103257942B CN201310103640.0A CN201310103640A CN103257942B CN 103257942 B CN103257942 B CN 103257942B CN 201310103640 A CN201310103640 A CN 201310103640A CN 103257942 B CN103257942 B CN 103257942B
- Authority
- CN
- China
- Prior art keywords
- bus
- primary module
- bus request
- request
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The invention provides a kind of method and device of SOC (system on a chip) shared bus request process, when wherein said method comprises the bus request receiving one or more primary module, obtain the bus statistical information of described primary module; Identify the first primary module, the first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value; Calculate the processing priority of primary module, successively the bus request of primary module is processed according to processing priority; When process the first primary module, judge the treatment state of bus, described treatment state comprises busy state; When the treatment state of bus is busy state, the process data volume of the bus request of the first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing, wherein N is positive integer.The present invention can utilize shared bus to greatest extent, realizes the efficient data communication of modules.
Description
Technical field
The present invention relates to the SOC (system on a chip) communications field, particularly relate to a kind of method of SOC (system on a chip) shared bus request process, and, a kind of device of SOC (system on a chip) shared bus request process.
Background technology
Along with the raising of the Automation Design ability and IC manufacturing level, particularly in the sub-micro epoch, many functional modules can be integrated on a phy chip by on-chip interconnect, thus form one piece of complete SOC (system on a chip), i.e. SOC system.
When SOC (system on a chip) modules all has unified interface, the interconnection of intermodule just becomes simpler.At present, in the interconnection structure between SOC (system on a chip) module, what the most extensively adopt is shared bus.
In the SOC (system on a chip) of shared bus, arbitration algorithm plays an important role for the impact of system performance, particularly in the limited system of bus bandwidth.Bus arbitration mode has two kinds: distributed arbitration program and centralized arbitration.But at present, most SOC (system on a chip) adopts centralized arbitration mode.
In concentrated arbitration mode, arbitration modules independent of each primary module, the request of passive reception primary module.In traditional concentrated arbitration mode, arbitration modules is independent of each primary module, and the request of passive reception primary module, lacks the mutual of primary module and concentrated arbitration mode, the frequency that primary module sends request and the data volume of once asking good by software configured in advance, centre be difficult to amendment.When a certain primary module request msg quantity is excessive, be easy to cause single module holding time in bus long cause other module can not in time respective request event occur.
Therefore, patented claim of the present invention proposes a kind of SOC (system on a chip) shared bus request processing mechanism, can utilize shared bus to greatest extent, realizes the efficient data communication of modules.
Summary of the invention
The invention provides a kind of method of SOC (system on a chip) shared bus request process, utilize shared bus to greatest extent to solve, realize the problem of the efficient data communication of modules.
Accordingly, present invention also offers a kind of device of SOC (system on a chip) shared bus request process, in order to ensure said method application in practice.
In order to solve the problem, the invention discloses a kind of method of SOC (system on a chip) shared bus request process, comprising:
When receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
Identify the first primary module, described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
According to the processing priority of one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, successively the bus request of described one or more primary module is processed according to described processing priority;
When processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state;
When the treatment state of bus is busy state, the process data volume of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
Preferably, described bus treatment state comprises Idle state, and described method also comprises:
When the treatment state of bus is Idle state, the process data volume of the bus request of described first primary module of disposable process.
Preferably, the bus statistical information of described one or more primary module is calculated by the statistic logic of primary module.
Preferably, described method also comprises:
The processing priority of described one or more primary module is recalculated every preset time period;
The bus request of described one or more primary module is processed successively according to the processing priority recalculated.
Preferably, described method also comprises:
When the treatment state of bus is busy state, process after the bus request of time primary module, the bus request inserting the primary module of second priority level processes.
Preferably, the treatment state of described bus, judges in the following way:
If detect, multiple primary module sends bus request, then the treatment state of described bus is busy state;
Only have a primary module to send bus request if detect, then the treatment state of described bus is Idle state.
The invention also discloses a kind of device of SOC (system on a chip) shared bus request process, comprising:
Bus statistical information acquisition unit, for when receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
First primary module recognition unit, for identifying the first primary module, described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
Priority calculation unit, for the processing priority according to one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, successively the bus request of described one or more primary module is processed according to described processing priority;
Treatment state judging unit, for when processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state;
Data batch treatment unit, for when the treatment state of bus is busy state, the process data volume of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, and a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
Preferably, described bus treatment state comprises Idle state, and described device also comprises:
Data unify processing unit, for when the treatment state of bus is Idle state, and the process data volume of the bus request of described first primary module of disposable process.
Preferably, the bus statistical information of the one or more primary module of described device is calculated by the statistic logic of primary module.
Preferably, described device also comprises:
Priority recalculates unit, for recalculating the processing priority of described one or more primary module every preset time period, processes the bus request of described one or more primary module according to the processing priority recalculated successively.
Preferably, described device also comprises:
Second priority level plug-in unit, for when the treatment state of bus is busy state, process after the bus request of time primary module, the bus request inserting the primary module of second priority level processes.
Preferably, the treatment state of described bus, is judged in the following ways by treatment state judging unit:
If detect, multiple primary module sends bus request, then the treatment state of described bus is busy state;
Only have a primary module to send bus request if detect, then the treatment state of described bus is Idle state.
Compared with prior art, the present invention includes following advantage:
First, in the embodiment of the present invention, each primary module has the bandwidth request control statistic logic of himself, the bus acknowledge situation of dynamic monitoring self, calculates the bus statistical information of this module, provides reliable data basis for bus arbiter module carries out bus arbitration.
Second, in the embodiment of the present invention, bus arbiter module also possesses bandwidth request control statistic logic, can according to the bus statistical information of each primary module, by configuring the register of primary module, the priority of dynamic conditioning primary module, carries out reasonable distribution by bus resource by the bus requirements of each primary module.
3rd, the time that the embodiment of the present invention can shorten according to the treatment state of bus or prolongation primary module bus request takies and/or process data volume, improve bus utilization to greatest extent, improve the work efficiency of primary module, optimize SOC system performance.
Accompanying drawing explanation
Fig. 1 shows the flow chart of steps of the embodiment of the method 1 of a kind of SOC (system on a chip) shared bus of the present invention request process;
Fig. 2 shows the flow chart of steps of the embodiment of the method 2 of a kind of SOC (system on a chip) shared bus of the present invention request process;
Fig. 3 shows the structured flowchart of the device embodiment of a kind of SOC (system on a chip) shared bus of the present invention request process.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
With reference to Fig. 1, show the flow chart of steps of the embodiment of the method 1 of a kind of SOC (system on a chip) shared bus of the present invention request process, can comprise the following steps:
Step 101, when receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
Specifically, in the SOC (system on a chip) of shared bus, can a statistic logic be added to respectively each primary module and concentrated arbitration modules, the statistic logic of primary module can be monitored in real time and add up the bus statistical information of own module, described bus statistical information can comprise the bus holding time of primary module, process data volume, bus acknowledge stand-by period and bus request frequency etc., when concentrated arbitration modules receives the bus request of one or more primary module, just can by the bus statistical information concentrating the statistic logic of arbitration modules to obtain the one or more primary modules sending bus request.Thus provide reliable data basis for concentrating arbitration modules to carry out bus arbitration.
Step 102, identifies the first primary module, and described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
In embodiments of the present invention, arbitration modules is concentrated to take the bus statistical information of each primary module of bus according to application, one by one the bus holding time of primary module can be compared with the first predetermined threshold value, and/or process data volume is compared with the second predetermined threshold value, identify bus holding time be greater than the first predetermined threshold value and/or process data volume be greater than the primary module of the second predetermined threshold value as the first primary module.
Step 103, according to the processing priority of one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, processes the bus request of described one or more primary module successively according to described processing priority;
The application embodiment of the present invention, after multiple primary module sends bus request, the information that concentrated arbitration modules can provide according to statistic logic, according to intrinsic arbitration algorithm, calculates the sequencing of bus acknowledge master requests and processes one by one.
In embodiments of the present invention, concentrated arbitration modules can collect the bus statistical information of each primary module, and according to each primary module for the demand intensity of bus and the time of the every secondary response of bus etc. parameter, the priority of each primary module is regulated, namely realize the dynamic surveillance to primary module priority and regulation and control, thus reasonably utilize bus bandwidth.
Step 104, when processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state;
In specific implementation, first primary module bus holding time is longer and/or process data volume is larger, before to its process, concentrated arbitration modules can according to the quantity of the primary module of the current bus request received, first judge that whether bus is busy, then according to the actual conditions of bus, the first primary module is processed.
Step 105, when the treatment state of bus is busy state, is divided into N one's share of expenses for a joint undertaking data volume by the process data volume of the bus request of described first primary module, and a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
In inventive embodiments, when concentrating arbitration modules to judge that bus is in busy state, hardware protocol feedack can be adopted in conjunction with primary module, under the prerequisite of performance not affecting primary module, configure the register of described first primary module, the single treatment data volume of described first primary module be divided into many numbers according to repeatedly processing, thus the time that shortening the first primary module bus takies.
In order to make those skilled in the art better understand the present invention, below by an instantiation, step 105 is described:
1, A primary module has 1000 data to transmit;
2, B primary module also has 1000 data to transmit;
3, concentrate arbitration modules to pass through the statistic logic of A primary module and B primary module inside, know that the demand of A and B is all larger;
4, by calculating the priority of A primary module higher than B primary module;
5, by concentrating the statistic logic of arbitration modules to judge that bus is in busy state;
6, configure the register of A primary module, make A primary module can send the order once transmitting 100 data;
7, configure the register of B primary module, make B primary module can send the order once transmitting 50 data;
8, A primary module sends application, 10 times can by data end of transmission;
9, B primary module sends application, 20 times can by data end of transmission.
Embodiments of the invention can calculate the priority of each primary module for the demand intensity of bus and the time of the every secondary response of bus etc. parameter according to each primary module, bus resource is reasonably distributed to each primary module, thus improves the work efficiency of primary module.And, the embodiment of the present invention can according to the treatment state of bus, shorten a bus holding time and/or the process data volume of primary module, effective solution primary module bus holding time is long and/or process the excessive problem causing other primary module to can not get bus resource of data volume, improve the utilization factor of bus, and the work efficiency of SOC system can be improve on the whole, reach the effect optimizing SOC system.
With reference to Fig. 2, show the flow chart of steps of the embodiment of the method 2 of a kind of SOC (system on a chip) shared bus of the present invention request process, can comprise the following steps:
Step 201, when receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
In embodiments of the present invention, the bus statistical information of described one or more primary module is calculated by the statistic logic of primary module.
Step 202, identifies the first primary module, and described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
Step 203, according to the processing priority of one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, processes the bus request of described one or more primary module successively according to described processing priority;
Step 204, each preset time period recalculates the processing priority of described one or more primary module, processes the bus request of described one or more primary module according to the processing priority recalculated successively;
The application embodiment of the present invention, every a time period, concentrated arbitration modules can according to the bus statistical information of intrinsic algorithm with each primary module, the register of primary module is configured, recalculate the priority of each primary module and according to the described priority recalculated, primary module processed, realizing the priority of dynamic conditioning primary module.
Step 205, when processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state and Idle state;
In one preferred embodiment of the invention, the treatment state of described bus can judge in the following way:
If detect, multiple primary module sends bus request, then the treatment state of described bus is busy state;
Only have a primary module to send bus request if detect, then the treatment state of described bus is Idle state.
Step 206, when the treatment state of bus is busy state, is divided into N one's share of expenses for a joint undertaking data volume by the process data volume of the bus request of described first primary module, a subdata amount of each bus request alignment processing of described primary module, and wherein N is positive integer;
Step 207, processes after the bus request of time primary module, and the bus request inserting the primary module of second priority level processes;
In specific implementation, when bus is in busy state, suitable is divided into repeatedly request high priority primary module bus request, and the primary module of lower priority just can obtain certain bus resource in the gap of the primary module bus request of process high priority.
In order to make those skilled in the art better understand the present invention, below by an instantiation, step 207 is described:
1, A primary module has 1000 data to transmit;
2, B primary module also has 1000 data to transmit;
3, the bandwidth request of primary module inside controls the demand of statistic logic display A primary module and B primary module all often, and the bandwidth request in arbitration modules controls statistic logic and finds that now bus is busier, but the priority of A, B primary module is higher;
4, configure the register of A primary module, notice A primary module can send the order once transmitting 100 data, 10 times can by data end of transmission;
5, configure the register of B primary module, notice B primary module can send the order once transmitting 50 data, 20 times can by data end of transmission;
6, in the process of A, B primary module transmission data, the priority ratio of A is higher, under same judgement, A primary module first can obtain bus acknowledge, but after A primary module is once transmitted, if 100 of second batch data are also not ready for, so B primary module just can also transmit oneself partial data by plug hole.
Step 208, when the treatment state of bus is Idle state, the process data volume of the bus request of described first primary module of disposable process.
Specifically, when bus is in Idle state, the register of primary module can be configured, make primary module once can send the bus application of comparing big data quantity, and respond its bus application.So just can shorten the working time of described primary module, improve the work efficiency of primary module.
In order to make those skilled in the art better understand the present invention, below by an instantiation, step 208 is described:
1, A primary module has 1000 data to transmit;
2, the bandwidth request of primary module inside controls the demand of statistic logic display A often, and the bandwidth request in arbitration modules controls statistic logic and finds that now bus is not in a hurry;
3, configure the register of A primary module, notice A primary module can send the order once transmitting 1000 data;
4, A primary module sends application, once can by data end of transmission;
5, in the process of described A primary module 1000 number of transmission, because bus is occupied, other any application all can not obtain corresponding.
Usual primary module is all IP that one by one can be multiplexing, this IP generally once applies for that the demand of bus can by register configuration, this configuration is static traditionally, if and had the dynamic arbitration schemes of the embodiment of the present invention, just can be configured it dynamically, like this when bus free, configure this register, allow the single job time of primary module longer, and in bus busy, allow the single job of primary module shorter, thus realize allowing other primary module insert order.
The present embodiment can regulate the priority of each primary module dynamically, and according to the virtual condition of bus, primary module bus application holding time and/or process data volume is shortened when bus is in busy state, allow each primary module can obtain certain bus resource, extend primary module bus application holding time and/or process data volume when bus is in Idle state, the work efficiency of this primary module can be improved.
With reference to Fig. 3, show the structured flowchart of the device embodiment of a kind of SOC (system on a chip) shared bus of the present invention request process, can comprise with lower module:
Bus statistical information acquisition unit 301, for when receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
First primary module recognition unit 302, for identifying the first primary module, described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
Priority calculation unit 303, for the processing priority according to one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, successively the bus request of described one or more primary module is processed according to described processing priority;
Priority recalculates unit 304, recalculates the processing priority of described one or more primary module for each preset time period, processes the bus request of described one or more primary module according to the processing priority recalculated successively;
Treatment state judging unit 305, for when processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state and Idle state;
In one preferred embodiment of the invention, the treatment state of described bus can be judged in the following way by treatment state judging unit:
If detect, multiple primary module sends bus request, then the treatment state of described bus is busy state;
Only have a primary module to send bus request if detect, then the treatment state of described bus is Idle state.
Data batch treatment unit 306, for when the treatment state of bus is busy state, the process data volume of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer;
Second priority level plug-in unit 307, for the treatment of complete after the bus request of time primary module, the bus request inserting the primary module of second priority level processes;
Data unify processing unit 308, for when the treatment state of bus is Idle state, and the process data volume of the bus request of described first primary module of disposable process.
For device embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.For device embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code.
The present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, equipment (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing device produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be loaded in computing machine or other programmable data processing device, make on computing machine or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computing machine or other programmable devices is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Finally, also it should be noted that, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Above the method for a kind of SOC (system on a chip) shared bus request process provided by the present invention and device are described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a method for SOC (system on a chip) shared bus request process, is characterized in that, comprising:
When receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
Identify the first primary module, described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
According to the processing priority of one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, successively the bus request of described one or more primary module is processed according to described processing priority;
When processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state;
When the treatment state of bus is busy state, the process data volume of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer;
When the treatment state of bus is busy state, process after the bus request of time primary module, the bus request inserting the primary module of second priority level processes.
2. method according to claim 1, is characterized in that, described bus treatment state comprises Idle state, and described method also comprises:
When the treatment state of bus is Idle state, the process data volume of the bus request of described first primary module of disposable process.
3. method according to claim 1 and 2, is characterized in that, the bus statistical information of described one or more primary module is calculated by the statistic logic of primary module.
4. method according to claim 1, is characterized in that, also comprises:
The processing priority of described one or more primary module is recalculated every preset time period;
The bus request of described one or more primary module is processed successively according to the processing priority recalculated.
5. method according to claim 1 and 2, is characterized in that, the treatment state of described bus, judges in the following way:
If detect, multiple primary module sends bus request, then the treatment state of described bus is busy state;
Only have a primary module to send bus request if detect, then the treatment state of described bus is Idle state.
6. a device for SOC (system on a chip) shared bus request process, is characterized in that, comprising:
Bus statistical information acquisition unit, for when receiving the bus request of one or more primary module, obtain the bus statistical information of described one or more primary module, described bus statistical information comprises bus holding time, process data volume, bus acknowledge stand-by period and bus request frequency;
First primary module recognition unit, for identifying the first primary module, described first primary module is that bus holding time is greater than the first predetermined threshold value and/or process data volume is greater than the primary module of the second predetermined threshold value;
Priority calculation unit, for the processing priority according to one or more primary module described in described bus acknowledge stand-by period and bus request frequency computation part, successively the bus request of described one or more primary module is processed according to described processing priority;
Treatment state judging unit, for when processing described first primary module, judge the treatment state of bus, described treatment state comprises busy state;
Data batch treatment unit, for when the treatment state of bus is busy state, the process data volume of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer;
Second priority level plug-in unit, for when the treatment state of bus is busy state, process after the bus request of time primary module, the bus request inserting the primary module of second priority level processes.
7. device according to claim 6, is characterized in that, described bus treatment state comprises Idle state, and described device also comprises:
Data unify processing unit, for when the treatment state of bus is Idle state, and the process data volume of the bus request of described first primary module of disposable process.
8. the device according to claim 6 or 7, is characterized in that, the bus statistical information of described one or more primary module is calculated by the statistic logic of primary module.
9. device according to claim 6, is characterized in that, also comprises:
Priority recalculates unit, for recalculating the processing priority of described one or more primary module every preset time period, processes the bus request of described one or more primary module according to the processing priority recalculated successively.
10. the device according to claim 6 or 7, is characterized in that, the treatment state of described bus, is judged in the following ways by treatment state judging unit:
If detect, multiple primary module sends bus request, then the treatment state of described bus is busy state;
Only have a primary module to send bus request if detect, then the treatment state of described bus is Idle state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310103640.0A CN103257942B (en) | 2013-03-27 | 2013-03-27 | A kind of method of SOC (system on a chip) shared bus request process and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310103640.0A CN103257942B (en) | 2013-03-27 | 2013-03-27 | A kind of method of SOC (system on a chip) shared bus request process and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103257942A CN103257942A (en) | 2013-08-21 |
| CN103257942B true CN103257942B (en) | 2015-12-02 |
Family
ID=48961872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310103640.0A Expired - Fee Related CN103257942B (en) | 2013-03-27 | 2013-03-27 | A kind of method of SOC (system on a chip) shared bus request process and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103257942B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103870404B (en) * | 2014-03-13 | 2016-09-14 | 武汉精测电子技术股份有限公司 | A kind of IIC criticizes command process control method |
| CN107844442A (en) * | 2016-09-19 | 2018-03-27 | 深圳市中兴微电子技术有限公司 | The referee method and device of request source response |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09160868A (en) * | 1995-12-11 | 1997-06-20 | Ricoh Co Ltd | Bus arbitration device and method therefor |
| JP2000132505A (en) * | 1998-10-27 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Bus access method and device therefor, and device and system using the bus access method and device |
| CN1282924A (en) * | 1999-07-29 | 2001-02-07 | 国际商业机器公司 | Enhanced bus orbitrator using variable priority and reasonableness |
| CN1507592A (en) * | 2001-06-23 | 2004-06-23 | Ħ��������˾ | System and method for controlling bus arbitration during cache memory burst cycles |
| CN1577304A (en) * | 2003-06-26 | 2005-02-09 | 三星电子株式会社 | Dynamic bus arbitration method and bus arbiter |
| CN1661579A (en) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
| CN101075220A (en) * | 2007-04-29 | 2007-11-21 | 北京中星微电子有限公司 | Simulator and method for bus arbitraction |
| CN101089833A (en) * | 2006-06-15 | 2007-12-19 | 索尼株式会社 | Information processing apparatus, method of same, and program for same |
| CN101510181A (en) * | 2009-03-19 | 2009-08-19 | 北京中星微电子有限公司 | Bus arbitration method and bus arbitration apparatus |
| WO2009147744A1 (en) * | 2008-06-06 | 2009-12-10 | 三菱電機株式会社 | Bus arbiter |
| CN101930417A (en) * | 2010-08-13 | 2010-12-29 | 北京飞利信科技股份有限公司 | Arbiter for serial data bus-based streaming media transmission system terminal equipment |
-
2013
- 2013-03-27 CN CN201310103640.0A patent/CN103257942B/en not_active Expired - Fee Related
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09160868A (en) * | 1995-12-11 | 1997-06-20 | Ricoh Co Ltd | Bus arbitration device and method therefor |
| JP2000132505A (en) * | 1998-10-27 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Bus access method and device therefor, and device and system using the bus access method and device |
| CN1282924A (en) * | 1999-07-29 | 2001-02-07 | 国际商业机器公司 | Enhanced bus orbitrator using variable priority and reasonableness |
| CN1507592A (en) * | 2001-06-23 | 2004-06-23 | Ħ��������˾ | System and method for controlling bus arbitration during cache memory burst cycles |
| CN1577304A (en) * | 2003-06-26 | 2005-02-09 | 三星电子株式会社 | Dynamic bus arbitration method and bus arbiter |
| CN1661579A (en) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
| CN101089833A (en) * | 2006-06-15 | 2007-12-19 | 索尼株式会社 | Information processing apparatus, method of same, and program for same |
| CN101075220A (en) * | 2007-04-29 | 2007-11-21 | 北京中星微电子有限公司 | Simulator and method for bus arbitraction |
| WO2009147744A1 (en) * | 2008-06-06 | 2009-12-10 | 三菱電機株式会社 | Bus arbiter |
| CN101510181A (en) * | 2009-03-19 | 2009-08-19 | 北京中星微电子有限公司 | Bus arbitration method and bus arbitration apparatus |
| CN101930417A (en) * | 2010-08-13 | 2010-12-29 | 北京飞利信科技股份有限公司 | Arbiter for serial data bus-based streaming media transmission system terminal equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103257942A (en) | 2013-08-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9477280B1 (en) | Specification for automatic power management of network-on-chip and system-on-chip | |
| US9684364B2 (en) | Technologies for out-of-band power-based task scheduling for data centers | |
| US20160378570A1 (en) | Techniques for Offloading Computational Tasks between Nodes | |
| US11206193B2 (en) | Method and system for provisioning resources in cloud computing | |
| US9641431B1 (en) | System and methods for utilization-based balancing of traffic to an information retrieval system | |
| US20200225724A1 (en) | Platform slicing of central processing unit (cpu) resources | |
| CN102664779B (en) | CAN bus data transmitting method | |
| CN109587072A (en) | Distributed system overall situation speed limiting system and method | |
| CN104503932A (en) | Method and system for judging master baseboard management controller of multi-mainboard server | |
| CN102811152B (en) | Method for realizing real-time transaction and data exchange of multiple main bus network communication | |
| CN109240822A (en) | The method, apparatus and storage medium and electronic equipment of application program elastic telescopic | |
| CN103257942B (en) | A kind of method of SOC (system on a chip) shared bus request process and device | |
| CN105022333A (en) | PLC system having a plurality of CPU modules and control method thereof | |
| CN109857190A (en) | A kind of clock signal processing method, device, equipment and readable storage medium storing program for executing | |
| CN105094944A (en) | Virtual machine migration method and apparatus | |
| CN104503885A (en) | Timing door watching device and system | |
| CN104185826A (en) | Controlling power management in micro-servers | |
| CN106294227A (en) | Arbitration equipment, dynamic self-adapting referee method and system | |
| CN109063926A (en) | Plan generated energy determines method, system and terminal device in period | |
| CN109857533A (en) | A kind of timed task dispatching method, device and intelligent terminal | |
| CN104283943A (en) | Communication optimizing method for cluster server | |
| TW202127250A (en) | Method for computation resource allocation and management and proxy server thereof | |
| Radu et al. | Domain-knowledge optimized simulated annealing for Network-on-Chip application mapping | |
| KR101506448B1 (en) | Method And Apparatus for Managing Machine to Machine Traffic | |
| CN109587221A (en) | Large data sets group managing means, device, storage medium and computer equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151202 |