CN103257942A - Method and device for processing system-on-chip shared bus requests - Google Patents
Method and device for processing system-on-chip shared bus requests Download PDFInfo
- Publication number
- CN103257942A CN103257942A CN2013101036400A CN201310103640A CN103257942A CN 103257942 A CN103257942 A CN 103257942A CN 2013101036400 A CN2013101036400 A CN 2013101036400A CN 201310103640 A CN201310103640 A CN 201310103640A CN 103257942 A CN103257942 A CN 103257942A
- Authority
- CN
- China
- Prior art keywords
- bus
- primary module
- primary
- request
- treatment state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention provides a method and a device for processing system-on-chip shared bus requests. The method includes: when a bus request for one or a plurality of master modules is received, acquiring bus statistical information of the master modules; recognizing the first master module, with bus holding time large than a first preset threshold and/or with processing data amount larger than a second preset threshold; calculating processing priority levels of the master modules, processing bus requests of the master modules sequentially according to the priority levels; when the first master module is processed, judging the processing state of a bus, including busy status; when the processing state of the bus is the busy status, dividing the processing data amount of the bus request of the first master module into N data sub-amounts, correspondingly processing one data sub-amount in response to each bus request. The letter N is a positive integer. The method and the device have the advantage that shared buses can be utilized maximally to allow for efficient data communication of the modules.
Description
Technical field
The present invention relates to the SOC (system on a chip) communications field, particularly relate to the method that a kind of SOC (system on a chip) shared bus request is handled, and, the device that a kind of SOC (system on a chip) shared bus request is handled.
Background technology
Along with the raising of The Automation Design ability and integrated circuit manufacture level, particularly in the sub-micro epoch, many functional modules can be integrated on the phy chip by on-chip interconnect, thereby form a complete SOC (system on a chip), i.e. SOC system.
When each module of SOC (system on a chip) all had unified interface, it is simpler that the interconnection of intermodule just becomes.At present, in the interconnection structure between the SOC (system on a chip) module, the most extensive employing is shared bus.
In the SOC (system on a chip) of shared bus, arbitration algorithm plays an important role for the influence of system performance, particularly in the limited system of bus bandwidth.The bus arbitration mode has two kinds: distributed arbitration program and centralized arbitration.But at present, most SOC (system on a chip) adopt the centralized arbitration mode.
In concentrated arbitration mode, arbitration modules is independent of each primary module, the request of passive reception primary module.In traditional concentrated arbitration mode, arbitration modules is independent of each primary module, and the request of passive reception primary module lacks the mutual of primary module and concentrated arbitration mode, primary module sends the frequency of asking and the data volume of once asking is good by the software configured in advance, and the centre is difficult to revise.Under the excessive situation of request msg quantity of a certain primary module, be easy to cause single module holding time on the bus long cause other module in time the event of respective request occur.
Therefore, patented claim of the present invention proposes a kind of SOC (system on a chip) shared bus request processing mechanism, can utilize shared bus to greatest extent, realizes the data communication efficiently of each module.
Summary of the invention
The invention provides the method that a kind of SOC (system on a chip) shared bus request is handled, utilize shared bus to greatest extent to solve, realize the problem of each module data communication efficiently.
Accordingly, the device that the present invention also provides a kind of SOC (system on a chip) shared bus request to handle is in order to guarantee said method application in practice.
In order to address the above problem, the invention discloses the method that a kind of SOC (system on a chip) shared bus request is handled, comprising:
When receiving the bus request of one or more primary modules, obtain the bus statistical information of described one or more primary modules, described bus statistical information comprises the bus holding time, deal with data amount, bus response wait time and bus request frequency;
Identify first primary module, described first primary module is the bus holding time greater than first predetermined threshold value and/or the deal with data amount primary module greater than second predetermined threshold value;
According to the processing priority of described bus response wait time and the described one or more primary modules of bus request frequency computation part, successively the bus request of described one or more primary modules is handled according to described processing priority;
When handling described first primary module, judge the treatment state of bus, described treatment state comprises busy attitude;
At the treatment state of bus during for busy attitude, the deal with data amount of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
Preferably, described bus treatment state comprises Idle state, and described method also comprises:
When the treatment state of bus is Idle state, the deal with data amount of the bus request of described first primary module of disposable processing.
Preferably, the bus statistical information of described one or more primary modules is calculated by the statistic logic of primary module.
Preferably, described method also comprises:
Recomputate the processing priority of described one or more primary modules every the Preset Time section;
Handle the bus request of described one or more primary modules successively according to the processing priority that recomputates.
Preferably, described method also comprises:
Treatment state in bus is when having much to do attitude, to handle after the bus request of time primary module, inserts the bus request of the primary module of time priority and handles.
Preferably, the treatment state of described bus, judge in the following way:
If detecting a plurality of primary modules sends bus request, then the treatment state of described bus is busy attitude;
If detect and have only a primary module to send bus request, then the treatment state of described bus is Idle state.
The invention also discloses the device that a kind of SOC (system on a chip) shared bus request is handled, comprising:
The bus statistical information acquisition unit, be used for obtaining the bus statistical information of described one or more primary modules when receiving the bus request of one or more primary modules, described bus statistical information comprises the bus holding time, the deal with data amount, bus response wait time and bus request frequency;
The first primary module recognition unit is used for identification first primary module, and described first primary module is the bus holding time greater than first predetermined threshold value and/or the deal with data amount primary module greater than second predetermined threshold value;
Priority calculation unit, be used for the processing priority according to described bus response wait time and the described one or more primary modules of bus request frequency computation part, successively the bus request of described one or more primary modules handled according to described processing priority;
The treatment state judging unit is used for judging the treatment state of bus that when handling described first primary module described treatment state comprises busy attitude;
Data batch treatment unit, the treatment state that is used in bus is when having much to do attitude, the deal with data amount of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
Preferably, described bus treatment state comprises Idle state, and described device also comprises:
The uniform data processing unit is used for when the treatment state of bus is Idle state the deal with data amount of the bus request of described first primary module of disposable processing.
Preferably, the bus statistical information of the one or more primary modules of described device is calculated by the statistic logic of primary module.
Preferably, described device also comprises:
Priority recomputates the unit, is used for recomputating every the Preset Time section processing priority of described one or more primary modules, handles the bus request of described one or more primary modules successively according to the processing priority that recomputates.
Preferably, described device also comprises:
Inferior priority is inserted the unit, and the treatment state that is used in bus is when having much to do attitude, to handle after the bus request of time primary module, inserts the bus request of the primary module of time priority and handles.
Preferably, the treatment state of described bus, judged in the following ways by the treatment state judging unit:
If detecting a plurality of primary modules sends bus request, then the treatment state of described bus is busy attitude;
If detect and have only a primary module to send bus request, then the treatment state of described bus is Idle state.
Compared with prior art, the present invention includes following advantage:
First, each primary module has the bandwidth request control statistic logic of himself in the embodiment of the invention, can dynamically monitor the bus response condition of self, calculate the bus statistical information of this module, carrying out bus arbitration for the bus arbitration module provides reliable data basis.
Second, the bus arbitration module also possesses bandwidth request control statistic logic in the embodiment of the invention, can be according to the bus statistical information of each primary module, register by the configuration primary module, dynamically adjust the priority of primary module, bus resource is carried out reasonable distribution by the bus requirements of each primary module.
The 3rd, the embodiment of the invention can shorten according to the treatment state of bus or prolong time and/or the deal with data amount that bus request of primary module takies, and improves total line use ratio to greatest extent, improves the work efficiency of primary module, optimizes the SOC system performance.
Description of drawings
Fig. 1 shows the flow chart of steps of the method embodiment 1 of a kind of SOC (system on a chip) shared bus of the present invention request processing;
Fig. 2 shows the flow chart of steps of the method embodiment 2 of a kind of SOC (system on a chip) shared bus of the present invention request processing;
Fig. 3 shows the structured flowchart of the device embodiment of a kind of SOC (system on a chip) shared bus of the present invention request processing.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
With reference to Fig. 1, show the flow chart of steps of the method embodiment 1 of a kind of SOC (system on a chip) shared bus of the present invention request processing, can may further comprise the steps:
Particularly, in the SOC (system on a chip) of shared bus, can add a statistic logic for respectively each primary module and concentrated arbitration modules, the bus statistical information of self module can be monitored and add up to the statistic logic of primary module in real time, described bus statistical information can comprise the bus holding time of primary module, the deal with data amount, bus response wait time and bus request frequency etc., when concentrated arbitration modules is received the bus request of one or more primary modules, just can obtain the bus statistical information of the one or more primary modules that send bus request by the statistic logic of concentrating arbitration modules.Thereby provide reliable data basis for concentrating arbitration modules to carry out bus arbitration.
In embodiments of the present invention, concentrate arbitration modules to take the bus statistical information of each primary module of bus according to application, can be one by one with the bus holding time of primary module and first predetermined threshold value relatively, and/or with deal with data amount and second predetermined threshold value relatively, identify the bus holding time greater than first predetermined threshold value and/or deal with data amount greater than the primary module of second predetermined threshold value as first primary module.
Use the embodiment of the invention, after a plurality of primary modules sent bus request, the information that concentrated arbitration modules can provide according to statistic logic according to intrinsic arbitration algorithm, calculated the sequencing of bus response primary module request and handles one by one.
In embodiments of the present invention, concentrated arbitration modules can be collected the bus statistical information of each primary module, and according to each primary module for time of the demand intensity of bus and the each response of bus etc. parameter, priority to each primary module is regulated, namely realize dynamic surveillance and regulation and control to primary module priority, thus the reasonable use bus bandwidth.
Step 104 when handling described first primary module, is judged the treatment state of bus, and described treatment state comprises busy attitude;
In specific implementation, the first primary module bus holding time is long and/or the deal with data amount is bigger, before it is handled, concentrated arbitration modules can be according to the quantity of the primary module of the current bus request of receiving, judge earlier that whether bus is busy, handles first primary module according to the actual conditions of bus again.
Step 105 at the treatment state of bus during for busy attitude, is divided into N one's share of expenses for a joint undertaking data volume with the deal with data amount of the bus request of described first primary module, a subdata amount of each bus request alignment processing of described primary module, and wherein N is positive integer.
In inventive embodiments, concentrate arbitration modules to judge that bus is in when having much to do attitude, can adopt the hardware protocol feedack in conjunction with primary module, under the prerequisite of the performance that does not influence primary module, dispose the register of described first primary module, the single treatment data volume of described first primary module is divided into many piece of data repeatedly handles, thereby shorten the time that bus of first primary module takies.
In order to make those skilled in the art better understand the present invention, below by an instantiation step 105 is described:
1, the A primary module has 1000 data to transmit;
2, the B primary module also has 1000 data to transmit;
3, concentrate arbitration modules by the statistic logic of A primary module and B primary module inside, know that the demand of A and B is all bigger;
4, be higher than the B primary module by the priority of calculating the A primary module;
5, judge that by the statistic logic of concentrating arbitration modules bus is in busy attitude;
6, the register of configuration A primary module makes the A primary module can send the order of once transmitting 100 data;
7, the register of configuration B primary module makes the B primary module can send the order of once transmitting 50 data;
8, the A primary module sends application, data transmission can be finished for 10 times;
9, the B primary module sends application, data transmission can be finished for 20 times.
Embodiments of the invention can be according to the priority of each primary module for the demand intensity of bus and the time of the each response of bus etc. each primary module of calculation of parameter, bus resource is reasonably distributed to each primary module, thereby improve the work efficiency of primary module.And, the embodiment of the invention can be according to the treatment state of bus, shorten bus holding time and/or the deal with data amount of primary module, effectively solve the long and/or excessive problem that causes other primary module to can not get bus resource of deal with data amount of bus holding time of primary module, improved the utilization factor of bus, and can improve the work efficiency of SOC system on the whole, reach the effect of optimizing the SOC system.
With reference to Fig. 2, show the flow chart of steps of the method embodiment 2 of a kind of SOC (system on a chip) shared bus of the present invention request processing, can may further comprise the steps:
In embodiments of the present invention, the bus statistical information of described one or more primary modules is calculated by the statistic logic of primary module.
Step 202 is identified first primary module, and described first primary module is the bus holding time greater than first predetermined threshold value and/or the deal with data amount primary module greater than second predetermined threshold value;
Step 203 according to the processing priority of described bus response wait time and the described one or more primary modules of bus request frequency computation part, is handled the bus request of described one or more primary modules successively according to described processing priority;
Use the embodiment of the invention, every a time period, concentrated arbitration modules can be according to the bus statistical information of intrinsic algorithm and each primary module, register to primary module is configured, recomputate the priority of each primary module and primary module is handled the dynamic priority of adjusting primary module of realization according to the described priority that recomputates.
Step 205 when handling described first primary module, is judged the treatment state of bus, and described treatment state comprises busy attitude and Idle state;
In a preferred embodiment of the present invention, the treatment state of described bus can be judged in the following way:
If detecting a plurality of primary modules sends bus request, then the treatment state of described bus is busy attitude;
If detect and have only a primary module to send bus request, then the treatment state of described bus is Idle state.
Step 206 at the treatment state of bus during for busy attitude, is divided into N one's share of expenses for a joint undertaking data volume with the deal with data amount of the bus request of described first primary module, a subdata amount of each bus request alignment processing of described primary module, and wherein N is positive integer;
Step 207 is handled after the bus request of time primary module, inserts the bus request of the primary module of time priority and handles;
In specific implementation, when bus is in busy attitude, a suitable bus request with the high priority primary module is divided into repeatedly request to be finished, and the primary module of lower priority just can obtain certain bus resource in the gap of the primary module bus request of handling high priority.
In order to make those skilled in the art better understand the present invention, below by an instantiation step 207 is described:
1, the A primary module has 1000 data to transmit;
2, the B primary module also has 1000 data to transmit;
3, the bandwidth request of primary module inside control statistic logic shows that the demand of A primary module and B primary module is all many, and bandwidth request control statistic logic discovery bus this moment in the arbitration modules is busier, but the priority of A, B primary module is higher;
4, the register of configuration A primary module, notice A primary module can send the order of once transmitting 100 data, data transmission can be finished for 10 times;
5, the register of configuration B primary module, notice B primary module can send the order of once transmitting 50 data, data transmission can be finished for 20 times;
6, in the process of A, B primary module transmission data, the priority ratio of A is higher, same judgement A primary module down can obtain the bus response earlier, but the A primary module once transmit finish after, if 100 data of second batch also are not ready for, the B primary module just can also transmit the partial data of oneself by plug hole so.
Particularly, when bus is in Idle state, can dispose the register of primary module, make primary module can once send the bus application of comparison big data quantity, and respond its bus application.So just can shorten the working time of described primary module, improve the work efficiency of primary module.
In order to make those skilled in the art better understand the present invention, below by an instantiation step 208 is described:
1, the A primary module has 1000 data to transmit;
2, the bandwidth request of primary module inside control statistic logic shows that the demand of A is many, and the bandwidth request control statistic logic in the arbitration modules finds that this moment, bus was not in a hurry;
3, the register of configuration A primary module, notice A primary module can send the order of once transmitting 1000 data;
4, the A primary module sends application, once data transmission can be finished;
5, in the process of described A primary module 1000 numbers of transmission, because bus is occupied, other any application can not obtain corresponding.
Usually primary module all be one by one can be multiplexing IP, this IP applies for once that generally the demand of bus can pass through register configuration, this configuration is static traditionally, if and the dynamic arbitration mechanism of the embodiment of the invention has been arranged, just can be configured it dynamically, like this when bus is idle, dispose this register, allow the single job time of primary module longer, and when bus is busy, allow the single job of primary module shorter, thereby realize allowing other primary module insert order.
Present embodiment can be regulated the priority of each primary module dynamically, and according to the virtual condition of bus, when being in busy attitude, bus shortens primary module bus application holding time and/or deal with data amount, allow each primary module can both obtain certain bus resource, when bus is in Idle state, prolong primary module bus application holding time and/or deal with data amount, can improve the work efficiency of this primary module.
With reference to Fig. 3, show the structured flowchart of the device embodiment of a kind of SOC (system on a chip) shared bus of the present invention request processing, can comprise with lower module:
Bus statistical information acquisition unit 301, be used for when receiving the bus request of one or more primary modules, obtain the bus statistical information of described one or more primary modules, described bus statistical information comprises the bus holding time, the deal with data amount, bus response wait time and bus request frequency;
The first primary module recognition unit 302 is used for identification first primary module, and described first primary module is the bus holding time greater than first predetermined threshold value and/or the deal with data amount primary module greater than second predetermined threshold value;
Treatment state judging unit 305 is used for judging the treatment state of bus that when handling described first primary module described treatment state comprises busy attitude and Idle state;
In a preferred embodiment of the present invention, the treatment state of described bus can be judged in the following way by the treatment state judging unit:
If detecting a plurality of primary modules sends bus request, then the treatment state of described bus is busy attitude;
If detect and have only a primary module to send bus request, then the treatment state of described bus is Idle state.
Data batch treatment unit 306, the treatment state that is used in bus is when having much to do attitude, the deal with data amount of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer;
Inferior priority is inserted unit 307,, inserts the bus request of the primary module of time priority and handles after the bus request of time primary module for the treatment of intact;
Uniform data processing unit 308 is used for when the treatment state of bus is Idle state the deal with data amount of the bus request of described first primary module of disposable processing.
For device embodiment, because it is similar substantially to method embodiment, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For device embodiment, because it is similar substantially to method embodiment, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
Those skilled in the art should understand that embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt complete hardware embodiment, complete software embodiment or in conjunction with the form of the embodiment of software and hardware aspect.And the present invention can adopt the form of the computer program of implementing in one or more computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) that wherein include computer usable program code.
The present invention is that reference is described according to process flow diagram and/or the block scheme of method, equipment (system) and the computer program of the embodiment of the invention.Should understand can be by the flow process in each flow process in computer program instructions realization flow figure and/or the block scheme and/or square frame and process flow diagram and/or the block scheme and/or the combination of square frame.Can provide these computer program instructions to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, make the instruction of carrying out by the processor of computing machine or other programmable data processing device produce to be used for the device of the function that is implemented in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame appointments.
These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, make the instruction that is stored in this computer-readable memory produce the manufacture that comprises command device, this command device is implemented in the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame.
These computer program instructions also can be loaded on computing machine or other programmable data processing device, make and carry out the sequence of operations step producing computer implemented processing at computing machine or other programmable devices, thereby be provided for being implemented in the step of the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame in the instruction that computing machine or other programmable devices are carried out.
Although described the preferred embodiments of the present invention, in a single day those skilled in the art get the basic creative concept of cicada, then can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the scope of the invention.
At last, also need to prove, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.Do not having under the situation of more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
More than method and device that a kind of SOC (system on a chip) shared bus request provided by the present invention is handled be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. the method that the request of SOC (system on a chip) shared bus is handled is characterized in that, comprising:
When receiving the bus request of one or more primary modules, obtain the bus statistical information of described one or more primary modules, described bus statistical information comprises the bus holding time, deal with data amount, bus response wait time and bus request frequency;
Identify first primary module, described first primary module is the bus holding time greater than first predetermined threshold value and/or the deal with data amount primary module greater than second predetermined threshold value;
According to the processing priority of described bus response wait time and the described one or more primary modules of bus request frequency computation part, successively the bus request of described one or more primary modules is handled according to described processing priority;
When handling described first primary module, judge the treatment state of bus, described treatment state comprises busy attitude;
At the treatment state of bus during for busy attitude, the deal with data amount of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
2. method according to claim 1 is characterized in that, described bus treatment state comprises Idle state, and described method also comprises:
When the treatment state of bus is Idle state, the deal with data amount of the bus request of described first primary module of disposable processing.
3. method according to claim 1 and 2 is characterized in that, the bus statistical information of described one or more primary modules is calculated by the statistic logic of primary module.
4. method according to claim 1 is characterized in that, also comprises:
Recomputate the processing priority of described one or more primary modules every the Preset Time section;
Handle the bus request of described one or more primary modules successively according to the processing priority that recomputates.
5. method according to claim 1 is characterized in that, also comprises:
Treatment state in bus is when having much to do attitude, to handle after the bus request of time primary module, inserts the bus request of the primary module of time priority and handles.
6. method according to claim 1 and 2 is characterized in that, the treatment state of described bus is judged in the following way:
If detecting a plurality of primary modules sends bus request, then the treatment state of described bus is busy attitude;
If detect and have only a primary module to send bus request, then the treatment state of described bus is Idle state.
7. the device that the request of SOC (system on a chip) shared bus is handled is characterized in that, comprising:
The bus statistical information acquisition unit, be used for obtaining the bus statistical information of described one or more primary modules when receiving the bus request of one or more primary modules, described bus statistical information comprises the bus holding time, the deal with data amount, bus response wait time and bus request frequency;
The first primary module recognition unit is used for identification first primary module, and described first primary module is the bus holding time greater than first predetermined threshold value and/or the deal with data amount primary module greater than second predetermined threshold value;
Priority calculation unit, be used for the processing priority according to described bus response wait time and the described one or more primary modules of bus request frequency computation part, successively the bus request of described one or more primary modules handled according to described processing priority;
The treatment state judging unit is used for judging the treatment state of bus that when handling described first primary module described treatment state comprises busy attitude;
Data batch treatment unit, the treatment state that is used in bus is when having much to do attitude, the deal with data amount of the bus request of described first primary module is divided into N one's share of expenses for a joint undertaking data volume, a subdata amount of each bus request alignment processing of described primary module, wherein N is positive integer.
8. device according to claim 7 is characterized in that, described bus treatment state comprises Idle state, and described device also comprises:
The uniform data processing unit is used for when the treatment state of bus is Idle state the deal with data amount of the bus request of described first primary module of disposable processing.
9. according to claim 7 or 8 described devices, it is characterized in that the bus statistical information of described one or more primary modules is calculated by the statistic logic of primary module.
10. device according to claim 7 is characterized in that, also comprises:
Priority recomputates the unit, is used for recomputating every the Preset Time section processing priority of described one or more primary modules, handles the bus request of described one or more primary modules successively according to the processing priority that recomputates.
11. device according to claim 7 is characterized in that, also comprises:
Inferior priority is inserted the unit, and the treatment state that is used in bus is when having much to do attitude, to handle after the bus request of time primary module, inserts the bus request of the primary module of time priority and handles.
12. according to claim 7 or 8 described devices, it is characterized in that the treatment state of described bus is judged in the following ways by the treatment state judging unit:
If detecting a plurality of primary modules sends bus request, then the treatment state of described bus is busy attitude;
If detect and have only a primary module to send bus request, then the treatment state of described bus is Idle state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310103640.0A CN103257942B (en) | 2013-03-27 | 2013-03-27 | A kind of method of SOC (system on a chip) shared bus request process and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310103640.0A CN103257942B (en) | 2013-03-27 | 2013-03-27 | A kind of method of SOC (system on a chip) shared bus request process and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103257942A true CN103257942A (en) | 2013-08-21 |
| CN103257942B CN103257942B (en) | 2015-12-02 |
Family
ID=48961872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310103640.0A Expired - Fee Related CN103257942B (en) | 2013-03-27 | 2013-03-27 | A kind of method of SOC (system on a chip) shared bus request process and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103257942B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103870404A (en) * | 2014-03-13 | 2014-06-18 | 武汉精测电子技术股份有限公司 | IIC (Inter-Integrated Circuit) batch command processing control method |
| CN107844442A (en) * | 2016-09-19 | 2018-03-27 | 深圳市中兴微电子技术有限公司 | The referee method and device of request source response |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09160868A (en) * | 1995-12-11 | 1997-06-20 | Ricoh Co Ltd | Bus arbitration device and method therefor |
| JP2000132505A (en) * | 1998-10-27 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Bus access method and device therefor, and device and system using the bus access method and device |
| CN1282924A (en) * | 1999-07-29 | 2001-02-07 | 国际商业机器公司 | Enhanced bus orbitrator using variable priority and reasonableness |
| CN1507592A (en) * | 2001-06-23 | 2004-06-23 | Ħ��������˾ | System and method for controlling bus arbitration during cache memory burst cycles |
| CN1577304A (en) * | 2003-06-26 | 2005-02-09 | 三星电子株式会社 | Dynamic bus arbitration method and bus arbiter |
| CN1661579A (en) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
| CN101075220A (en) * | 2007-04-29 | 2007-11-21 | 北京中星微电子有限公司 | Simulator and method for bus arbitraction |
| CN101089833A (en) * | 2006-06-15 | 2007-12-19 | 索尼株式会社 | Information processing apparatus, method of same, and program for same |
| CN101510181A (en) * | 2009-03-19 | 2009-08-19 | 北京中星微电子有限公司 | Bus arbitration method and bus arbitration apparatus |
| WO2009147744A1 (en) * | 2008-06-06 | 2009-12-10 | 三菱電機株式会社 | Bus arbiter |
| CN101930417A (en) * | 2010-08-13 | 2010-12-29 | 北京飞利信科技股份有限公司 | Arbiter for serial data bus-based streaming media transmission system terminal equipment |
-
2013
- 2013-03-27 CN CN201310103640.0A patent/CN103257942B/en not_active Expired - Fee Related
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09160868A (en) * | 1995-12-11 | 1997-06-20 | Ricoh Co Ltd | Bus arbitration device and method therefor |
| JP2000132505A (en) * | 1998-10-27 | 2000-05-12 | Matsushita Electric Ind Co Ltd | Bus access method and device therefor, and device and system using the bus access method and device |
| CN1282924A (en) * | 1999-07-29 | 2001-02-07 | 国际商业机器公司 | Enhanced bus orbitrator using variable priority and reasonableness |
| CN1507592A (en) * | 2001-06-23 | 2004-06-23 | Ħ��������˾ | System and method for controlling bus arbitration during cache memory burst cycles |
| CN1577304A (en) * | 2003-06-26 | 2005-02-09 | 三星电子株式会社 | Dynamic bus arbitration method and bus arbiter |
| CN1661579A (en) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
| CN101089833A (en) * | 2006-06-15 | 2007-12-19 | 索尼株式会社 | Information processing apparatus, method of same, and program for same |
| CN101075220A (en) * | 2007-04-29 | 2007-11-21 | 北京中星微电子有限公司 | Simulator and method for bus arbitraction |
| WO2009147744A1 (en) * | 2008-06-06 | 2009-12-10 | 三菱電機株式会社 | Bus arbiter |
| CN101510181A (en) * | 2009-03-19 | 2009-08-19 | 北京中星微电子有限公司 | Bus arbitration method and bus arbitration apparatus |
| CN101930417A (en) * | 2010-08-13 | 2010-12-29 | 北京飞利信科技股份有限公司 | Arbiter for serial data bus-based streaming media transmission system terminal equipment |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103870404A (en) * | 2014-03-13 | 2014-06-18 | 武汉精测电子技术股份有限公司 | IIC (Inter-Integrated Circuit) batch command processing control method |
| CN103870404B (en) * | 2014-03-13 | 2016-09-14 | 武汉精测电子技术股份有限公司 | A kind of IIC criticizes command process control method |
| CN107844442A (en) * | 2016-09-19 | 2018-03-27 | 深圳市中兴微电子技术有限公司 | The referee method and device of request source response |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103257942B (en) | 2015-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11507430B2 (en) | Accelerated resource allocation techniques | |
| CN110618870B (en) | Working method and device for deep learning training task | |
| de Souza Carvalho et al. | Dynamic task mapping for MPSoCs | |
| US11010313B2 (en) | Method, apparatus, and system for an architecture for machine learning acceleration | |
| JP2020515976A (en) | Method, apparatus and system for blockchain consensus | |
| TWI547817B (en) | Method, system and apparatus of planning resources for cluster computing architecture | |
| CN101986272A (en) | Task scheduling method under cloud computing environment | |
| CN102855218A (en) | Data processing system, method and device | |
| CN105320570B (en) | Method for managing resource and system | |
| CN114281521B (en) | Method, system, equipment and medium for optimizing deep learning heterogeneous resource communication efficiency | |
| CN105335229A (en) | Business resource scheduling method and apparatus | |
| CN106528288A (en) | Resource management method, device and system | |
| CN103699433A (en) | Method and system for performing dynamic adjustment on number of tasks in Hadoop platform | |
| CN105488134A (en) | Big data processing method and big data processing device | |
| CN109587072A (en) | Distributed system overall situation speed limiting system and method | |
| Fan et al. | Dynamic virtual network embedding of mobile cloud system based on global resources in internet of vehicles | |
| CN111309488A (en) | Method and system for sharing computing resources of unmanned aerial vehicle cluster and computer storage medium | |
| CN114741200A (en) | Data center station-oriented computing resource allocation method and device and electronic equipment | |
| CN103257942A (en) | Method and device for processing system-on-chip shared bus requests | |
| CN108153583A (en) | Method for allocating tasks and device, real-time Computational frame system | |
| CN103823712A (en) | Data flow processing method and device for multi-CPU virtual machine system | |
| CN109347982A (en) | A kind of dispatching method and device of data center | |
| CN114003238B (en) | Container deployment method, device, equipment and storage medium based on transcoding card | |
| Bargavi et al. | The dynamic window-based scheduling framework for complex wireless sensor networks | |
| Zhu et al. | Research on fog resource scheduling based on cloud-fog collaboration technology in the electric internet of things |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151202 |