CN103257850B - A kind of instruction cache based on zone bit access trace - Google Patents
A kind of instruction cache based on zone bit access trace Download PDFInfo
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- CN103257850B CN103257850B CN201310159643.6A CN201310159643A CN103257850B CN 103257850 B CN103257850 B CN 103257850B CN 201310159643 A CN201310159643 A CN 201310159643A CN 103257850 B CN103257850 B CN 103257850B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to a kind of instruction cache (Instruction Cache) based on zone bit access trace, comprise: tracking information table, its degree of depth equals Instruction Cache line number, and whether every a line exists the tracking information position of the access trace to tag memory corresponding row for storing expression; Tracking information maintenance circuitry, export overflow control signal according to the program segment address scope in the branch direction inputted, branch target address, fetching address and tracking information maintenance circuitry, described overflow control signal represents whether fetching address or branch target address are within program segment address scope; Control circuit, for controlling the reading to tag memory according to tracking information position, and safeguards tracking information table according to overflow control signal.Instruction Cache of the present invention utilizes the zone bit of record access tracking information to carry out hit detection to Instruction Cache in advance in program process, eliminates unnecessary tag memory access, effectively reduces the power consumption of Instruction Cache.
Description
Technical field
The present invention relates to a kind of instruction cache based on zone bit access trace.
Background technology
Along with the develop rapidly of semiconductor process techniques, the performance of flush bonding processor chip and integrated level are obtained for very large raising, and the power problems brought thus is also day by day serious.As the vitals making gaps between their growth rates between processor cores and primary memory up, power consumption is remarkable owing to having very high access frequency for instruction cache (Instruction Cache).Therefore, the design important in inhibiting of power consumption for low-power-consumption embedded processor of Instruction Cache is effectively reduced.
As shown in Figure 1, it is primarily of mark (tag) storer, data (data) storer and mode bit (state) composition for the structure of the Instruction Cache of the direct mapping mode of traditional employing.As processor cores access instruction Cache, tag memory reads zone bit tag according to the index bit (Index) in fetching address as address, and with the Tag bit comparison in fetching address: if comparative result is that both are equal, then represent Cache hit, processor cores is reading command from the data-carrier store of Instruction Cache directly; If it is unequal that comparative result is for both, then represent Cache disappearance, at this moment can start the operation of an access primary memory.Processor cores needs to carry out a large amount of reading tag memory operations and compare operation, the energy that these action need consumption are a large amount of in the process of instruction fetch.If the number of times of access flag storer can be reduced, then effectively can reduce the power consumption of Instruction Cache.
In August, 2002 low power dissipation electron of No. 12-14 with design (ISLPED) meeting on, the article " A History-Based I-Cache for Low-Energy MultimediaApplications " that the people such as KojiInoue deliver proposes a kind of Low-Power Instruction Cache method for designing based on history of program execution information, and the method and branch prediction techniques are combined closely.Its principle of work is: if Branch Target Instruction once performed, and performs this Branch Target Instruction and Instruction Cache did not occur during performing this Branch Target Instruction last time and lack, then can stop access flag storer.
But the Low-Power Instruction Cache method for designing based on history of program execution information that the people such as Koji Inoue propose has following shortcoming:
(1) this technology is combined closely with branch target buffer, and when branch prediction and history of program execution information updating occur simultaneously, processor pipeline there will be pause, causes processor performance to decline;
(2) when occurring that Instruction Cache lacks, need the history of program execution information cleared all, cause processor that the effective historical information already recorded cannot be utilized in program process to eliminate unnecessary tag memory access, thus reduce the service efficiency of history of program execution information;
(3) for the flush bonding processor not adopting branch prediction mechanism, setting up a branch predictor needs to increase very large hardware costs, and branch predictor itself also needs to consume part energy.
Summary of the invention
The object of this invention is to provide a kind of instruction cache based on zone bit access trace that can address the aforementioned drawbacks.
The invention provides a kind of instruction cache based on zone bit access trace, comprise tracking information maintenance circuitry, tracking information table, control circuit, tag memory and data-carrier store, wherein: the line number of described tracking information table is equal with the line number of described tag memory and described data-carrier store respectively, every a line of described tracking information table for storing a tracking information position, whether effective access trace representing the corresponding row whether existed described tag memory respectively of described tracking information position; Described tracking information maintenance circuitry is used for exporting overflow control signal according to the program segment address scope in the branch direction inputted, branch target address, fetching address and described tracking information maintenance circuitry, and the whether effective of described overflow control signal represents whether described fetching address or described branch target address are within described program segment address scope respectively; Control circuit, for controlling the reading to described tag memory, and for safeguarding described tracking information table according to described overflow control signal according to described tracking information position.
Preferably, described tracking information maintenance circuitry comprises: control register, for section first address and the section tail address of storing said program sector address scope; Comparing unit, for according to described branch direction, described branch target address, described fetching address and described program segment address scope output branch overflow signals, branch's underflow signal and order underflow signal; Or door, for exporting described overflow control signal according to described branch overflow signals, branch's underflow signal and order underflow signal.
Preferably, described control register comprises: the first register, for the section first address of storing said program sector address scope; Second register, for the section tail address of storing said program sector address scope.
Preferably, described comparing unit comprises: the first comparing unit, and it, by described branch target address and described section of first address being compared, exports described branch overflow signals; Second comparing unit, it, by described branch target address and described section of tail address being compared, exports described branch underflow signal; 3rd comparing unit, it, by being compared in described fetching address and described section of tail address, exports described order underflow signal.
Preferably, described tracking information position is effective, and described control circuit is arranged to: forbid reading described tag memory, and utilizes described fetching address reading command from described data-carrier store.
Preferably, described overflow control signal is effective, described control circuit is also arranged to: under described branch overflow signals or the effective situation of described branch underflow signal, remove the content in described tracking information table, and using described branch target address as described section of first address stored in described first register, simultaneously using the capability value sum of described branch target address and instruction cache memory as described section of tail address stored in described second register, described capability value represents in units of byte; In the effective situation of described order underflow signal, remove the content in described tracking information table, and described first register and described second register are reset.
Preferably, it is backward branch instruction or forward-facing branch instruction that described branch direction is used to indicate branch instruction, when described branch direction instruction branch instruction is backward branch instruction, described first comparing unit work, described control circuit cuts out the 3rd comparing unit; When described branch direction instruction branch instruction is forward-facing branch instruction, described second comparing unit work; When described branch direction instruction branch instruction be forward-facing branch instruction or branch instruction performs unsuccessfully, described 3rd comparing unit of described control circuit startup.
Preferably, described tracking information position is invalid, and described control circuit is also arranged to: reading command from described data-carrier store or primary memory is also returned to processor cores; When the instruction of reading returns to processor cores, the described tracking information position of corresponding row in described tracking information table is set to effectively.
Preferably, described tracking information position is invalid, and described control circuit is also arranged to: utilize described fetching address to read zone bit from described tag memory; Judge whether the zone bit read mates with the zone bit in described fetching address; In the event of a match, described fetching address reading command from the corresponding row of described data-carrier store is utilized; In absence of such a match, utilize described fetching address reading command from primary memory, and the instruction of reading is write the corresponding row of described data-carrier store.
Preferably, described control circuit is also arranged to: from the corresponding row of described tracking information table, read described tracking information position according to described fetching address, to determine whether there is the access trace of the corresponding row to described tag memory.
Instruction Cache based on zone bit access trace of the present invention utilizes the zone bit of record access tracking information to carry out hit detection to Instruction Cache in advance in program process, eliminate unnecessary tag memory access, effectively reduce the power consumption of Instruction Cache.
Accompanying drawing explanation
Fig. 1 is the structural representation of the Instruction Cache of traditional direct mapping mode of employing;
Fig. 2 is the structural representation of the Instruction Cache based on zone bit access trace according to the embodiment of the present invention;
Fig. 3 is the workflow diagram of the Instruction Cache based on zone bit access trace according to the embodiment of the present invention; And
Fig. 4 is a concrete instruction code schematic diagram.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 2 is the structural representation of the Instruction Cache based on zone bit access trace according to the embodiment of the present invention.
Fig. 3 is the workflow diagram of the Instruction Cache based on zone bit access trace according to the embodiment of the present invention.
Below, composition graphs 2 and Fig. 3, be introduced the principle of work of the Instruction Cache based on zone bit access trace according to the embodiment of the present invention.
As shown in Figure 2, Instruction Cache forms primarily of tracking information maintenance circuitry, tracking information table, tag memory, data-carrier store and control circuit (not shown).
Tracking information maintenance circuitry mainly comprise control register, comparing unit and or door, its for accept to be inputted to it by processor cores branch direction, branch target address, fetching address, export overflow control signal according to the program segment address scope in these inputs and described tracking information maintenance circuitry, the whether effective of described overflow control signal represents whether the fetching address of input or branch target address are within program segment address scope respectively.
Control register comprises the first register and the second register, is respectively used to section first address and the section tail address of storage program sector address scope.Comparing unit comprises the first comparing unit, the second comparing unit and the 3rd comparing unit.Section first address in the branch target address of input and the first register compares by the first comparing unit, output branch underflow signal; Section tail address in the branch target address of input and the second register compares by the second comparing unit, output branch underflow signal; Section tail address in the fetching address of input and the second register compares by the 3rd comparing unit, output order underflow signal.Or door exports overflow control signal according to branch's overflow signals, branch's underflow signal and order underflow signal.
The line number of tracking information table is all equal with the line number of the line number of tag memory and data-carrier store, its every a line for storing a tracking information position, whether effective access trace representing the corresponding row whether existed described tag memory respectively of described tracking information position.
Control circuit is used for the reading controlling described tag memory according to tracking information position, and for safeguarding tracking information table according to described overflow control signal.Described control circuit both can exist independent of each several part in Instruction Cache, also can be integrated in tracking information maintenance circuitry.The implementation method that it will be appreciated by those skilled in the art that the control circuit in order to realize controlling functions according to various control signal is various.At this, the function of a description control circuit and repeat no more its specific implementation, in order to avoid fuzzy theme of the present invention.
In addition, tag memory and data-carrier store and traditional Instruction Cache are as good as, and repeat no more.
Those skilled in the art are to be understood that, it is the Instruction Cache of the direct mapping mode of N byte for capacity, if the program segment that in primary memory, certain beginning and end address is respectively X and Y to be in Instruction Cache and Y-X<N, then when fetching address PC meets X≤PC<X+N, the instruction in this program segment can be replaced away scarcely.
The course of work of process flow diagram to the Instruction Cache according to the embodiment of the present invention below in conjunction with Fig. 3 is described.
In program process, when running into Article 1 branch instruction, capability value (Cache capacity represents in units of the byte) sum of this branch target address and instruction Cache using the branch target address of this branch instruction as in the first register of section first address write control register, can write in the second register of control register as section tail address by tracking information maintenance circuitry simultaneously.Establish a program segment address scope by section first address and section tail address, represent that starting now executive address is in program segment within this program segment address scope.
Owing to being first time perform this branch instruction, processor cores there will be Cache disappearance when reading the target instruction target word of this branch instruction, thus needs the target instruction target word of reading this branch instruction from primary memory.When the target instruction target word of this branch instruction returned from primary memory is written into Instruction Cache, in tracking information table, the tracking information position of corresponding row is set to effective.
In ensuing program process, need to judge the fetching address of input, adopt different processing modes, described in specific as follows according to judged result.
On the one hand, when being in fetching address within the program segment address scope in tracking information maintenance circuitry:
If control circuit is effectively (disable signal is effective) according to the tracking information position that the index bit in fetching address reads, then presentation directives Cache hits, under the control of control circuit, processor cores is reading command and do not need access flag storer from data-carrier store directly; If the tracking information position that control circuit reads according to the index bit in fetching address is invalid (disable signal is invalid), then needs access flag storer under the control of control circuit to carry out decision instruction Cache and whether hit.
When tracking information position is invalid: if Instruction Cache hit, then control circuit will from data-carrier store reading command, the instruction of reading is returned to processor cores be simultaneously set to effectively by the tracking information position of corresponding row in tracking information table; If Instruction Cache disappearance, then control circuit will from primary memory reading command, by the instruction of reading write data-carrier store in and the tracking information position of corresponding row in tracking information table is set to effectively simultaneously.
On the other hand, if the fetching address of input is not in (situation that fetching address is overflowed) within the program segment address scope in tracking information maintenance circuitry, then need under the control of control circuit, first register and the second register are modified or reset, and remove tracking information table simultaneously, keep a correct corresponding relation all the time with tracking information table with the program segment address scope guaranteeing in tracking information maintenance circuitry.
In program process, occur that the situation that fetching address is overflowed has following three kinds:
First, it will be apparent to those skilled in the art that branch instruction comprises backward branch instruction and forward-facing branch instruction: the finger offsets quantity symbol position of backward branch instruction is negative, the branch direction of its correspondence is " 1 "; The finger offsets quantity symbol position of forward-facing branch instruction is just, the branch direction of its correspondence is " 0 ".
(1) situation that the fetching address caused by branch instruction is upwards overflowed, it occurs when running into backward branch instruction and the branch target address of this backward branch instruction is less than value (the section first address) of the first register.When this happens, branch's overflow signals that the first comparing unit exports is effective, or the overflow control signal that door exports is effective.Now, control circuit is according to effective overflow control signal, remove tracking information table, and the branch target address of this backward branch instruction is write in the first register, the capability value sum of this branch target address and instruction Cache is write in the second register simultaneously.
(2) situation that the fetching address caused by branch instruction is overflowed downwards, it occurs when running into forward-facing branch instruction and the branch target address of this forward-facing branch instruction is more than or equal to value (the section tail address) of the second register.When this happens, branch's underflow signal that the second comparing unit exports is effective, or the overflow control signal that door exports is effective.Now, control circuit is according to effective overflow control signal, remove tracking information table, and the branch target address of this forward-facing branch instruction is write in the first register, the capability value sum of this branch target address and instruction Cache is write in the second register simultaneously.
(3) situation that the fetching address caused by sequential instructions is overflowed downwards, it occurs when running into sequential instructions and the fetching address of this sequential instructions equals the value of the second register.When this happens, the order underflow signal that the 3rd comparing unit exports is effective, or the overflow control signal that door exports is effective.Now, control circuit, according to effective overflow control signal, removes tracking information table, and the first register and the second register is reset.Next, when again running into branch instruction, then the branch target address of this branch instruction being write in the first register, the capability value sum of this branch target address and instruction Cache being write in the second register simultaneously.
According to the signal whether branch direction and instruction branch instruction run succeeded, control circuit can control first, second, and third comparing unit.Particularly, the first comparing unit works to during branch instruction after execution, and control circuit cuts out the 3rd comparing unit when running into backward branch instruction; Second comparing unit works to during branch instruction before execution; Control circuit when branch direction instruction branch instruction be forward-facing branch instruction or performs unsuccessfully in branch instruction, startup the 3rd comparing unit.
Fig. 4 is a concrete instruction code schematic diagram.
The concrete implementation of instruction code to the Instruction Cache based on zone bit access trace according to the embodiment of the present invention below by Fig. 4 is described.
Presumptive instruction Cache capacity is 8KB, and block size is 16B, adopts direct mapping mode.The tracking information table degree of depth is 512, equals the line number of Instruction Cache; Tracking information epi-position is wide is 1bit, and its value is that " 1 " represents that the tracking information position of corresponding row is effective, and its value is that " 0 " represents that the tracking information position of corresponding row is invalid.Concrete instruction code as shown in Figure 4.
The first register in tracking information maintenance circuitry and the initial value of the second register are all 0, and the initial value of tracking information table is full 0.
When program performs the branch instruction at 0x00000080 place, because value address is overflowed, the branch target address 0x00000090 of this branch instruction can write in the first register by tracking information maintenance circuitry, the capability value sum (0x00000090+0x2000=0x00002090) of this branch target address and instruction Cache is write in the second register simultaneously.The value section of the being respectively first address of the first register and the second register and section tail address, namely represent that starting now executive address is in program segment between 0x00000090 to 0x00002090.Due to be first time perform this branch instruction, therefore there will be Cache disappearance when processor cores reads the instruction at 0x00000090 place, control circuit is according to fetching address reading command from primary memory, and by the instruction write Instruction Cache returned from primary memory, the tracking information position of corresponding row is set to 1 simultaneously.In ensuing fetching process, if be 1 according to the tracking information position of the index bit reading in fetching address, then control circuit cuts out tag memory, directly reading command from data-carrier store; If be 0 according to the tracking information position that the index bit in fetching address reads, then need access flag storer to carry out decision instruction Cache and whether hit.If Instruction Cache hits, then control circuit reading command from data-carrier store, and while the instruction of reading returns to processor cores, the tracking information position of corresponding row is set to 1; If Instruction Cache lacks, then control circuit reading command from primary memory, and the instruction of reading is write in Instruction Cache, the tracking information position of corresponding row is set to 1 simultaneously.
When program performs the instruction at 0x00002090 place, the fetching address of this instruction is equal with the value of the second register.At this moment, the order underflow signal that the 3rd comparing unit exports is 1, or the overflow control signal that door exports is 1.First register and the second register according to effective overflow control signal removal tracking information table, and reset by control circuit.
When program performs the branch instruction at 0x00002190 place, because fetching address is overflowed, the branch target address 0x00004100 of this branch instruction can write in the first register by tracking information maintenance circuitry, the capability value sum (0x00004100+0x2000=0x00006100) of this branch target address and instruction Cache is write in the second register simultaneously.In ensuing fetching process, if be 1 according to the tracking information position of the index bit reading in fetching address, then control circuit cuts out tag memory, directly reading command from data-carrier store; If be 0 according to the tracking information position that the index bit in fetching address reads, then need access flag storer to carry out decision instruction Cache and whether hit.If Instruction Cache hits, then control circuit reading command from data-carrier store, and while the instruction of reading returns to processor cores, the tracking information position of corresponding row is set to 1; If Instruction Cache lacks, then control circuit reading command from primary memory, and the instruction of reading is write in Instruction Cache, the tracking information position of corresponding row is set to 1 simultaneously.
When program performs the branch instruction at 0x00004200 place, the branch target address 0x00006200 of this branch instruction is greater than the value of the second register.At this moment, branch's underflow signal that the second comparing unit exports is 1, or the overflow control signal that door exports is 1.0x00006200 according to effective overflow control signal removal tracking information table, and writes in the first register by control circuit, (0x00006200+0x2000=0x00008200) is write in the second register simultaneously.In ensuing fetching process, if be 1 according to the tracking information position of the index bit reading in fetching address, then control circuit cuts out tag memory, directly reading command from data-carrier store; If be 0 according to the tracking information position that the index bit in fetching address reads, then need access flag storer to carry out decision instruction Cache and whether hit.If Instruction Cache hits, then control circuit reading command from data-carrier store, and while the instruction of reading returns to processor cores, the tracking information position of corresponding row is set to 1; If Instruction Cache lacks, then control circuit reading command from primary memory, and the instruction of reading is write in Instruction Cache, the tracking information position of corresponding row is set to 1 simultaneously.
When program performs the branch instruction at 0x00006260 place, the branch target address 0x00004100 of this branch instruction is less than the value of the first register.At this moment, the overflow signals that first comparing unit exports is 1, or the overflow control signal that door exports is 1, control circuit is according to effective overflow control signal removal tracking information table, and 0x00004100 is write in the first register, (0x00004100+0x2000=0x00006100) is write in the second register simultaneously.In ensuing fetching process, if be 1 according to the tracking information position of the index bit reading in fetching address, then control circuit cuts out tag memory, directly reading command from data-carrier store; If be 0 according to the tracking information position that the index bit in fetching address reads, then need access flag storer to carry out decision instruction Cache and whether hit.If Instruction Cache hits, then control circuit reading command from data-carrier store, and while the instruction of reading returns to processor cores, the tracking information position of corresponding row is set to 1; If Instruction Cache lacks, then control circuit reading command from primary memory, and the instruction of reading is write in Instruction Cache, the tracking information position of corresponding row is set to 1 simultaneously.Next, when not being in when fetching address within the program segment address scope in tracking information maintenance circuitry, control circuit is according to overflow control signal removal tracking information table, and revise the value of the first register and the second register, keep a correct corresponding relation all the time with tracking information table with the program segment address scope guaranteeing in tracking information maintenance circuitry.
Can find that the present invention uses tracking information position to carry out hit detection to Instruction Cache in advance by example above, decrease unnecessary tag memory access, thus effectively reduce the power consumption of Instruction Cache.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1., based on an instruction cache for zone bit access trace, comprise tracking information maintenance circuitry, tracking information table, control circuit, tag memory and data-carrier store, wherein:
The line number of described tracking information table is equal with the line number of described tag memory and described data-carrier store respectively, every a line of described tracking information table for storing a tracking information position, whether effective access trace representing the corresponding row whether existed described tag memory respectively of described tracking information position;
Described tracking information maintenance circuitry is used for exporting overflow control signal according to the program segment address scope in the branch direction inputted, branch target address, fetching address and described tracking information maintenance circuitry, the whether effective of described overflow control signal represents whether described fetching address or described branch target address are within described program segment address scope, and described tracking information maintenance circuitry comprises respectively:
Control register, for section first address and the section tail address of storing said program sector address scope;
Comparing unit, for according to described branch direction, described branch target address, described fetching address and described program segment address scope output branch overflow signals, branch's underflow signal and order underflow signal;
Or door, for exporting described overflow control signal according to described branch overflow signals, branch's underflow signal and order underflow signal;
Control circuit, for controlling the reading to described tag memory, and for safeguarding described tracking information table according to described overflow control signal according to described tracking information position.
2. the instruction cache based on zone bit access trace according to claim 1, wherein, described control register comprises:
First register, for the section first address of storing said program sector address scope;
Second register, for the section tail address of storing said program sector address scope.
3. the instruction cache based on zone bit access trace according to claim 1, wherein, described comparing unit comprises:
First comparing unit, it, by described branch target address and described section of first address being compared, exports described branch overflow signals;
Second comparing unit, it, by described branch target address and described section of tail address being compared, exports described branch underflow signal;
3rd comparing unit, it, by being compared in described fetching address and described section of tail address, exports described order underflow signal.
4. the instruction cache based on zone bit access trace according to claim 1, wherein, described tracking information position is effective, and described control circuit is arranged to:
Forbid reading described tag memory, and utilize described fetching address reading command from described data-carrier store.
5. the instruction cache based on zone bit access trace according to claim 1, wherein, described overflow control signal is effective, and described control circuit is also arranged to:
Under described branch overflow signals or the effective situation of described branch underflow signal, remove the content in described tracking information table, and using described branch target address as described section of first address stored in the first register, simultaneously using the capability value sum of described branch target address and instruction cache memory as described section of tail address stored in the second register, described capability value represents in units of byte;
In the effective situation of described order underflow signal, remove the content in described tracking information table, and described first register and described second register are reset.
6. the instruction cache based on zone bit access trace according to claim 3, wherein, it is backward branch instruction or forward-facing branch instruction that described branch direction is used to indicate branch instruction,
When described branch direction instruction branch instruction is backward branch instruction, described first comparing unit work, described control circuit cuts out the 3rd comparing unit;
When described branch direction instruction branch instruction is forward-facing branch instruction, described second comparing unit work;
When described branch direction instruction branch instruction be forward-facing branch instruction or branch instruction performs unsuccessfully, described 3rd comparing unit of described control circuit startup.
7. the instruction cache based on zone bit access trace according to claim 1, wherein, described tracking information position is invalid, and described control circuit is also arranged to:
Reading command from described data-carrier store or primary memory is also returned to processor cores;
When the instruction of reading returns to processor cores, the described tracking information position of corresponding row in described tracking information table is set to effectively.
8. the instruction cache based on zone bit access trace according to claim 1, wherein, described tracking information position is invalid, and described control circuit is also arranged to:
Described fetching address is utilized to read zone bit from described tag memory;
Judge whether the zone bit read mates with the zone bit in described fetching address;
In the event of a match, described fetching address reading command from the corresponding row of described data-carrier store is utilized;
In absence of such a match, utilize described fetching address reading command from primary memory, and the instruction of reading is write the corresponding row of described data-carrier store.
9. the instruction cache based on zone bit access trace according to claim 1, wherein, described control circuit is also arranged to:
From the corresponding row of described tracking information table, described tracking information position is read, to determine whether there is the access trace of the corresponding row to described tag memory according to described fetching address.
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| CN104765698B (en) * | 2015-03-17 | 2018-02-13 | 中国科学院声学研究所 | A kind of cache memory and road Forecasting Methodology |
| CN105677583B (en) * | 2015-12-31 | 2019-01-08 | 华为技术有限公司 | A kind of buffer memory management method and device |
| US9354885B1 (en) | 2016-01-08 | 2016-05-31 | International Business Machines Corporation | Selective suppression of instruction cache-related directory access |
| US9898296B2 (en) | 2016-01-08 | 2018-02-20 | International Business Machines Corporation | Selective suppression of instruction translation lookaside buffer (ITLB) access |
| CN105868126B (en) * | 2016-03-23 | 2018-09-18 | 中国电子科技集团公司第三十八研究所 | A kind of device and method improving instruction-cache hit rate |
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| US5307477A (en) * | 1989-12-01 | 1994-04-26 | Mips Computer Systems, Inc. | Two-level cache memory system |
| US6122709A (en) * | 1997-12-19 | 2000-09-19 | Sun Microsystems, Inc. | Cache with reduced tag information storage |
| CN1445661A (en) * | 2003-04-21 | 2003-10-01 | 杭州中天微系统有限公司 | Control logic for lowering power consumption of cache instructions |
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| CN103257850A (en) | 2013-08-21 |
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