CN102902346B - Method and device for reducing power consumption of instruction cache memory - Google Patents
Method and device for reducing power consumption of instruction cache memory Download PDFInfo
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- CN102902346B CN102902346B CN201210365854.0A CN201210365854A CN102902346B CN 102902346 B CN102902346 B CN 102902346B CN 201210365854 A CN201210365854 A CN 201210365854A CN 102902346 B CN102902346 B CN 102902346B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to method and device for reducing the power consumption of an instruction cache memory. The method comprises the steps of recording the history information executed by a branch instruction, generating a first chip selection signal according to the history information executed by the branch instruction and the current information of the branch instruction, processing according to the first chip selection signal and a second chip selection signal output by an instruction cache controller to obtain a chip selection control signal of a mark memory, and controlling according to the chip selection signal of the mark memory to decide whether to access the mark memory. Therefore, according to the method and the device provided by the invention, the access frequency to the mark memory in the program execution process can be decreased, and thus the integral power consumption of the instruction cache memory can be reduced.
Description
Technical field
The present invention relates to field of processors, particularly relate to a kind of method and the device that reduce power consumption of instruction cache memory.
Background technology
Along with the develop rapidly of integrated circuit technique, the speed of processor chips and integrated level are obtained for very large lifting, and the power problems brought thus also becomes very outstanding.A large amount of power consumption consumption can reduce the serviceable life of battery in portable set, and brings a lot of problem can to the power supply of processor, heat radiation and reliability.In the design of current digital signal processor, power consumption has become a very important index.Instruction cache (being called for short: Instruction Cache) is as the critical component improving processor cores fetching speed, be program most active part when running, the power consumption therefore effectively reducing Instruction Cache has great significance for the design of low power processor.
As shown in Figure 1, it is primarily of mark (tag) storer, data (data) storer and mode bit (state) composition for the Instruction Cache structure of the mode that is directly connected.As kernel access instruction Cache, tag storer reads zone bit tag according to the Index position of kernel address as address, and with the Tag bit comparison in kernel address, if equal, represent hit, kernel directly reads data from Instruction Cache; If unequal, represent not hit, at this moment can start the operation of an access main memory.Kernel can carry out a large amount of reading tag storage operation and compare operation, the power consumption that this process need consumption is a large amount of in the process of instruction fetch.If the number of times of access tag storer can be reduced, then effectively can reduce the power consumption of Instruction Cache.
In the article " A History-Based I-Cache for Low-Energy MultimediaApplications " that in August, 2002, the low power dissipation electron of No. 12-14 was delivered with the people such as Koji Inoue in design (ISLPED) meeting, propose a kind of Low-Power Instruction Cache method for designing based on procedural operation history information, the method and branch prediction techniques are combined closely.Its principle of work is: when Branch Target Instruction once performed and perform this Branch Target Instruction and do not occur during performing this Branch Target Instruction last time Instruction Cache lack time, access tag storer can be stopped.But this technology is combined closely with branch target buffer, when branch prediction and procedural operation history information updating occur simultaneously, processor pipeline there will be pause, causes processor performance to decline; When occurring that Instruction Cache access disappearance or branch target buffer content are replaced, need the procedural operation history information cleared all, this just requires the historical information of processor logging program operation again in follow-up fetching process, and in the recording process again of procedural operation history information, the access power consumption of processor due to the effective historical information already recorded cannot be utilized to eliminate unnecessary tag storer, thus reduce the service efficiency of procedural operation history information; For the digital signal processor not adopting branch prediction mechanism, setting up a branch predictor needs to increase very large hardware costs, and branch predictor itself also needs to consume a part of power consumption.
In the article " the instruction cache low power consumption method based on url history relation " that the interim Gong Shuai general of journal of Zhejiang university (engineering version) the 45th volume the 3rd in March, 2011 waits people to deliver, propose a kind of Low-Power Instruction Cache method for designing based on Instruction Cache history access links relation, the method needs in Instruction Cache, set up a history access links relation table.Its principle of work is: can according to the url history relation recorded in url history table in the process that program performs, and directly reading command from the data-carrier store of link, reduces the access of unnecessary tag storer.But the method exists following not enough: it needs to increase a url history relation table in Instruction Cache unit, can increase area and the design complexities of Instruction Cache like this, and url history relation table also can consume a part of power consumption.
Summary of the invention
The embodiment of the present invention proposes a kind of method and the device that reduce power consumption of instruction cache memory, can reduce the access times to tag memory in program process, thus reduces the overall power of instruction cache.
In first aspect, embodiments provide a kind of device reducing power consumption of instruction cache memory, comprising:
Tag memory control module, for recording the historical information that branch instruction performs, and the historical information performed according to described branch instruction and branch instruction current information generate the first chip selection signal;
Instruction cache module, comprises instruction cache controller, the tag memory be connected with described instruction cache controller and data-carrier store;
Wherein, whether the sheet that the second chip selection signal that described first chip selection signal and described instruction cache controller export obtains tag memory through process selects control signal, select control signal to control to conduct interviews to described tag memory by the sheet of described tag memory.
In second aspect, embodiments provide a kind of method reducing power consumption of instruction cache memory, described method is used for device as described in the first aspect of the invention, and described method comprises:
The historical information that record branch instruction performs;
The historical information performed according to described branch instruction and branch instruction current information generate the first chip selection signal;
Selecting control signal according to the second chip selection signal that described first chip selection signal and instruction cache controller export through processing the sheet obtaining tag memory, selecting control signal to control whether to conduct interviews to described tag memory by the sheet of described tag memory.
Method and apparatus provided by the invention can reduce the access times to tag memory in program process, thus reduces the overall power of instruction cache.
Accompanying drawing explanation
Fig. 1 is prior art Instruction Cache structural representation;
The instruction code fragment that Fig. 2 provides for the embodiment of the present invention;
The schematic diagram of the device of the reduction Instruction Cache power consumption that Fig. 3 provides for the embodiment of the present invention;
The course of work schematic diagram of device in Fig. 3 that Fig. 4 provides for the embodiment of the present invention;
The method flow diagram of the reduction Instruction Cache power consumption that Fig. 5 provides for the embodiment of the present invention;
The tag memory control module course of work process flow diagram that Fig. 6 provides for the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the specific embodiment of the invention is described in further detail.
First, the key concept in composition graphs 2 pairs of embodiment of the present invention does clearly sets forth, the instruction code fragment that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2:
Branch instruction: refer in program process, the instruction needing to jump to other local execution run into, comprise branch's jump instruction, cycling jump instruction sum functions calls, as shown in Figure 2, perform after flow process 1 and 2 presentation directives performs BRANCH1 and jump to the execution of Branch Target Instruction LOOP2 place, then BRANCH1 is branch instruction.
Branch instruction redirect success: refer in program process, run into branch instruction, and jump to this Branch Target Instruction place to perform, as shown in Figure 2, perform after flow process 1 and 2 presentation directives performs BRANCH1 and jump to the execution of Branch Target Instruction LOOP2 place, now claim branch instruction BRANCH1 redirect success.
Branch instruction redirect failure: refer in program process, run into branch instruction, does not jump to this Branch Target Instruction place and perform, but order performs instruction below.As the execution flow process 3 in Fig. 2, after instruction performs branch instruction BRANCH1, do not jump to Branch Target Instruction LOOP2 place and perform, but order performs instruction below, now claim branch instruction BRANCH1 redirect failure.
The schematic diagram of the device of the reduction Instruction Cache power consumption that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, described device is primarily of tag memory control module and Instruction Cache module composition.The historical information that tag memory control module performs for recording branch instruction, and the historical information performed according to described branch instruction and branch instruction current information generate the first chip selection signal.Instruction Cache module comprises Instruction Cache controller, the tag storer be connected with described Instruction Cache controller and data-carrier store; Wherein, whether the sheet that the second chip selection signal that described first chip selection signal and described Instruction Cache controller export obtains tag storer through process selects control signal, select control signal to control to conduct interviews to described tag storer by the sheet of described tag storer.
In Fig. 3, each significance signal is as follows: bt is for representing the successful information of the current redirect of branch instruction, and bt=1 represents the current redirect success of branch instruction; Bnt is for representing the information of the current redirect failure of branch instruction, and bnt=1 represents the current redirect failure of branch instruction; B is used for representing whether have branch instruction, and b=1 indicates branch instruction; T for the successful information of redirect before representing branch instruction, T=1 indicate this branch instruction before the successful information of redirect; NT for the information of redirect failure before representing branch instruction, NT=1 indicate this branch instruction before the information of redirect failure.It should be noted that, those skilled in the art can define the value meaning of each signal according to actual conditions.
In Fig. 3, the meaning of each device is as follows, and: D1-D4 is or door, and D5-D7 is and door, and D8 is not gate, and D9 is d type flip flop, wherein, plays retroactive effect with door D7, can play the effect of maintenance first chip selection signal.
The input of tag memory control module comprises branch instruction redirect pass signal, branch instruction redirect failure signal and branch instruction address, and output is the first chip selection signal.
Tag memory control module comprises branch instruction address queue (BIAQ), branch instruction history lists (BIH) and control circuit, wherein:
The BIAQ degree of depth is N, and data width is M(instruction address width), for storing branch instruction address.
The BIH degree of depth is N, and data width is 2bits, for the information of redirect failure before the successful information of redirect before recording branch instruction and branch instruction.
It should be noted that, those skilled in the art can define the size of parameter in BIAQ and BIH according to actual conditions.
It should be noted that, before branch instruction address before recording in BIAQ, the branch instruction that records in BIH, before the successful information of redirect and branch instruction, the information of redirect failure together constitutes the historical information that branch instruction performs.
The principle of work of the device that the embodiment of the present invention provides is: in the implementation of program, if the branch instruction of encountering, processor cores can send the signal of this branch instruction redirect success or redirect failure to tag memory control module, can send the address of this branch instruction simultaneously.When tag memory control module has detected branch instruction, it according to the address lookup BIAQ of this branch instruction, if equal with a certain item in BIAQ, can represent hit, if all unequal, represents not hit.
If BIAQ is not hit in the address of branch instruction, the information of this branch instruction redirect success or redirect failure by the address of this branch instruction stored in BIAQ, can be recorded in BIH by tag memory control module simultaneously.BIAQ adopts the writing mode of " first in first out ", namely the branch instruction address writing BIAQ at first can be replaced when the content of BIAQ needs to replace.
If the address hit BIAQ of branch instruction, BIH can read information T before this branch instruction and NT according to hiting signal,
If meet one of following condition:
(1) this branch instruction current redirect success and T=1;
(2) this branch instruction current redirect failure and NT=1,
Then represent that the target instruction target word of this branch instruction exists in Instruction Cache, now can stop the access to tag storer, directly instruction fetch from Instruction Cache.
If the address hit BIAQ of branch instruction, but do not meet above in two conditions, if then:
(1) the current redirect success of branch instruction, be then updated to 1 by the T in the BIH of correspondence;
(2) the current redirect failure of branch instruction, be then updated to 1 by the NT in the BIH of correspondence,
Make tag memory operation in normal condition simultaneously.
For ease of understanding, below for Fig. 4, concrete elaboration is done to above-mentioned principle of work.The course of work schematic diagram of device in Fig. 3 that Fig. 4 provides for the embodiment of the present invention, code snippet corresponding to the course of work in Fig. 4 as shown in Figure 2.As shown in Figure 4, wherein m-BRANCHn represents that branch instruction BRANCHn performs the time point in stream at the m time.Below in conjunction with Fig. 4 and Fig. 3, the course of work of the device that the embodiment of the present invention provides is elaborated:
Suppose that the degree of depth of BIAQ in tag memory control module is 2, instruction address width is 32bits, and is sky in BIAQ and BIH during assumed initial state, and the sheet of tag storer selects control signal Low level effective.The course of work then represented in Fig. 4 is as follows:
1-BRANCH1:tag memory control module has detected branch instruction, and the current redirect success of branch instruction, find not hit by inquiry BIAQ, as can be seen from Figure 3, be high level with an input signal bt of door D5, another input signal is low level, and known its exports as low level.Be low level with two input signals of door D6, known its exports as low level.With the output signal of door D5 be or the input signal of door D2 that known or door D2 exports as low level with the output signal of door D6.In addition, because b is high level, output low level after not gate D8, therefore, exports as low level with door D7.With the output signal of door D7 and or the output signal of door D2 is or the input signal of door D3, known or door D3 output low level, thus the first chip selection signal that d type flip flop D9 exports is low level, or the second chip selection signal that the output of door D4 is exported by Instruction Cache controller controls, tag storer is in normal operating conditions.Now the address BRANCH1 of this branch instruction is write BIAQ by tag memory control module, successful for redirect information is recorded in BIH.
2-BRANCH1:tag memory control module has detected branch instruction, and the current redirect success of branch instruction, hit is found by inquiry BIAQ, and the successful information record of redirect before finding that there is this branch instruction by inquiry BIH, as shown in Figure 4, the T=1 in the BIH that in BIAQ, BRANCH1 is corresponding, as can be seen from Figure 3, be high level with two input signals of door D5, known its exports as high level.Be or the input signal of door D2 that known or door D2 exports as high level with the output signal of door D5.Or the output signal of door D2 is or the input signal of door D3, known or door D3 exports as high level.Therefore after d type flip flop D9, the first chip selection signal of output is also high level, or the output of door D4 is high level, closes tag storer.
3-BRANCH1:tag memory control module has detected branch instruction, and the current redirect failure of branch instruction, hit is found by inquiry BIAQ, but by the information record of redirect failure before inquiry BIH discovery not this branch instruction, as can be seen from Figure 3, be high level with an input signal bnt of door D6, another input signal is low level, and known its exports as low level.Be low level with two input signals of door D5, known its exports as low level.With the output signal of door D5 be or the input signal of door D2 that known or door D2 exports as low level with the output signal of door D6.In addition, because b is high level, output low level after not gate D8, therefore, exports as low level with door D7.With the output signal of door D7 and or the output signal of door D2 is or the input signal of door D3, known or door D3 output low level, thus the first chip selection signal that d type flip flop D9 exports is low level, or the second chip selection signal that the output of door D4 is exported by Instruction Cache controller controls, tag storer is in normal operating conditions.Now the information of this branch instruction redirect failure is recorded in BIH by tag memory control module.
3-BRANCH2:tag memory control module has detected branch instruction, and the current redirect success of branch instruction, find not hit by inquiry BIAQ, as can be seen from Figure 3, be high level with an input signal bt of door D5, another input signal is low level, and known its exports as low level.Be low level with two input signals of door D6, known its exports as low level.With the output signal of door D5 be or the input signal of door D2 that known or door D2 exports as low level with the output signal of door D6.In addition, because b is high level, output low level after not gate D8, therefore, exports as low level with door D7.With the output signal of door D7 and or the output signal of door D2 is or the input signal of door D3, known or door D3 output low level, thus the first chip selection signal that d type flip flop D9 exports is low level, or the second chip selection signal that the output of door D4 is exported by Instruction Cache controller controls, tag storer is in normal operating conditions.Now the address BRANCH2 of this branch instruction is write BIAQ by tag memory control module, successful for redirect information is recorded in BIH.
4-BRANCH1:tag memory control module has detected branch instruction, and the current redirect failure of branch instruction, hit is found by inquiry BIAQ, and the information record of redirect failure before finding that there is this branch instruction by inquiry BIH, as shown in Figure 4, the NT=1 in the BIH that in BIAQ, BRANCH1 is corresponding, as can be seen from Figure 3, be high level with two input signals of door D6, known its exports as high level.Be or the input signal of door D2 that known or door D2 exports as high level with the output signal of door D6.Or the output signal of door D2 is or the input signal of door D3, known or door D3 exports as high level.Therefore by after d type flip flop D9, the first chip selection signal of output is also high level, or the output of door D4 is high level, closes tag storer.
4-BRANCH2:tag memory control module has detected branch instruction, and the current redirect success of branch instruction, hit is found by inquiry BIAQ, and the successful information record of redirect before finding that there is this branch instruction by inquiry BIH, as shown in Figure 4, the T=1 in the BIH that in BIAQ, BRANCH2 is corresponding, as can be seen from Figure 3, be high level with two input signals of door D5, known its exports as high level.Be or the input signal of door D2 that known or door D2 exports as high level with the output signal of door D5.Or the output signal of door D2 is or the input signal of door D3, known or door D3 exports as high level.Therefore after d type flip flop D9, the first chip selection signal of output is also high level, or the output of door D4 is high level, closes tag storer.
5-BRANCH1:tag memory control module has detected branch instruction, and the current redirect failure of branch instruction, hit is found by inquiry BIAQ, and the information record of redirect failure before finding that there is this branch instruction by inquiry BIH, as shown in Figure 4, the NT=1 in the BIH that in BIAQ, BRANCH1 is corresponding, as can be seen from Figure 3, be high level with two input signals of door D6, known its exports as high level.Be or the input signal of door D2 that known or door D2 exports as high level with the output signal of door D6.Or the output signal of door D2 is or the input signal of door D3, known or door D3 exports as high level.Therefore by after d type flip flop D9, the first chip selection signal of output is also high level, or the output of door D4 is high level, closes tag storer.
5-BRANCH2:tag memory control module has detected branch instruction, and the current redirect failure of branch instruction, hit is found by inquiry BIAQ, but by the information record of redirect failure before inquiry BIH discovery not this branch instruction, as can be seen from Figure 3, be high level with an input signal bnt of door D6, another input signal is low level, and known its exports as low level.Be low level with two input signals of door D5, known its exports as low level.With the output signal of door D5 be or the input signal of door D2 that known or door D2 exports as low level with the output signal of door D6.In addition, because b is high level, output low level after not gate D8, therefore, exports as low level with door D7.With the output signal of door D7 and or the output signal of door D2 is or the input signal of door D3, known or door D3 output low level, therefore, after d type flip flop D9, the first chip selection signal exported also is low level, or the second chip selection signal that the output of door D4 is exported by Instruction Cache controller controls, tag storer is in normal operating conditions.Now the information of this branch instruction redirect failure is recorded in BIH by tag memory control module.
5-BRANCH3:tag memory control module has detected branch instruction, and the current redirect success of branch instruction, find not hit by inquiry BIAQ, as can be seen from Figure 3, be high level with an input signal bt of door D5, another input signal is low level, and known its exports as low level.Be low level with two input signals of door D6, known its exports as low level.With the output signal of door D5 be or the input signal of door D2 that known or door D2 exports as low level with the output signal of door D6.In addition, because b is high level, output low level after not gate D8, therefore, exports as low level with door D7.With the output signal of door D7 and or the output signal of door D2 is or the input signal of door D3, known or door D3 output low level, thus the first chip selection signal that known d type flip flop D9 exports is low level, or the second chip selection signal that the output of door D4 is exported by Instruction Cache controller controls, tag storer is in normal operating conditions.Now the address BRANCH3 of this branch instruction is write BIAQ by tag memory control module, successful for redirect information is recorded in BIH.Because now BIAQ has been in full state, need wherein a line to replace away, the present embodiment adopts the mode (also can adopt other modes) of " first in first out ", replaces away, and remove the information in BIH corresponding to BRANCH1 by BRANCH1.
6-BRANCH3:tag memory control module has detected branch instruction, and the current redirect success of branch instruction, hit is found by inquiry BIAQ, and the successful information record of redirect before finding that there is this branch instruction by inquiry BIH, as shown in Figure 4, the T=1 in the BIH that in BIAQ, BRANCH3 is corresponding, as can be seen from Figure 3, be high level with two input signals of door D5, known its exports as high level.Be or the input signal of door D2 that known or door D2 exports as high level with the output signal of door D5.Or the output signal of door D2 is or the input signal of door D3, known or door D3 exports as high level.Therefore after d type flip flop D9, the first chip selection signal of output is also high level, or the output of door D4 is high level, closes tag storer.
7-BRANCH3:tag memory control module has detected branch instruction, and the current redirect failure of branch instruction, hit is found by inquiry BIAQ, but by the information record of redirect failure before inquiry BIH discovery not this branch instruction, as can be seen from Figure 3, be high level with an input signal bnt of door D6, another input signal is low level, and known its exports as low level.Be low level with two input signals of door D5, known its exports as low level.With the output signal of door D5 be or the input signal of door D2 that known or door D2 exports as low level with the output signal of door D6.In addition, because b is high level, output low level after not gate D8, therefore, exports as low level with door D7.With the output signal of door D7 and or the output signal of door D2 is or the input signal of door D3, known or door D3 output low level, therefore, after d type flip flop D9, the first chip selection signal exported also is low level, or the second chip selection signal that the output of door D4 is exported by Instruction Cache controller controls, tag storer is in normal operating conditions.Now the information of this branch instruction redirect failure is recorded in BIH by tag memory control module.
Comprehensive said process is known: when an execution branch instruction, if this branch instruction current redirect success and the successful information record of redirect before having this branch instruction, if or this branch instruction current redirect failure and the information record of redirect failure before having this branch instruction, then illustrate that the target instruction target word of this branch instruction exists in Instruction Cache, can directly instruction fetch from Instruction Cache, and do not need to conduct interviews to tag storer; If this branch instruction current redirect success and the not successful information record of redirect before this branch instruction, if or this branch instruction current redirect failure and the information record of not redirect failure before this branch instruction, then illustrate that the target instruction target word of this branch instruction does not exist in Instruction Cache, now need to conduct interviews to tag storer.Current execution branch instruction and on once perform this branch instruction during to be replaced out the situation of Instruction Cache by new instruction block if there is target instruction target word block, program may perform makes mistakes, therefore when using of the present invention, demand fulfillment condition: the instruction block size of program can not be greater than the size of Instruction Cache.After meeting this condition, current execution branch instruction and on once perform this branch instruction during would not occur that target instruction target word block is replaced out the situation of Instruction Cache by new instruction block, program would not perform makes mistakes.
It should be noted that, those skilled in the art also can adopt other circuit realiration above-mentioned functions, are not limited to the circuit provided in embodiment of the present invention Fig. 3.
What above-described embodiment described is that tag memory control module exports the first chip selection signal according to the information of branch instruction in the situation of input signal, branch instruction hit BIAQ and BIH, the sheet that the second chip selection signal that Instruction Cache controller in this first chip selection signal and instruction Cache module exports obtains tag storer through process selects control signal, control signal is selected to control to conduct interviews the need of to tag storer by this sheet, the access to tag storer in program process can be reduced thus, thus effectively can reduce the power consumption of Instruction Cache.
The method for reducing Instruction Cache power consumption that following embodiment describes.The method flow diagram of the reduction Instruction Cache power consumption that Fig. 5 provides for the embodiment of the present invention.As shown in Figure 5, the embodiment of the present invention comprises the following steps:
Step 501, the historical information that tag memory control module record branch instruction performs.
Particularly, if the branch instruction address of input does not hit BIAQ, then by this branch instruction address stored in BIAQ, and record the information of this branch instruction redirect success or redirect failure.If the branch instruction address hit BIAQ of input, if this branch instruction current redirect success and the not successful information record of redirect before this branch instruction, if or this branch instruction current redirect failure and the information record of not redirect failure before this branch instruction, then upgrade the information of this branch instruction redirect success or redirect failure in BIH.
Step 502, the historical information performed according to described branch instruction and branch instruction current information generate the first chip selection signal.
The information of branch instruction address before the historical information that branch instruction performs refers to, redirect failure before the successful information of redirect and described branch instruction before described branch instruction.
Branch instruction current information refers to the information of current branch instruction address, the successful information of the current redirect of described branch instruction or the current redirect failure of described branch instruction.
Step 503, whether the sheet that the second chip selection signal that the first chip selection signal exported according to tag memory control module and Instruction Cache controller export obtains tag storer through process selects control signal, select control signal to control to conduct interviews to described tag storer by the sheet of described tag storer.
Below in conjunction with Fig. 6, above-mentioned steps 502 and step 503 are further elaborated, the tag memory control module course of work process flow diagram that Fig. 6 provides for the embodiment of the present invention.As shown in Figure 6, said method comprising the steps of:
Step 601, in program process, runs into branch instruction.
Step 602, the redirect success of this branch instruction that tag memory control module receiving processor kernel sends or redirect failure signal, this branch instruction address, and detect this branch instruction address and whether hit BIAQ.
Step 603, if branch instruction address does not hit BIAQ, the information of this branch instruction redirect success or redirect failure by this branch instruction address stored in BIAQ, can be recorded in BIH by tag memory control module simultaneously.BIAQ adopts the writing mode of " first in first out ", and namely the branch address writing BIAQ at first can be replaced when the content of BIAQ needs to replace, BIAQ also can adopt other writing modes.
Step 604, if branch instruction address hit BIAQ, BIH can read information before this branch instruction according to hiting signal, whether interpretation can close the access to tag storer.
Step 605, if meet one of following condition:
(1) this branch instruction current redirect success and the successful information record of redirect before having this branch instruction;
(2) this branch instruction current redirect failure and the information record of redirect failure before having this branch instruction,
Then represent that the target instruction target word of this branch instruction exists in Instruction Cache, now tag memory control module generates one and can close the control signal of tag storer and export, and closes tag storer.
Step 606, if branch instruction address hit BIAQ, but does not meet above in two conditions, if then:
(1) the current redirect success of branch instruction, be then recorded in BI H by the successful information of this branch instruction redirect;
(2) the current redirect failure of branch instruction, be then recorded in BIH by the information of this branch instruction redirect failure,
The control signal that now tag Memory Controller CMOS macro cell one is invalid also exports, and tag storer normally works.
Comprehensive said process is known: if branch instruction current redirect success and the successful information record of redirect before having this branch instruction, if or branch instruction current redirect failure and the information record of redirect failure before having this branch instruction, then illustrate that the target instruction target word of this branch instruction exists in Instruction Cache, can directly instruction fetch from Instruction Cache, and do not need to conduct interviews to tag storer; If branch instruction current redirect success and the not successful information record of redirect before this branch instruction, if or branch instruction current redirect failure and the information record of not redirect failure before this branch instruction, then illustrate that the target instruction target word of this branch instruction does not exist in Instruction Cache, now need to conduct interviews to tag storer.
The method for reducing Instruction Cache power consumption that above-described embodiment describes, tag memory control module is according to input signal, in the branch instruction hit situation of BIAQ and BIH, the information of branch instruction exports the first chip selection signal, the sheet that the second chip selection signal that Instruction Cache controller in this first chip selection signal and instruction Cache module exports obtains tag storer through process selects control signal, control signal is selected to control to conduct interviews the need of to tag storer by this sheet, the method can reduce the access to tag storer in program process, thus effectively can reduce the overall power of Instruction Cache.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
In conjunction with the software module that the method step of embodiment disclosed herein description can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. reduce a device for power consumption of instruction cache memory, it is characterized in that, comprising:
Tag memory control module, for recording the historical information that branch instruction performs, and the historical information performed according to described branch instruction and branch instruction current information generate the first chip selection signal;
Instruction cache module, comprises instruction cache controller, the tag memory be connected with described instruction cache controller and data-carrier store;
Wherein, the instruction block size of program can not be greater than the size of instruction cache module, whether the sheet that the second chip selection signal that described first chip selection signal and described instruction cache controller export obtains tag memory through process selects control signal, select control signal to control to conduct interviews to described tag memory by the sheet of described tag memory.
2. device as claimed in claim 1, is characterized in that, the information of redirect failure before the successful information of redirect and described branch instruction before branch instruction address, described branch instruction before the historical information that described branch instruction performs refers to.
3. device as claimed in claim 1, is characterized in that, described branch instruction current information refers to the information of current branch instruction address, the successful information of the current redirect of described branch instruction or the current redirect failure of described branch instruction.
4. the device as described in claim 1,2 or 3, it is characterized in that, described tag memory control module comprises the branch instruction address queue storing branch instruction address, the branch instruction history lists recording branch instruction redirect success and redirect failure information in described branch instruction address queue and control circuit;
If the branch instruction address of input does not hit described branch instruction address queue, the information of described branch instruction redirect success or redirect failure stored in described branch instruction address queue, and is recorded in described branch instruction history lists by described tag memory control module by described branch instruction address;
If the branch instruction address of input hits described branch instruction address queue, if described branch instruction current redirect success and the successful information record of redirect before having described branch instruction, if or described branch instruction current redirect failure and the information record of redirect failure before having described branch instruction, then described branch instruction address queue and described branch instruction history lists remain unchanged; If described branch instruction current redirect success and the successful information record of redirect before not having described branch instruction, if or described branch instruction current redirect failure and the information record of redirect failure before not having described branch instruction, then described tag memory control module upgrades the information of branch instruction redirect success or redirect failure described in described branch instruction history lists.
5. reduce a method for power consumption of instruction cache memory, described method is used for the device as described in any one of Claims 1-4, and it is characterized in that, described method comprises:
The historical information that record branch instruction performs;
The historical information performed according to described branch instruction and branch instruction current information generate the first chip selection signal;
Selecting control signal according to the second chip selection signal that described first chip selection signal and instruction cache controller export through processing the sheet obtaining tag memory, selecting control signal to control whether to conduct interviews to described tag memory by the sheet of described tag memory;
Wherein, the instruction block size of program can not be greater than the size of instruction cache.
6. method as claimed in claim 5, is characterized in that, the information of redirect failure before the successful information of redirect and described branch instruction before branch instruction address, described branch instruction before the historical information that described branch instruction performs refers to.
7. the method as described in claim 5 or 6, is characterized in that, described branch instruction current information refers to the information of current branch instruction address, the successful information of the current redirect of described branch instruction or the current redirect failure of described branch instruction.
8. method as claimed in claim 7, is characterized in that, the historical information that described record branch instruction performs comprises further:
If described branch instruction address does not hit branch instruction address queue, then by described branch instruction address stored in described branch instruction address queue, and record the information of described branch instruction redirect success or redirect failure;
If described branch instruction address hits described branch instruction address queue, if described branch instruction current redirect success and the successful information record of redirect before not having described branch instruction, if or described branch instruction current redirect failure and the information record of redirect failure before not having described branch instruction, then upgrade the information of branch instruction redirect success or redirect failure described in described branch instruction history lists.
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| CN101329589A (en) * | 2008-07-28 | 2008-12-24 | 北京中星微电子有限公司 | Control system and method of low power consumption read-write register |
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| CN101114207A (en) * | 2007-08-03 | 2008-01-30 | 东南大学 | Method for realizing shadow stack memory on picture and circuit thereof |
| CN101329589A (en) * | 2008-07-28 | 2008-12-24 | 北京中星微电子有限公司 | Control system and method of low power consumption read-write register |
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