CN101114207A - Method for realizing shadow stack memory on picture and circuit thereof - Google Patents
Method for realizing shadow stack memory on picture and circuit thereof Download PDFInfo
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Abstract
The invention discloses a method and a circuit of realizing on-chip shadow stack memory which relate to a stack operation method inside a microprocessor and a storage circuit. The invention comprises an on-chip shadow stack memory, a configuration register, a chip selection circuit, an address compare circuit, an address decoding circuit, a storage controller, an attached memory and so on. By using a dynamic configuration method, the invention maps the data of a stack segment unit which is accessed with high frequency in the attached memory onto the on-chip shadow stack memory and accesses the on-chip shadow stack memory when the microprocessor is conducting the stack operation. Therefore, the problem that a memory page is deleted because of the stack accessing is avoided and the unnecessary page switching time is reduced. At the same time, by using the on-chip shadow stack memory, the storage power consumption is reduced; the running speed of the microprocessor is accelerated, thus leading the on-chip system performance to be greatly increased; and the problems of a current handheld terminal and a consumer electronic product on the performance and power consumption are solved.
Description
One, technical field
The present invention relates to a kind of memory control methods and circuit, relate in particular to a kind of Method and circuits of realizing shadow stack memory on picture.
Two, background technology
Current embedded system, particularly SOC (system on a chip) (System-On-a-chip) just more and more are applied in handheld device and the consumer electronics, as mobile phone, MP4 player, PS2 etc.These are used not only needs embedded system to have very high performance to support complicated day by day functional requirement, and needs the continuous power consumption that reduces to realize working long hours of equipment.Therefore, performance and power consumption become two key problems of embedded system research.
In the typical embedded system applies, processor instruction fetch always and data, and realize the operation of program by storehouse.In this course, processor needs constantly visit chip external memory, as SDRAM/DRAM (Synchronous Dynamic Random Access Memory/Dynamic RandomAccess Memory, synchronous DRAM/dynamic RAM).And chip external memories such as SDRAM/DRAM are the form tissues with the page, and the size of each page is generally 512Bytes～2048Bytes.When processor is visited SDRAM/DRAM, at first need activation command Ac activate the page at the visit data/instruction of wanting or storehouse place, the content of this page is stored in the sense amplifier just can be accessed to, activation manipulation needs the time At (when bus frequency is 133MHz) of 2～4 clock period usually, as shown in Figure 1.If read chip external memory, also need an extra stand-by period, promptly CAS waits for, is generally 2～3 clock period, if write operation then can directly be write in the external memory storage.When processor during at access sdram next time/DRAM, if data/commands that will visit this moment or storehouse be not in sense amplifier, need earlier the content in the sense amplifier to be write back among the SDRAM/DRAM by precharge command Pr, and then choose the page that to visit, and place it in the sense amplifier by activation command Ac, precharge operation needs the time Pt (when bus frequency is 133MHz) of 2～4 clock period usually, as shown in Figure 2.
Usually, the layout of the final code of program is to instruct up front, and the back is followed by global data.When program run, at first instruction and data is loaded in the storer, the start address and the size of storehouse is set when program run then.The storehouse operated by rotary motion is in the back of data, and the program layout during operation as shown in Figure 3.In program operation process, the visit of instruction is more continuous, so when carrying out instruction fetch operation, can sequential read instruction fetch on a page that activates.When run into the page be read finish, executive chairman's jump instruction or visit be when the data in this page or storehouse, the chip external memory page to occur does not hit, the operation of need skipping this moment, the page no-hit probability that produces during wherein with visit data or storehouse is the highest.Because data are linked to the back of instruction code usually, storehouse then often is set at ending place of data, thus data and storehouse not and instruction leave in the same page.When visit data or storehouse, the page often takes place not hit, need orders such as precharge and activation to the external memory storage operation of skipping, increased the access time, the delay that has caused program to carry out.
Some researchists have proposed on-chip memory (SPM) to this, some data commonly used by static analysis after, employing linker or compiler with valuable instruction or data load in SPM.Because SPM is positioned at chip internal, thus to it visit without any need for stand-by period (no CAS wait for), the situation of skipping can not appear, on-chip memory normally is made up of RAM on the sheet.
The whole stack area that traditional SPM design towards storehouse normally uses program is all left among the SPM, to quicken the access speed to storehouse, reduces the operation of skipping that produces because of stack accessing simultaneously.If but the storehouse of program uses address realm very big, then needs a large amount of SPM capacity to support.
Three, summary of the invention
The objective of the invention is to overcome the deficiency of prior art, a kind of method and circuit thereof of realizing shadow stack memory on picture is provided, adopt the on-chip memory of low capacity, the dynamic-configuration stack address, the latency delays time of storer when reducing the storehouse visit, thus the speed of microprocessor operation improved.
Above-mentioned purpose of the present invention is realized by following technical scheme:
A kind of method that realizes shadow stack memory on picture of the present invention, including processor cores links to each other with chip external memory by bus, finish access control by memory controller to chip external memory, shadow stack memory on picture adopts and is divided into the multisegment mode storage, and be provided with the first address that the configuration register identical with number of fragments deposited each section, address decoding circuitry is delivered to through bus in the address of visit chip external memory stack cell, address comparison circuit is relatively from the address of wanting storage unit access of address decoding circuitry and each section first address in the configuration register, comparative result is delivered to chip select circuit be used to select chip external memory or shadow stack memory on picture, finish visit to storage unit in chip external memory or the shadow stack memory on picture, select a correspondent section in the shadow stack memory on picture and the respective memory unit in the section with the address of address bus in section first address and the bus in the configuration register as section bias internal amount, the read-write control signal of shadow stack memory on picture is from memory controller.
Shadow stack memory on picture mapping configuration phase: the processor cores execution command reads the section first address content of configuration register by bus, and the content that chip external memory has been mapped to shadow stack memory on picture relays gets back to corresponding storage unit in the chip external memory.Reset the section first address content of configuration register as required, and with the content map of the corresponding stack segment of chip external memory in shadow stack memory on picture, the described content that chip external memory has been mapped to shadow stack memory on picture relays gets back in the chip external memory and the content map of the corresponding stack segment of chip external memory can be adopted processor cores execution command, hardware interrupts mode or dma mode transmission in shadow stack memory on picture.
Shadow stack memory on picture working stage: when processor cores execution stack operational order or hardware interrupts are carried out stack manipulation, to bus application read-write chip external memory stack segment data, address decoding circuitry is carried out address resolution with the address of processor cores application visit, and judge by address comparison circuit whether the current address of visiting is identical with some contents of configuration register, identical then chip select circuit produces selects the shadow stack memory on picture signal, and the stacked memory section conducts interviews on that sheet that the selection address coincide; Otherwise chip select circuit produce to be selected the signal of chip external memory, finishes visit to external memory storage by memory controller.
Described a kind of circuit of realizing the shadow stack memory on picture method as shown in Figure 4, includes bus, chip external memory, memory controller, address decoding circuitry, chip select circuit, configuration register and shadow stack memory on picture.Bus is connected with chip external memory, and memory controller controls is to the visit of chip external memory.Address decoder is accepted the address signal that bus is come, one road input end of address comparison circuit is linked in its output, the signal of another road input end of address comparison circuit is from configuration register, chip select circuit is linked in its output, configuration register carries out first address configuration by processor cores to it by bus, the two-way output signal of chip select circuit, one the tunnel for selecting the chip external memory signal to deliver to memory controller, shadow stack memory on picture is delivered to for selecting the shadow stack memory on picture signal in another road, shadow stack memory on picture is linked in another road output of configuration register ground, and shadow stack memory on picture also links to each other with bus.
Shadow stack memory on picture adopts and is divided into the multisegment mode storage, the setting of configuration register quantity is identical with the shadow stack memory on picture number of fragments, it is used to deposit the first address of each section of shadow stack memory on picture, address decoding circuitry is delivered to through bus in the address of data in the visit chip external memory storehouse, address comparison circuit is relatively from the address of wanting stack accessing of address decoding circuitry and each section first address in the configuration register, comparative result is delivered to chip select circuit be used to select chip external memory or shadow stack memory on picture, finish visit chip external memory or shadow stack memory on picture.
During shadow stack memory on picture work, when processor cores during to bus application read-write chip external memory stacked data, the address that the processor cores application that address decoding circuitry is come bus is visited is carried out address resolution and is outputed to address comparison circuit, address comparison circuit judges that the current address of visiting is whether identical with some contents that configuration register is sent here, identical then chip select circuit produces selects the shadow stack memory on picture signal, and that shadow stack memory on picture section of selecting the address to coincide conducts interviews; Otherwise chip select circuit produce to be selected the signal of chip external memory, finishes visit to external memory storage by memory controller.
The capacity of general shadow stack memory on picture can be 512 bytes, is divided into four sections, and the capacity of each section is 128 bytes.Configuration register have four corresponding with four sections of shadow stack memory on picture respectively.Shadow stack memory on picture can adopt static RAM, and simultaneously, it has the boundary alignment requirement, so only need compare the address more than the border relatively the time, does like this and can accelerate comparison speed, and the hardware that simplifies comparator circuit is realized.
The visit of storehouse its feature instantiation on the local address is a continuity, but the address usable range of storehouse is very big, and this scope in each address be not average use, so general performance is a discreteness.Advantage of the present invention and effect provide a kind of method and circuit thereof of realizing shadow stack memory on picture, have adopted to have the shadow feature and store the less high speed shadow stack memory on picture of area to shine upon the stack address with high access frequency.This shadow stack memory on picture is organized in the mode of section, and is different with common on-chip memory (Scratch-Pad-Memory is called for short SPM), and its actual address is also invisible, but can dispose the first address of each section.When processor cores has access to the sector address that stacked memory disposed on the sheet, will directly visit this shadow stack memory on picture.Section mapping by the small size on-chip memory, make the stack address of high-frequency visit in the high speed on-chip memory, to carry out, reduced access times, improved the speed of carrying out to a great extent, and reduced the power consumption that external memory access is brought external memory storage.
Four, description of drawings
Fig. 1 is the read-write sequence figure of SDRAM/DRAM page or leaf when hitting;
Fig. 2 is the read-write sequence figure of SDRAM/DRAM page or leaf when not hitting;
Layout when Fig. 3 is general procedure static topology and operation;
Fig. 4 is a shadow stack memory on picture circuit diagram of the present invention;
Fig. 5 is a shadow stack memory on picture mapping logic graph of a relation of the present invention;
Fig. 6 is this general procedure process flow diagram;
Fig. 7 is the process flow diagram after this general procedure carries out storehouse mapping configuration;
Fig. 8 is the frequency of utilization figure on each stack address of MPEG-4 decoding program;
Fig. 9 is the time series chart that MPEG-4 decoding program stack address uses.
The reference numeral explanation
At:: activate the stand-by period;
Pt: precharge stand-by period;
CAS: read operation stand-by period;
Ac: activation command;
Pr: precharge command;
RD: read operation;
WR: write operation;
Dx: the transmission data on the bus.
Five, embodiment
Embodiment 1: below in conjunction with accompanying drawing and embodiment the present invention being described in further detail, is example with MPEG-4 multimedia decoding program.
At first carry out static analysis, Fig. 6 is the general procedure flow process, it is set up the trace model that a program code is carried out, be used for recording instruction and the data visit situation on storer, then program is loaded on this model and moves, to draw memory access information, the height of frequency according to visit sorts to instruction and data afterwards, and the instruction and data that will have a high access frequency is labeled as important instruction and data.
Fig. 8 is the frequency of utilization figure on each stack address of MPEG-4 multimedia decoding program, and as can be seen, the address usable range of storehouse is very big, and the frequency of utilization of each address is all different, and some places are often used, and some places seldom use.Fig. 9 is the time series chart that MPEG-4 decoding program stack address uses, as can be seen from the figure, storehouse use at the beginning concentrates on about the 0x308F FC18 of high address place, along with the operation of program, stack address uses and has forwarded between relatively low the address 0x308F F254 of place and 0x308FF63C.This is because program is being carried out initialization and set up MPEG-4 decoding environment at the beginning, the use that relatively concentrate this moment storehouse; Along with the beginning of decoding, deepening continuously of function called, and also just constantly extend to low address the address of storehouse.Decoding is a process of constantly calling the decoding storehouse repeatedly, and because of the complexity of decoding, the temporary variable that a large amount of local variables occurred and preserve because of computation requirement in decoding makes the use of storehouse become very frequent.
By the operating position analysis of MPEG-4 multimedia decoding program on storehouse, program is to discrete, the local continuous access characteristics of the integral body of storehouse, this specific character according to the storehouse visit, selection have high rate of people logging in, visit continuously and the reference address place of often repeating as the visit optimization objects, this sector address is mapped on the shadow stack memory on picture.When normal the use, stacked memory is invisible for the programmer on the sheet, and it is a shadow memory, class CACHE structure.In former MPEG-4 multimedia decoding program, insert stack segment mapping configurator piece, as shown in Figure 7, original program is dynamically carried out stack segment mapping, make the storage unit of the corresponding stack segment address realm on the chip external memory be replaced by shadow stack memory on picture.And in ensuing storehouse visit, directly visit shadow stack memory on picture rather than chip external memory, shadow stack memory on picture mapping logic graph of a relation as shown in Figure 5.The capacity of section is decided according to range of application, is 128Bytes as the capacity of each section.
The configuration of configuration register content is to be arranged in the stack segment of the insertion mapping configurator piece, after program is carried out the trace model operation by code, will generate the use information of a stack address; Determine which stack address needs according to this information then and carry out the on-chip memory mapping.During mapping, shadow stack memory on picture can copy the content of that section chip external memory that will shine upon in that segment memory that shadow stack memory on picture disposes.When mapping cancellation, in order to guarantee the integrality of data in the mapping address, shadow stack memory on picture can copy back its content of on-chip memory in the corresponding chip external memory again.The present invention is provided with four configuration registers, and flexible configuration as required during use promptly can be carried out a plurality of configurations simultaneously, also can carry out individual configuration.
Shadow stack memory on picture adopts the form tissue of section, is realized by the value of setting configuration register by program.The value of program setting is the first address that needs to shine upon stack segment in the corresponding chip external memory.Configuration register is corresponding with the section of on-chip memory, i.e. the corresponding one section on-chip memory of each configuration register.In shadow stack memory on picture, if four configuration registers are arranged, on-chip memory at most also just is divided into four sections so.Storer is continuous physically, and promptly four sections have been formed a complete on-chip memory.But when logical access, then present different sections according to the first address that configuration register disposed.As: when only disposing a configuration register, then whole on-chip memory is a section, the first address of this on-chip memory is the first address in the configuration register, it will shine upon the address of corresponding chip external memory with it, and the size of mapping capacity is the size of whole on-chip memory just.When having set the value of two configuration registers, on-chip memory has been equally divided into two sections, when four configuration registers all are set, each configuration register correspondence 1/4th on-chip memory.Shadow stack memory on picture is organized in the mode of segmentation, and the quantity of size of each section and section designs according to practical application, and every section size is between 128Bytes～512Bytes usually.Each section on-chip memory all has independently first address, and this first address needs the programmer to dispose.Be provided with a certain section first address when program after, when processor cores conducts interviews to this address, content that will this section of visit shadow stack memory on picture, rather than the content in the chip external memory, i.e. chip external memory conductively-closed on this sector address.The programmer can optionally change the first address of shadow stack memory on picture according to the frequent degree of the visit of chip external memory address with carry out sequence, allows them the memory block of chip external memory is shone upon and be replaced.Here the map addresses scope between the shadow stack memory on picture of it should be noted that can not have overlapping, and the address of mapping needs the 16Bytes boundary alignment, to make things convenient for the realization of address chip select circuit.
When storehouse reference address that processor cores sends is relatively dropping in the mapping scope of shadow stack memory on picture the discovery address that will visit in back through address comparator, then processor cores is directly carried out accessing operation from shadow stack memory on picture.During visit, at first obtain the correspondent section of shadow stack memory on picture, the current address is deducted address (i.e. the first address of this section) in this configuration register, the section of drawing bias internal amount by corresponding configuration register.Then this side-play amount is added the sector address of configuration register correspondence, promptly may have access to correct stack content (if i.e. this moment visit is second section, just since second segment memory locate add that side-play amount obtains correct address).If the storehouse reference address that processor cores sends is relatively being found not in the mapping scope at shadow stack memory on picture, then by memory controller visit chip external memory the back through address comparator.
After adopting shadow stack memory on picture, make processor accelerate visit to storehouse, reduced the time delay of having been brought because of switching the page back and forth between instruction and the storehouse when chip external memory is visited, accelerated the execution speed of system.Simultaneously because the operation that has reduced access external memory and skipped, make the power consumption of chip external memory also along with reduction.
Claims (4)
1. method that realizes shadow stack memory on picture, including processor cores links to each other with chip external memory by bus, finish access control by memory controller to chip external memory, it is characterized in that: shadow stack memory on picture adopts and is divided into the multisegment mode storage, and be provided with the first address that the configuration register identical with number of fragments deposited each section, address decoding circuitry is delivered to through bus in the address of visit chip external memory stack cell, address comparison circuit is relatively from the address of wanting storage unit access of address decoding circuitry and each section first address in the configuration register, comparative result is delivered to chip select circuit be used to select chip external memory or shadow stack memory on picture, finish visit to storage unit in chip external memory or the shadow stack memory on picture, select a correspondent section in the shadow stack memory on picture and the respective memory unit in the section with the address of address bus in section first address and the bus in the configuration register as section bias internal amount, the read-write control signal of shadow stack memory on picture is from memory controller; Shadow stack memory on picture mapping configuration phase: the processor cores execution command reads the section first address content of configuration register by bus, and the content that chip external memory has been mapped to shadow stack memory on picture relays gets back in the chip external memory; Reset the content of configuration register as required, and with the content map of the corresponding stack segment of chip external memory in shadow stack memory on picture; The described content that chip external memory has been mapped to shadow stack memory on picture relay get back in the chip external memory and with the content map of the corresponding stack segment of chip external memory in shadow stack memory on picture, can adopt processor cores execution command, hardware interrupts mode or dma mode transmission; Shadow stack memory on picture working stage: when processor cores execution stack operational order or hardware interrupts are carried out stack manipulation, to bus application read-write chip external memory stack segment data, address decoding circuitry is carried out address resolution with the address of processor cores application visit, and judge by address comparison circuit whether the current address of visiting is identical with some contents of configuration register, identical then chip select circuit produces selects the shadow stack memory on picture signal, and the stacked memory section conducts interviews on that sheet that the selection address coincide; Otherwise chip select circuit produce to be selected the signal of chip external memory, finishes visit to external memory storage by memory controller.
2. according to the described a kind of circuit of realizing the shadow stack memory on picture method of claim 1, include bus, chip external memory, memory controller, bus is connected with chip external memory, memory controller controls is to the visit of chip external memory, and its feature also includes address decoding circuitry, chip select circuit, configuration register and shadow stack memory on picture; Address decoder is accepted the address signal that bus is come, one road input end of address comparison circuit is linked in its output, the signal of another road input end of address comparison circuit is from configuration register, chip select circuit is linked in its output, configuration register is put number by processor cores to it by bus, the two-way output signal of chip select circuit, one the tunnel for selecting the chip external memory signal to deliver to memory controller, shadow stack memory on picture is delivered to for selecting the shadow stack memory on picture signal in another road, shadow stack memory on picture is linked in another road output of configuration register ground, and shadow stack memory on picture also links to each other with bus; Shadow stack memory on picture adopts and is divided into the multisegment mode storage, the setting of configuration register quantity is identical with the shadow stack memory on picture number of fragments, it is used to deposit the first address of each section of shadow stack memory on picture, address decoding circuitry is delivered to through bus in the address of data in the visit chip external memory storehouse, address comparison circuit is relatively from the address of wanting stack accessing of address decoding circuitry and each section first address in the configuration register, comparative result is delivered to chip select circuit be used to select chip external memory or shadow stack memory on picture, finish visit chip external memory or shadow stack memory on picture; Shadow stack memory on picture mapping configuration phase: processor cores executes instruction and reads the section first address content of configuration register by bus, and the content that chip external memory has been mapped to shadow stack memory on picture relays by bus gets back in the corresponding address location of chip external memory; Reset the content of the section first address of configuration register as required, and the content of the corresponding stack segment of chip external memory is mapped in the shadow stack memory on picture by bus; The described content that chip external memory has been mapped to shadow stack memory on picture relay get back in the corresponding address location of chip external memory and with the content map of the corresponding stack segment of chip external memory in shadow stack memory on picture, can adopt processor cores execution command, hardware interrupts mode or dma mode transmission; Shadow stack memory on picture working stage: when processor cores during to bus application read-write chip external memory stacked data, the address that the processor cores application that address decoding circuitry is come bus is visited is carried out address resolution and is outputed to address comparison circuit, address comparison circuit judges that the current address of visiting is whether identical with some contents that configuration register is sent here, identical then chip select circuit produces selects the shadow stack memory on picture signal, and that shadow stack memory on picture section of selecting the address to coincide conducts interviews; Otherwise chip select circuit produce to be selected the signal of chip external memory, finishes visit to external memory storage by memory controller.
3. shadow stack memory on picture circuit according to claim 2 is characterized in that: the capacity of described shadow stack memory on picture is 512 bytes, is divided into four sections, and the capacity of each section is 128 bytes; Described configuration register have four corresponding with four sections of shadow stack memory on picture respectively.
4. according to claim 2 or 3 described shadow stack memory on picture circuit, it is characterized in that: described shadow stack memory on picture adopts static RAM.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101847096B (en) * | 2010-02-05 | 2012-12-12 | 中国科学院计算技术研究所 | Optimization method of stack variable-containing function |
| CN102902346A (en) * | 2012-09-27 | 2013-01-30 | 中国科学院声学研究所 | Method and device for reducing power consumption of instruction cache memory |
| CN104850503A (en) * | 2015-05-06 | 2015-08-19 | 中国航天科技集团公司第九研究院第七七一研究所 | Common address space management method and structure |
| CN106844230A (en) * | 2017-02-21 | 2017-06-13 | 奇瑞汽车股份有限公司 | A kind of method and device of refresh controller program |
| CN107209721A (en) * | 2015-02-20 | 2017-09-26 | 高通股份有限公司 | Local and non-local memory adaptive memory is accessed |
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| CN107710151A (en) * | 2015-06-24 | 2018-02-16 | 英特尔公司 | The technology that shadow storehouse for binary file converting system manipulates |
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| CN111209042A (en) * | 2020-01-06 | 2020-05-29 | 北京字节跳动网络技术有限公司 | Method, device, medium and electronic equipment for establishing function stack |
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- 2007-08-03 CN CNB2007100255250A patent/CN100511119C/en not_active Expired - Fee Related
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| CN101847096B (en) * | 2010-02-05 | 2012-12-12 | 中国科学院计算技术研究所 | Optimization method of stack variable-containing function |
| CN102902346A (en) * | 2012-09-27 | 2013-01-30 | 中国科学院声学研究所 | Method and device for reducing power consumption of instruction cache memory |
| CN102902346B (en) * | 2012-09-27 | 2015-07-08 | 中国科学院声学研究所 | Method and device for reducing power consumption of instruction cache memory |
| CN107209721B (en) * | 2015-02-20 | 2020-10-23 | 高通股份有限公司 | Adaptive memory access to local and non-local memory |
| CN107209721A (en) * | 2015-02-20 | 2017-09-26 | 高通股份有限公司 | Local and non-local memory adaptive memory is accessed |
| CN104850503A (en) * | 2015-05-06 | 2015-08-19 | 中国航天科技集团公司第九研究院第七七一研究所 | Common address space management method and structure |
| CN104850503B (en) * | 2015-05-06 | 2017-09-19 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of general address space management and its system |
| CN107710151A (en) * | 2015-06-24 | 2018-02-16 | 英特尔公司 | The technology that shadow storehouse for binary file converting system manipulates |
| CN107710151B (en) * | 2015-06-24 | 2021-09-07 | 英特尔公司 | Techniques for shadow stack manipulation for binary file translation systems |
| CN108463826A (en) * | 2016-02-04 | 2018-08-28 | 英特尔公司 | Processor extension for protecting stack during ring changes |
| CN108463826B (en) * | 2016-02-04 | 2022-08-09 | 英特尔公司 | Processor extensions for protecting a stack during ring transitions |
| CN106844230A (en) * | 2017-02-21 | 2017-06-13 | 奇瑞汽车股份有限公司 | A kind of method and device of refresh controller program |
| CN107566904A (en) * | 2017-08-31 | 2018-01-09 | 海信电子科技（深圳）有限公司 | A kind of resource data updating method and set-top box device |
| CN111258653A (en) * | 2018-11-30 | 2020-06-09 | 上海寒武纪信息科技有限公司 | Atomic access and storage method, storage medium, computer equipment, device and system |
| CN111258653B (en) * | 2018-11-30 | 2022-05-24 | 上海寒武纪信息科技有限公司 | Atomic access and storage method, storage medium, computer equipment, device and system |
| CN112462729A (en) * | 2019-09-09 | 2021-03-09 | 贝克休斯油田作业有限责任公司 | Shadow functionality for protecting a monitoring system |
| CN112462729B (en) * | 2019-09-09 | 2023-12-19 | 贝克休斯油田作业有限责任公司 | Shadow function for protecting monitoring system |
| CN111209042A (en) * | 2020-01-06 | 2020-05-29 | 北京字节跳动网络技术有限公司 | Method, device, medium and electronic equipment for establishing function stack |
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