Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
Alternative embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
A first embodiment provided by the present disclosure is an embodiment of a method for establishing a function stack.
The establishment of the function stack is described in detail below with reference to fig. 1 and 2.
In step S101, an instruction execution address in the instruction counter is obtained.
For the application of the method to the ARM architecture, three important registers are involved in the function calling process: an instruction counter (PC register for short), a link register (LR register for short) and a stack pointer (SP register for short).
Both the PC register and the LR register point to code segments.
Each thread, when started, creates a thread stack and PC registers. The PC register holds the address of the currently executing JVM instruction. Each thread has its own PC register, which is also created when the thread starts. The PC register is used to hold a register of the address of the next instruction to be executed. The contents of the PC register always point to the address of the next instruction to be executed, which may be a local pointer or an offset in the method area corresponding to the start instruction of the method.
The LR register holds the return address of the current function. And the address of the LR register is saved in the first location of the function stack.
The SP register points to the top of the thread stack.
Referring to FIG. 2, for the Linux system, each thread has a corresponding thread stack. For example, when a thread starts, a thread stack M is started, and the thread includes: a function A, a function B, a function C and a function D; wherein, function A calls function B, function B calls function C, and function C calls function D, and then the function stack is arranged continuously in the thread stack, and the arrangement sequence is: function stack D1, function stack C1, function stack B1, and function stack A1; since function D is the last function, the SP register points to the top of the thread stack, i.e., to the top of function stack D1.
The process does not execute an instruction and the PC registers all point to the address of the instruction. Thus, each time an instruction is executed, the instruction execution address is retrieved from the PC register.
Step S102, when the value of the instruction execution address is the first calling address of the first calling function, acquiring a first return address and acquiring a stack pointer value through a stack pointer.
Referring to FIG. 3, for example, continuing the above example, when function A is executed to the calling address, then function B is called, and first, the address of function B is written into the PC register; then, the address of the next instruction at the call position of the function a, that is, the return address, is written into the LR register; to prevent the value in the LR register from being modified, further, the value in the LR register is pushed in the function stack B1, see fig. 2; when function stack B1 pops up the value, the value is assigned to the PC register value and the space of function stack B1 is freed.
Specifically, the obtaining of the first return address at least includes one of the following obtaining manners:
the method comprises the steps that in the first mode, a first return address is obtained from a link register;
and in the second mode, calculating the value of adding one to the instruction execution address to obtain the first return address.
Since the method described in the embodiments of the present disclosure occurs before the function stack is created, the first return address can only be obtained by calculation or LR register.
Step S103, retrieving a historical function stack data set based on the first calling address, the first returning address and the stack pointer value, and obtaining a retrieval result.
A historical function stack data set for storing information of function stacks that have been called, comprising: call address, return address, stack pointer value, and clone function stack address.
The cloned function stack is completely the same as the normal function stack, and because the function stack is released after the function call is completed, in order to avoid the consumption of resources caused by the generation of the function stack in the past, the embodiment of the disclosure saves different function stacks as the cloned function stack, so that the cloned function stack is used for establishing a new and same function stack, and the efficiency of establishing the function stack is improved. The cloned function stack address points to the address of the cloned function stack.
Optionally, the retrieving a historical function stack data set based on the first call address, the first return address, and the stack pointer value to obtain a retrieval result includes the following steps:
step S103-1, retrieving a historical function stack data set based on the first calling address, the first returning address and the page alignment value, and obtaining a retrieval result.
Wherein the page alignment value is the value of the last three bits of the stack pointer value.
Step S104, when the retrieval result is not empty, determining that the retrieval result is a second clone function stack address associated with a second calling function, creating a first function stack associated with the first calling function, and copying information in the second clone function stack to the first function stack according to the second clone function stack address.
The result of the search being non-empty indicates that there is a retrieved value in the historical function stack dataset and that the retrieved value may be determined to be the second clone function stack address, i.e., that a second calling function identical to the current function was called that created the second clone function stack.
The embodiment of the disclosure finds out the same stack by quickly comparing stack information, avoids repeated calculation, and improves the stack backtracking efficiency.
Step S105, when the retrieval result is empty, a first function stack associated with the first calling function is created, and calling information associated with the first calling function is stored in the first function stack.
Wherein the calling information at least comprises the first return address.
The first return address is typically stored at a first spatial location of the first function stack. When the space size of the function stack is known, the start position of the last function stack, and hence the value of the LR register, can be retrieved.
The search result being null indicates that there is no value retrieved in the history function stack dataset, i.e., that no same function has been called. The first function stack can only be created following the steps of the traditional call function.
Step S106, acquiring a first function stack address based on the first function stack.
Step S107, the first call address, the first return address, the stack pointer value and the first function stack address are saved in a history function stack data set.
To improve the efficiency of later function calls, embodiments of the present disclosure save the information of the new function call in the historical function stack dataset.
And further comprising the steps of:
and step S108, copying the first function stack to generate a first clone function stack.
Therefore, when the new function is called again later, the efficiency of function calling can be improved.
According to the method and the device, the function stack information is quickly compared, the same function stack is found from the historical function stack data set, and the clone function stack is utilized to quickly create the corresponding function stack. And repeated calculation is avoided, and the function stack backtracking efficiency is improved. After optimization, the efficiency is improved by 2-3 times. Wherein the effect is related to the number of repeated threads.
Corresponding to the first embodiment provided by the present disclosure, the present disclosure also provides a second embodiment, that is, an apparatus for establishing a function stack. Since the second embodiment is basically similar to the first embodiment, the description is simple, and the relevant portions should be referred to the corresponding description of the first embodiment. The device embodiments described below are merely illustrative.
Fig. 4 illustrates an embodiment of an apparatus for creating a function stack according to the present disclosure. Referring to fig. 4, the present disclosure provides an apparatus for creating a function stack, including: a fetch instruction execution address unit 401, a fetch parameter information unit 402, a retrieval unit 403, and a first copy unit 404.
A fetch instruction execution address unit 401 for fetching an instruction execution address in the instruction counter;
an obtaining parameter information unit 402, configured to, when the value of the instruction execution address is a first call address of a first call function, obtain a first return address and obtain a stack pointer value through a stack pointer;
a retrieving unit 403, configured to retrieve a historical function stack data set based on the first call address, the first return address, and the stack pointer value, and obtain a retrieval result;
a first copying unit 404, configured to, when the retrieval result is not empty, determine that the retrieval result is a second clone function stack address associated with a second calling function, create a first function stack associated with the first calling function, and copy information in the second clone function stack into the first function stack according to the second clone function stack address.
Optionally, the retrieving unit 403 includes:
the retrieval subunit is configured to retrieve a history function stack data set based on the first call address, the first return address, and the page alignment value, and obtain a retrieval result; wherein the page alignment value is the value of the last three bits of the stack pointer value.
Optionally, in the apparatus, the apparatus further includes:
the original unit is used for creating a first function stack associated with the first calling function when the retrieval result is empty, and storing calling information associated with the first calling function into the first function stack; wherein the calling information at least comprises the first return address.
Optionally, in the apparatus, the apparatus further includes:
a first function stack address obtaining unit, configured to obtain a first function stack address based on the first function stack;
a saving unit, configured to save the first call address, the first return address, the stack pointer value, and the first function stack address to a history function stack data set.
Optionally, in the apparatus, the apparatus further includes:
and the second copying unit is used for copying the first function stack to generate a first clone function stack.
Optionally, the obtaining parameter information unit 402 at least includes one of the following obtaining method sub-units:
the first acquisition mode subunit is used for acquiring a first return address from the link register;
and the second obtaining mode subunit is used for calculating a value obtained by adding one to the instruction execution address to obtain the first return address.
Optionally, the apparatus is applied to an ARM architecture.
According to the method and the device, the function stack information is quickly compared, the same function stack is found from the historical function stack data set, and the clone function stack is utilized to quickly create the corresponding function stack. And repeated calculation is avoided, and the function stack backtracking efficiency is improved. After optimization, the efficiency is improved by 2-3 times. Wherein the effect is related to the number of repeated threads.
The present disclosure provides a third embodiment, that is, an electronic device, where the electronic device is used in a method for establishing a function stack, and the electronic device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the one processor to cause the at least one processor to perform the method of establishing a function stack as described in the first embodiment.
The fourth embodiment provides a computer storage medium for establishing a function stack, where the computer storage medium stores computer-executable instructions that can execute the method for establishing a function stack as described in the first embodiment.
Referring now to FIG. 5, shown is a schematic diagram of an electronic device suitable for use in implementing embodiments of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle terminal (e.g., a car navigation terminal), and the like, and a stationary terminal such as a digital TV, a desktop computer, and the like. The electronic device shown in fig. 4 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 4, the electronic device may include a processing means (e.g., central processing unit, graphics processor, etc.) 501 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)502 or a program loaded from a storage means 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data necessary for the operation of the electronic apparatus are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.
Generally, the following devices may be connected to the I/O interface 505: input devices 506 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 507 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, and the like; storage devices 508 including, for example, magnetic tape, hard disk, etc.; and a communication device 509. The communication means 509 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. While fig. 4 illustrates an electronic device having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 509, or installed from the storage means 508, or installed from the ROM 502. The computer program performs the above-described functions defined in the methods of the embodiments of the present disclosure when executed by the processing device 501.
It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
In some embodiments, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperText transfer protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communications network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed network.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
Computer program code for carrying out operations for the present disclosure may be written in any combination of one or more programming languages, including but not limited to an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present disclosure may be implemented by software or hardware. Where the name of an element does not in some cases constitute a limitation on the element itself.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other embodiments in which any combination of the features described above or their equivalents does not depart from the spirit of the disclosure. For example, the above features and (but not limited to) the features disclosed in this disclosure having similar functions are replaced with each other to form the technical solution.
Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.