CN103249243A - Circuit structure for circuit laminated board - Google Patents
Circuit structure for circuit laminated board Download PDFInfo
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- CN103249243A CN103249243A CN2012100238769A CN201210023876A CN103249243A CN 103249243 A CN103249243 A CN 103249243A CN 2012100238769 A CN2012100238769 A CN 2012100238769A CN 201210023876 A CN201210023876 A CN 201210023876A CN 103249243 A CN103249243 A CN 103249243A
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Abstract
A circuit structure for a circuit laminated board comprises a substrate, a circuit metal layer, a nano plating layer and a covering layer, wherein the nano plating layer is a flat plating layer with the thickness of 5-40 mm, and is formed on the outer surface of the circuit metal layer, or the circuit metal layer and the nano plating layer can be firstly formed on a pre-molded board, then the substrate is pressed on the pre-molded board with the circuit metal layer and the nano plating layer, and finally the pre-molded board is removed to form the circuit structure of the circuit layer and the nano plating layer which are embedded into the substrate. In virtue of the chemical bonding force of the nano plating layer and the covering layer or the substrate, the interface bonding effect is improved, the surface roughening of the circuit metal layer can be omitted, and reserving circuit width for performing size compensation can be further omitted, so that the circuit density can be increased, and more dense circuits can be manufactured on the same area.
Description
Technical field
The present invention relates to a kind of line construction of circuit laminated plates, especially utilize the chemical bonded refractory power of nanometer coating layer and cover layer or substrate to improve the interface effect, do not need circuit layer on surface of metal roughening.
Background technology
With reference to figure 1, the generalized section of the line construction of prior art circuit laminated plates.The line construction 1 of prior art circuit laminated plates comprises substrate 10, circuit metal level 20 and cover layer 30.The upper surface of substrate 10 is a rough surface; circuit metal level 20 is formed on the upper surface of substrate 10; usually by copper, aluminium, silver, gold one of them is made at least; cover layer 30 is for cohering glue or welding resisting layer; circuit metal level 20 is covered; because circuit metal level 20 is different with the material of cover layer 30; for fear of delamination; usually the surface of circuit metal level 20 can be utilized mode roughenings such as chemistry, machinery or electricity slurry; increase skin-friction coefficient; and improve interfacial property, and make outer surface 25 form a rough surface.
Yet, prior art has some shortcomings with the surface roughening of circuit metal level 20, when making circuit metal level 20, for the surface roughening with circuit metal level 20, need to reserve width usually, with the compensation width that roughening was reduced, yet present line density is more and more higher, feasible limited tangible restriction in design, therefore, need a kind of line build-out that reduces to increase line construction and the manufacture method of line density.
Summary of the invention
Main purpose of the present invention provides a kind of line construction of circuit laminated plates, and this line construction comprises: a substrate, the upper surface of this substrate are a rough surface; One circuit metal level is formed on the upper surface of this substrate; One nanometer coating layer, be formed on the outer surface of this circuit metal level, thickness with 5～40nm, and after this nanometer coating layer forms, the roughness of this outer surface is Ra＜0.35 μ m, Rz＜3 μ m, and the outer surface of this circuit metal level and this nanometer coating layer are a tabular surface, can't be under 1000 times of light microscopes inspect with section and judge roughness; And a cover layer, be to cohere glue or a welding resisting layer, this circuit metal level and this nanometer coating layer are covered.
Main purpose of the present invention provides a kind of line construction of circuit laminated plates, this line construction comprises: a substrate, have a plurality of die cavitys, one nanometer coating layer, be arranged in the hole wall of described die cavity of this substrate, have the thickness of 5～40nm, and the roughness of this nanometer plating be Ra＜0.35 μ m, Rz＜3 μ m, and this nanometer coating layer is a tabular surface, can't be under 1000 times of light microscopes inspects with section and judges roughness; An and circuit metal level, be formed in the described die cavity of this substrate, and be positioned on this nanometer coating layer, form an embedded line construction, wherein a surface of this circuit metal level exposes at the upper surface of this substrate, and be positioned at same level with the upper surface of this substrate, the upper surface that makes substrate is that roughness levels off to a smooth surface of zero, surface roughness Ra＜0.35 μ m for example, Rz＜0.3 μ m, above-mentioned line construction is earlier circuit metal level and nanometer coating layer to be formed on the preformed board, with substrate and the preformed board pressing with circuit metal level and nanometer coating layer, at last preformed board is removed and formed again.
The line construction of circuit laminated plates of the present invention, chemical bonded refractory power by nanometer coating layer and cover layer or substrate, and significantly improved the interface effect, and improved existing in order to improve the interface effect with circuit layer on surface of metal roughening, carry out the side effect of dimension compensation and need to reserve line width, because the surfacing of the line construction of circuit laminated plates of the present invention, do not need to reserve line width and carry out dimension compensation, can increase line density, can be at the more intensive circuit of the making of same area.
Description of drawings
Fig. 1 is the generalized section of the line construction of prior art circuit laminated plates.
Fig. 2 is the generalized section of line construction first embodiment of circuit laminated plates of the present invention.
Fig. 3 is the generalized section of line construction second embodiment of circuit laminated plates of the present invention.
Embodiment
Following conjunction with figs. is done more detailed description to embodiments of the present invention, so that those skilled in the art can implement after studying this specification carefully according to this.
With reference to figure 2, the generalized section of line construction first embodiment of circuit laminated plates of the present invention.As shown in Figure 2, the line construction 2 of circuit laminated plates of the present invention comprises substrate 10, circuit metal level 20, nanometer coating layer 40 and cover layer 30.Substrate 10 by FR4 glass fibre or bismaleimides-cyanate resin (namely, the BT resin) made, the upper surface of substrate 10 is a rough surface, circuit metal level 20 is formed on the upper surface of substrate 10, usually by copper, aluminium, silver, gold one of them is made at least, nanometer coating layer 40 is formed on the outer surface of circuit metal level 20, thickness with 5～40nm, by copper, tin, aluminium, nickel, silver, at least two kinds of gold are made, and roughness is Ra＜0.35 μ m, Rz＜3 μ m, the outer surface of nanometer coating layer 40 and circuit metal level 20 is a tabular surface, can't be under 1000 times of light microscopes inspects with section and judges roughness.Cover layer 30 covers circuit metal level 20 and Nanoalloy coating layer 40 for cohering glue or welding resisting layer (that is, green lacquer).
Wherein, circuit metal level 20 is to form by traditional image transfer mode, nanometer coating layer 40 is to utilize electroless plating (namely, chemical plating), evaporation, sputter or ald (Atomic Layer Deposition, ALD) mode is formed on the outer surface of circuit metal level 20, circuit metal level 20 is formed have the structure on three smooth surfaces.
With reference to figure 3, the generalized section of line construction second embodiment of circuit laminated plates of the present invention.As shown in Figure 3, the line construction 3 of circuit laminated plates of the present invention comprises substrate 10, circuit metal level 20 and nanometer coating layer 40, nanometer coating layer 40 is arranged in the hole wall of die cavity 12 of substrate 10, circuit metal level 20 is formed in the die cavity 12 of substrate 10, and be positioned on the nanometer coating layer 40, form an embedded line construction, one surface of circuit metal level 20 exposes at the upper surface of substrate 10, and be positioned at same level with the upper surface of substrate 10, and the upper surface that makes substrate 10 is a smooth surface, surface roughness Ra＜0.35 μ m, Rz＜3 μ m, and can't be under 1000 times of light microscopes inspect with section and judge roughness.
The line construction 3 of second embodiment of the invention circuit laminated plates is the production method that utilizes similar first embodiment, earlier circuit metal level 20 and nanometer coating layer 40 are formed on the preformed board 100, again with substrate 10 and preformed board 100 pressings with circuit metal level 20 and nanometer coating layer 40, at last preformed board 100 is removed and formed, preformed board 100 can be Ra＜0.35 μ m for roughness, Rz＜3 μ m, and can't be under 1000 times of light microscopes inspect with section and judge roughness, preformed board 100 can be for having the polished surface metallic plate, for example, steel plate, aluminium sheet, copper coin etc., or comprise the insulated substrate of the metal level of polishing, the FR4 substrate that for example comprises the copper layer of polishing, or comprise the BT substrate etc. of aluminium lamination, at this only as example, as restriction.So can make circuit metal level 20 form the structure with smooth surface, four sides.
The line construction of circuit laminated plates of the present invention, by the chemical bonded refractory power of nanometer coating layer 40 with cover layer 30 or substrate 10, and significantly improved the interface effect, and improved existing in order to improve the interface effect with circuit metal level 20 surface roughenings, carry out the side effect of dimension compensation and need to reserve line width, because the surfacing of the line construction of circuit laminated plates of the present invention, do not need to reserve line width and carry out dimension compensation, can increase line density, can be at the more intensive circuit of the making of same area.
The above person only is in order to explain preferred embodiment of the present invention, be not that attempt is done any pro forma restriction to the present invention according to this, therefore, all have in that identical invention spirit is following do relevant any modification of the present invention or change, all must be included in the category of claim of the present invention.
Claims (8)
1. the line construction of a circuit laminated plates is characterized in that, the line construction of this circuit laminated plates comprises:
One substrate, a upper surface of this substrate is a rough surface;
One circuit metal level is formed on this upper surface of this substrate;
One nanometer coating layer is formed on the outer surface of this circuit metal level, have the thickness of 5～40nm, and roughness is Ra＜0.35 μ m, Rz＜3 μ m; And
One cover layer is to cohere glue or a welding resisting layer, this circuit metal level and this nanometer coating layer covered,
Wherein the outer surface of this circuit metal level and this nanometer coating layer are inspected with section under 1000 times of light microscopes and can't be judged roughness.
2. the line construction of circuit laminated plates according to claim 1, it is characterized in that, this substrate is made by FR4 glass fibre or bismaleimides-cyanate resin, this circuit metal level by copper, aluminium, silver, gold one of them is made at least, this nanometer coating layer is made by copper, tin, aluminium, nickel, silver, gold at least two kinds.
3. the line construction of circuit laminated plates according to claim 1 is characterized in that, this nanometer coating layer is to utilize the mode of electroless plating, evaporation, sputter or ald to be formed on the outer surface of this circuit metal level.
4. the line construction of a circuit laminated plates is characterized in that, the line construction of this circuit laminated plates comprises:
One substrate has a plurality of die cavitys;
One nanometer coating layer is arranged in the hole wall of described die cavity of this substrate, have the thickness of 5～40nm, and roughness is Ra＜0.35 μ m, Rz＜3 μ m; And
One circuit metal level is formed in the described die cavity of this substrate, and is positioned on this nanometer coating layer, forms an embedded line construction,
Wherein a surface of this circuit metal level exposes at the upper surface of this substrate, and be positioned at same level with the upper surface of this substrate, the upper surface that makes this substrate is that surface roughness is the smooth surface of Ra＜0.35 μ m, Rz＜3 μ m, and the surface of the upper surface of this nanometer coating layer, this substrate and this circuit metal level is inspected with section under 1000 times of light microscopes and can't be judged roughness again.
5. as the line construction of circuit laminated plates as described in the claim 4, it is characterized in that, this substrate is made by FR4 glass fibre or bismaleimides-cyanate resin, this circuit metal level by copper, aluminium, silver, gold one of them is made at least, this nanometer coating layer is made by copper, tin, aluminium, nickel, silver, gold at least two kinds.
6. as the line construction of circuit laminated plates as described in the claim 4, it is characterized in that, this circuit metal level is formed on the preformed board in an image transfer mode, this nanometer coating layer is to utilize the mode of electroless plating, evaporation, sputter or ald to be formed on the outer surface of this circuit metal level, with this substrate and this preformed board pressing with this circuit metal level and this nanometer coating layer, at last this preformed board is removed and this embedded line construction of formation again.
7. as the line construction of circuit laminated plates as described in the claim 5, it is characterized in that, this preformed board is that surface roughness is Ra＜0.35 μ m, Rz＜3 μ m, and the surface of this preforming substrate is inspected with section under 1000 times of light microscopes can't judge roughness, and this preformed board is an insulated substrate that has a metallic plate of a polished surface or have a polishing metal layer again.
8. as the line construction of circuit laminated plates as described in the claim 7, it is characterized in that this metallic plate is steel plate, aluminium sheet or copper coin, this polishing metal layer is copper layer or aluminium lamination, and this insulated substrate is made by FR4 glass fibre or bismaleimides-cyanate resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100238769A CN103249243A (en) | 2012-02-03 | 2012-02-03 | Circuit structure for circuit laminated board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100238769A CN103249243A (en) | 2012-02-03 | 2012-02-03 | Circuit structure for circuit laminated board |
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| Publication Number | Publication Date |
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| CN103249243A true CN103249243A (en) | 2013-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012100238769A Pending CN103249243A (en) | 2012-02-03 | 2012-02-03 | Circuit structure for circuit laminated board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108696705A (en) * | 2018-03-22 | 2018-10-23 | 江苏蔚联机械股份有限公司 | A kind of television set under-chassis and preparation method thereof with high brightness minute surface |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101616535A (en) * | 2008-06-24 | 2009-12-30 | 松下电器产业株式会社 | Circuit board, and the manufacture method of circuit board |
| CN101668880A (en) * | 2007-04-27 | 2010-03-10 | 日立化成工业株式会社 | Connecting terminal, semiconductor package using connecting terminal and method for manufacturing semiconductor package |
| JP2010238928A (en) * | 2009-03-31 | 2010-10-21 | Nippon Mining & Metals Co Ltd | Copper foil for printed circuit board |
| JP2011100795A (en) * | 2009-11-04 | 2011-05-19 | Panasonic Electric Works Co Ltd | Circuit board |
-
2012
- 2012-02-03 CN CN2012100238769A patent/CN103249243A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101668880A (en) * | 2007-04-27 | 2010-03-10 | 日立化成工业株式会社 | Connecting terminal, semiconductor package using connecting terminal and method for manufacturing semiconductor package |
| CN101616535A (en) * | 2008-06-24 | 2009-12-30 | 松下电器产业株式会社 | Circuit board, and the manufacture method of circuit board |
| JP2010238928A (en) * | 2009-03-31 | 2010-10-21 | Nippon Mining & Metals Co Ltd | Copper foil for printed circuit board |
| JP2011100795A (en) * | 2009-11-04 | 2011-05-19 | Panasonic Electric Works Co Ltd | Circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108696705A (en) * | 2018-03-22 | 2018-10-23 | 江苏蔚联机械股份有限公司 | A kind of television set under-chassis and preparation method thereof with high brightness minute surface |
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Application publication date: 20130814 |