CN103248794A - Line-field synchronizing signal generating device with adjustable resolution - Google Patents
Line-field synchronizing signal generating device with adjustable resolution Download PDFInfo
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Abstract
The invention discloses a line-field synchronizing signal generating device with adjustable resolution. Two line-field parameter registers are adopted to store line-field parameters in a default display mode and an adjustable display mode respectively, input of a port is selected according to the display mode at the top layer, and a corresponding line-field parameter is selected to be sent to a line-field synchronizing signal generating module; and a line signal counter performs counting to a clock, the field signal counter performs counting to the count cycle of the line signal counter, then according to the count values of the line signal counter and the field signal counter and the line-field parameters, high level or low level is output, and a line-field synchronizing signal and a data effective signal are obtained. According to the invention, FPGA (Field Programmable Gate Array) can be used to realize the line-field synchronizing signal generating device, Verilog language can be adopted to describe the two counters, judge modules adopt corresponding if statements to perform level judging according to count values so as to obtain the line-field synchronizing signal with adjustable resolution and the data effective signal, and the implementation logic is simpler and more intuitive.
Description
Technical field
The invention belongs to the video technique field, more specifically say, relate to the adjustable capable field sync signal generation device of a kind of resolution.
Background technology
Common capable field sync signal generation device adopts state machine to produce corresponding capable field sync signal, and the value of time sequence parameter fixes, and all is the value under a certain specified resolution, and just resolution is non-adjustable.For example Lee state is firm, Yu Jun, " VGA industrial standard " followed in the VGA display strictness of Ling Chaodong design in " based on the implementation method of the VGA graphics controller of FPGA ", and capable field sync signal resolution herein is non-adjustable, only supports this a kind of pattern of 640 * 48060Hz.But in the processes such as emulation that image is handled, it is inconvenient that this mode seems.And for example, for detect the digital video generator that uses for the digitized image processor, it is different from traditional analog video generator, content is fixed though the latter can produce digital video, this digital signal video generator can be changed the parameters of signal generator output video in real time, but the adjustable mechanism of not mentioned resolution still herein.Therefore, design has adopted the capable field sync signal generation device of the adjustable mechanism of resolution to seem necessary.
Simultaneously, adopt state machine to realize the generation of row field sync signal, seem complicated though inerrancy realizes logic, the resource of consumption is also more relatively.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of resolution adjustable capable field sync signal generation device, realize that resolution is adjustable, reduce the consumption of resource simultaneously.
For achieving the above object, the capable field sync signal generation device that resolution of the present invention is adjustable is characterized in that, comprising: time sequence parameter module and row field sync signal generation module;
In the time sequence parameter module, including two row parameter registers is default row field parameter register and line of input field parameter register; The time sequence parameter module is selected the input of port according to the display mode of top layer, select corresponding display mode, if module default resolution pattern, capable field blanking front porch width, unit synchronous head width, capable field blanking back porch width, effective coverage width and the total length of field sync signal are exported to capable field sync signal generation module at once then to select a row parameter in the parameter register of default row field; If the resolution adjustable mode, capable field blanking front porch width, unit synchronous head width, capable field blanking back porch width, effective coverage width and the total length of field sync signal are exported to capable field sync signal generation module at once then to select a row parameter in the parameter register of line of input field;
Wherein, the row parameter in the parameter register of line of input field is outside input, both can be the input from the user, also can be the input from other modules, thereby realizes that resolution is adjustable;
Include capable event counter, field signal counter in the field sync signal of the being expert at generation module;
After reset signal and module enable signal were set to high level, row event counter and field signal counter began counting respectively;
The row event counter is that clock is counted, and its count value is no more than total clock number of current resolution downstream signal one-period of regulation, is determined by the total length of line synchronizing signal; Namely write all over if the count value of row event counter reaches total clock number of capable signal one-period, then zero clearing is counted again since 0;
The field signal counter event counter of being expert at is whenever finished a count cycle and is namely write all over once, and when just having remembered delegation, count value adds 1; In like manner, the count value of field signal counter is no more than total line number total length of synchronizing signal on the spot of the current resolution next frame of regulation, if the count value of field signal counter reaches total line number of a frame, then zero clearing is since 0 counting again;
Also include capable signal output level judge module, field signal output level judge module and data useful signal output level judge module in the field sync signal of the being expert at generation module;
Row signal output level judge module is according to blanking crop, row synchronous head, blanking back porch, the sequential of effective coverage and the clock number of width correspondence separately of line synchronizing signal, count value according to the row event counter, determine a certain position in line synchronizing signal, output high level or low level obtain line synchronizing signal;
Field signal output level judge module is according to blanking crop, field synchronization head, blanking back porch, the sequential of effective coverage and the line number of width correspondence separately of field signal, count value according to the field signal counter, determine a certain position in field sync signal, output high level or low level obtain field sync signal;
Data useful signal output level judge module, blanking crop, row synchronous head, blanking back porch, the sequential of effective coverage and the clock number of width correspondence separately according to the row signal, count value according to the row event counter, determine a certain position at the data useful signal, output high level or low level obtain the line data useful signal; Blanking crop, field synchronization head, blanking back porch, the sequential of effective coverage and the line number of width correspondence separately according to field signal, count value according to the field signal counter, determine a certain position at the data useful signal, output high level or low level, obtain the field data useful signal, then with the field data useful signal as enable signal, the output of line data useful signal is controlled, output obtained the data useful signal when only the presence data useful signal was effective.
Goal of the invention of the present invention is achieved in that
The capable field sync signal generation device that resolution of the present invention is adjustable, adopt two row parameter registers to store a row parameter under acquiescence and the adjustable display mode of resolution respectively, and select the input of port according to the display mode of top layer, select a corresponding row parameter to give row field sync signal generation module; The row event counter is counted clock, the field signal counter was counted the count cycle of row event counter, according to a row parameter, count value output high level or low level according to the row field signal counter obtain row field sync signal and data useful signal then.The present invention can realize with FPGA, adopt two counters of Verilog language description and each judge module to adopt corresponding if statement to carry out electrical level judging according to count value, obtain the adjustable capable field sync signal of resolution and data useful signal, and realize more simple, intuitive of logic.Therefore, the present invention directly realizes the generation of row field sync signal with counter without state machine, and has resolution adjustable function to a certain degree.
Description of drawings
Fig. 1 is the adjustable capable field sync signal generation device one embodiment theory diagram of resolution of the present invention;
Fig. 2 is the interface block diagram of time sequence parameter module shown in Figure 1;
Fig. 3 is the cut-away view of time sequence parameter module shown in Figure 1;
Fig. 4 is the schematic diagram that concerns of line synchronizing signal and data useful signal;
Fig. 5 is the schematic diagram that concerns of field sync signal and data useful signal;
Fig. 6 is time sequence parameter module interface sequential chart shown in Figure 1;
Fig. 7 is the interface block diagram of capable field sync signal generation module shown in Figure 1;
Fig. 8 is the cut-away view of capable field sync signal generation module shown in Figure 1;
Fig. 9 is capable field sync signal generation module interface sequence figure shown in Figure 1;
Figure 10 adopts capable field sync signal and the data useful signal of the present invention's output to carry out the image result displayed.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.What need point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.
The function that row field sync signal generation device is finished is according to (the Consumer Electronics Association of U.S. consumer electronics AEM, CEA) " uncompressed digital video standard " (CEA-861 of Zhi Dinging, latest edition is CEA-861-E), generation meets capable field sync signal and the data useful signal of this standard time sequence, realizes the synchronous output of input pixel file.
Fig. 1 is the adjustable capable field sync signal generation device one embodiment theory diagram of resolution of the present invention.
In the present embodiment, as shown in Figure 1, the capable field sync signal generation device that resolution is adjustable comprises time sequence parameter module timing_par1 and row field sync signal generation module video_sig_gen2.
At first, time sequence parameter module timing_par1 selects corresponding display mode according to the input of the display mode selection port op_mode of top layer.In the present embodiment, have two kinds to select display modes, a kind of is the resolution 720 * 480p of module acquiescence, another kind of then be the resolution adjustable mode that the line of input field parameter according to the outside disposes.If module default resolution pattern, blanking front porch width, unit synchronous head width, blanking back porch width, effective coverage width and the total length of field sync signal are exported to capable field sync signal generation module at once then to select a row parameter in the parameter register of default row field; If the resolution adjustable mode, blanking front porch width, unit synchronous head width, blanking back porch width, effective coverage width and the total length of field sync signal are exported to capable field sync signal generation module at once then to select a row parameter in the parameter register of line of input field.
In the field sync signal of the being expert at generation module, have two counters event counter, field signal counter at once altogether, carry out clock count respectively and to the count cycle counting of row event counter, simultaneously, regulation according to the relevant row parameter in the CEA-861-E standard, and the relation between the blanking crop of row (field) signal, row field synchronization head, blanking back porch and these several persons of data effective coverage width, this module arranges Rule of judgment, count value output high level or low level according to the row field signal counter obtain row field sync signal and data useful signal.
1, time sequence parameter module
1.1, structure
The major function that time sequence parameter module timing_par1 realizes is the row parameter under storage acquiescence and the adjustable display mode of resolution, and exports to capable field sync signal generation module.Row parameter under the adjustable display mode of its intermediate-resolution is outside input, both can be the input from the user, also can be the input from other modules.
This module definition a kind of resolution of acquiescence for selecting for use, also can select to dispose simultaneously resolution.The resolution of this module acquiescence is 720 * 480p, its time sequence parameter all defines according to the EIA-CEA-861-E standard, and these time sequence parameters comprise: blanking crop, row (field) synchronous head, blanking back porch and row (field) the signal effective coverage of row (field) signal.If select the adjustable display mode of resolution, then the value of above line field parameter need rely on an outside row parameter of importing and being stored in the parameter register of line of input field.It is display mode that user by selecting port op_mode selects to adopt which kind of resolution configuration mode, and this module outputs to capable field sync signal generation module video_sig_gen2 for its work with each row parameter in the register then.
The interface block diagram of time sequence parameter module timing_par1 and cut-away view are shown in Fig. 2,3, and its I/O port list is as shown in table 1.Wherein, the parameter configuration input port is used for a row parameter of configuration line field parameter register, both can be the input from the user, also can be the input from other modules, thereby realizes that resolution is adjustable.
| Signal | Direction | Bit wide | Describe | |
| | Input | 1 | System's input global | |
| rst | Input | |||
| 1 | Systematic reset signal, low level is effective | |||
| op_mode | |
1 | The time sequence parameter configuration mode is selected | |
| v_total_cfg | |
11 | The parameter configuration input port is for the value of configuration v_total | |
| | Input | 11 | The parameter configuration input port is for the value of configuration v_width | |
| | Input | 6 | The parameter configuration input port is for the value of configuration v_front | |
| | Input | 5 | The parameter configuration input port is for the value of configuration v_back | |
| v_sw_cfg | |
4 | The parameter configuration input port is for the value of configuration v_sw | |
| | Input | 12 | The parameter configuration input port is for the value of configuration | |
| h_width_cfg | Input | |||
| 11 | The parameter configuration input port is for the value of configuration | |||
| h_front_cfg | Input | |||
| 8 | The parameter configuration input port is for the value of configuration | |||
| h_back_cfg | Input | |||
| 7 | The parameter configuration input port is for the value of configuration | |||
| h_sw_cfg | Input | |||
| 8 | The parameter configuration input port is for the value of configuration h_sw | |||
| v_total | |
11 | The field sync signal total | |
| v_width | Output | |||
| 11 | Field sync signal effective coverage width |
| Signal | Direction | Bit wide | Describe |
| v_front | |
6 | Field sync signal blanking crop |
| v_back | |
5 | Field sync signal blanking back porch |
| v_sw | |
4 | The field synchronization head of field sync |
| h_total | Output | ||
| 12 | The line synchronizing signal total | ||
| h_width | Output | ||
| 11 | Line synchronizing signal valid interval | ||
| h_front | Output | ||
| 8 | Line synchronizing signal blanking | ||
| h_back | Output | ||
| 7 | Line synchronizing signal blanking back | ||
| h_sw | Output | ||
| 8 | The capable synchronous head of line synchronizing signal |
Table 1
Time sequence parameter submodule timing_par1 is built-in 2 kinds of time sequence parameter configuration modes are respectively the parameter of 720 * 480p of presetting and the parameter of outside input, select this two kinds of configuration modes according to the input of input op_mode.
1.2, operation principle
Time sequence parameter module timing_par1 operation principle is: receive after clock signal clk and reset signal rst be set to high level, this module can realize the selection to descending parameter of different resolution according to the difference of the input value of display mode selection port op_mode.If it is the 0(low level that display mode is selected the input value of port op_mode), the row parameter under 720 * 480p resolution of then selecting to give tacit consent to; Input value is the 1(high level if display mode is selected port op_mode), this moment, this module just entered the resolution adjustable mode, and a row parameter is no longer pre-set, but is imported by the outside.Here so-called outside input both can be the input from the user, also can be the input from other modules.
A parameter of going comprises crop h_front, row synchronous head h_sw, back porch h_back, the effective sector width h_width of row, crop v_front, a field synchronization v_sw of field sync signal, field blanking back porch v_back, effective sector width v_width of line synchronizing signal; H_total represents the line synchronizing signal total length of one-period, equals the parameter value addition of above-mentioned several line synchronizing signals on the numerical value; V_total is with regard to therewith in like manner, and corresponding is the field sync signal total length of one-period.In the built-in default resolution of module, the value of these parameters all arranges in strict accordance with the regulation of the time sequence parameter of 720 * 480p resolution in the EIA-CEA-861-E standard.
Here above-mentioned parameter concerned that brief description is as follows:
The relation of line synchronizing signal and data useful signal.The line synchronizing signal of one-period comprises blanking crop, row synchronous head, blanking back porch and row effective coverage, and capable effective coverage herein namely is the effective coverage of data useful signal.According to " common progressive video format sequential " in EIA-CEA-861-E standard figure, the pass of line synchronizing signal and data useful signal is tied up to this draw and illustrate, as shown in Figure 4.
The relation of field sync signal and data useful signal.The field signal of one-period comprises field blanking crop, field synchronization head, field blanking back porch and effective district, and only within effective district on the scene, the data useful signal could be in aforementioned row is effectively distinguished effectively.According to " common progressive video format sequential " in EIA-CEA-861-E standard figure, the pass of field signal and data useful signal ties up to this signal of drawing, as shown in Figure 5.
1.3, interface sequence
The Time-Series analysis of time sequence parameter submodule as shown in Figure 6, this module is input as at 0 o'clock in time sequence parameter configuration mode selecting side, the time sequence parameter of 720 * 480p of output acquiescence; If be input as 1, then each time sequence parameter is endowed the value of exterior arrangement.
2, go the field sync signal generation module
2.1, structure
The major function that row field sync signal generation module video_sig_gen2 realizes is, module on having obtained, after being the data imported into of time sequence parameter module timing_par1, under the driving of clock signal, the regulation that related parameter is arranged according to row (field) synchronizing signal in each resolution in the EIA-CEA-861-E standard, export correct row (field) synchronizing signal, use for subsequent module.
The interface block diagram of row field sync signal generation module video_sig_gen2 and cut-away view are shown in Fig. 7,8, and its I/O port list is as shown in table 2.
| Signal | Direction | Bit wide | Describe | |
| | Input | 1 | Clock signal of | |
| rst | Input | |||
| 1 | Systematic reset signal, low level is | |||
| Module_en | Input | |||
| 1 | Module enables, and high level is effective | |||
| v_total | |
11 | The field sync signal total length | |
| v_width | |
11 | Field sync signal effective coverage width | |
| v_front | |
6 | The field sync signal crop | |
| v_back | |
5 | The field sync signal back porch | |
| v_sw | |
4 | The field sync signal synchronous | |
| h_total | Input | |||
| 12 | The line synchronizing signal total | |||
| h_width | Input | |||
| 11 | Line synchronizing signal valid interval | |||
| h_front | Input | |||
| 8 | The line synchronizing signal | |||
| h_back | Input | |||
| 7 | The line synchronizing signal back | |||
| h_sw | Input | |||
| 8 | The line synchronizing signal synchronous head |
| Signal | Direction | Bit wide | Describe | |
| | Output | 1 | The line synchronizing signal of output, high level is | |
| vsync | Output | |||
| 1 | The field sync signal of output, high level is effective | |||
| de | |
1 | The data useful signal of output, high level is effective |
Table 2
As seen from Figure 8, row field sync signal generation module video_sig_gen2 comprises two counters, is respectively capable event counter and field signal counter.The row event counter is counted the clock clk of input, and the field signal counter is then counted row, and the event counter of namely being expert at adds 1 after finishing a count cycle (having remembered delegation).The count results of row event counter and field signal counter is given each follow-up judge module, the height that the level of capable signal, field signal and data useful signal is set according to the EIA-CEA-861-E standard changes, and the width of level is determined according to blanking crop, row field synchronization head, blanking back porch and the data effective coverage width of row (field) signal.The d type flip flop of FDC(asynchronous reset) effect then is above-mentioned three signals to be made a call to one clap back output.
2.2, operation principle
Row field sync signal generation module video_sig_gen2 operation principle is as follows: after reset signal rst_n and module enable signal Module_en are set to high level, under the driving of clock signal clk, two counters of inside modules, event counter (hsync_cnt) and field signal counter (hsync_cnt) begin counting respectively at once.The event counter of wherein going is that clock is counted, and its count value is no more than total clock number of current resolution downstream signal one-period of stipulating in the EIA-CEA-861-E standard, and counter O reset is counted again since 0 if count value is full.The field signal counter is expert at event counter when whenever finishing a count cycle (writing all over), and when just having remembered delegation, count value adds 1.In like manner, the count value of field signal counter is no more than total line number of the current resolution next frame of EIA-CEA-861-E standard code, if fill it up with regard to zero clearing, counts again.
Simultaneously, row parameter under the various resolution that this module reception time sequence parameter submodule timing_par1 imports into, the blanking crop that comprises row (field) signal, row (field) synchronous head, blanking back porch and row (field) the signal effective coverage of row (field) signal.Line synchronizing signal and field sync signal high level always not within one-period in the present embodiment, is low level in the interval of be expert at synchronous head and field synchronization head, and rest interval is high level.The data useful signal only is expert at signal and field signal when all being positioned at separately effective coverage, just is high level, and all the other times all are low levels.Therefore according to above-mentioned sequential rule, designed corresponding judgment mechanism in the module, different according to the count value of front row event counter and field signal counter, the level of corresponding capable signal, field signal and data useful signal is also correspondingly put height or is put lowly, then these several signals is made a call to one and is clapped the back and export.
In this special instruction:
(1), the row (field) signal one-period among, the level of the level of synchronous head and blanking crop, blanking back porch and effective coverage is different.But what person is that what person of high level is low level actually, there is no unified regulation in the EIA-CEA-861-E standard, but behind the time sequence parameter table, done such statement---the signal major part of negative polarity (negative polarity) is high level, and it is low having only synchronous head; Positive polarity (positive polarity) is then just in time opposite;
(2) in the screen procedure for displaying of reality, have only when the synchronous head of row (field) signal for low all the other when being high, screen just can show.
According to above 2 points, the capable field sync signal of video_sig_gen module herein adopts the regulation of so-called negative polarity signal in the EIA-CEA-861-E standard without exception, and namely synchronous head is low level, and remainder is high level.
In addition, row field sync signal generation module video_sig_gen2 worker's clock signal clk, be the CLK of top-level module, its clock frequency defines when excitation is write in emulation according to the pixel clock frequency under the resolution of every kind of frame frequency in the EIA-CEA-861-E standard.
2.3, interface sequence
The interface sequence figure of row field sync signal generation module as shown in Figure 9.Do not indicate resolution at this, because no matter be which kind of resolution, the sequential relationship of output signal de, hsync and vsync also is similar, difference only is the effectively difference of the concrete width in district of (field) blanking crop, row (field) synchronous head, row (field) blanking back porch, row (field), and this row parameter according to input is determined.
Sequential relationship and concrete width according to various piece in the row field sync signal, when count value reaches some values, determine the to be expert at a certain position of field sync signal and data useful signal, thus output level put height or put lowly, obtain row field sync signal and data useful signal.
3, experimental result
3.1, image shows the result
Correctness for the adjustable capable field sync signal generation device of the resolution that can test the present invention's proposition, capable field sync signal and the data useful signal of the capable field sync signal generation device output that the resolution that the pixel file is proposed according to the present invention is adjustable, under Modelsim SE6.5 environment, carry out functional simulation, and utilized MATLAB that simulation result is printed demonstration.Present embodiment, employing resolution are that the view data of 720*480 is tested, and test result is illustrated in fig. 15 shown below.The result shows, can provide correct sequential for other modules.
3.2, systematic function
In the present embodiment, the development platform of selection is Xilinx Virtex-5xc5vlx330t-1ff1738, utilizes Xilinx ISE 10.1 compiling implementation tools to adopt Verilog that above-mentioned framework has been carried out compiling and emulation.Adopt the resolution 720 * 480p of module acquiescence herein, because the sequential relationship between each time sequence parameter has unified standard, if so emulation can obtain correct result under this resolution, other as long as itself do not have mistake, just also can obtain correct capable field sync signal from the time sequence parameter of outside input so.System performance analysis is as shown in table 4.
| ? | ? |
| Clock frequency (Hz) | The user defines (according to the EIA-CEA-861 standard) |
| Outside bit wide (bit) | 30 |
| Processing speed | 1pixel/clock |
| Pixel color depth (bit) | 10 |
Table 4
4, conclusion
In order to realize the requirement of row field sync signal in the Video processing, the present invention proposes the adjustable capable field sync signal generation device of a kind of resolution, this device adopts the mode of counter to realize the generation of line synchronizing signal, field sync signal and data useful signal, and the sequential of above-mentioned signal meets the EIA-CEA-861-E standard.Compare with the implementation of state machine, the present invention has simplified processing logic, has reduced resource consumption.In order to reach the adjustable requirement of resolution, the present invention has designed a module separately, stores the time sequence parameter of different resolution with a series of register groups.On development platform Xilinx Virtex-5xc5vlx330t, this row field sync signal generation module can produce the correct capable field sync signal of sequential under 321 logical blocks consume, have the processing speed of 1pixel/clock.Test result shows, the adjustable capable field sync signal generation device of resolution that the present invention proposes can correctly produce capable field sync signal and data useful signal, obtains correct image and exports, thereby provide correct sequential for other modules.
Although above the illustrative embodiment of the present invention is described; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present invention determined in, these variations are apparent, all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (2)
1. the capable field sync signal generation device that resolution is adjustable is characterized in that resolution is adjustable and adopts the counter mode to realize the generation of row field sync signal, and this device comprises: time sequence parameter module and row field sync signal generation module;
In the time sequence parameter module, including two row parameter registers is default row field parameter register and line of input field parameter register; The time sequence parameter module is selected the input of port according to the display mode of top layer, select corresponding display mode, if module default resolution pattern, capable field blanking front porch width, unit synchronous head width, capable field blanking back porch width, effective coverage width and the total length of field sync signal are exported to capable field sync signal generation module at once then to select a row parameter in the parameter register of default row field; If the resolution adjustable mode, capable field blanking front porch width, unit synchronous head width, capable field blanking back porch width, effective coverage width and the total length of field sync signal are exported to capable field sync signal generation module at once then to select a row parameter in the parameter register of line of input field;
Wherein, the row parameter in the parameter register of line of input field is outside input, both can be the input from the user, also can be the input from other modules, thereby realizes that resolution is adjustable;
Include capable event counter, field signal counter in the field sync signal of the being expert at generation module;
After reset signal and module enable signal were set to high level, row event counter and field signal counter began counting respectively;
The row event counter is that clock is counted, and its count value is no more than total clock number of current resolution downstream signal one-period of regulation, is determined by the total length of line synchronizing signal; Namely write all over if the count value of row event counter reaches total clock number of capable signal one-period, then zero clearing is counted again since 0;
The field signal counter event counter of being expert at is whenever finished a count cycle and is namely write all over once, and when just having remembered delegation, count value adds 1; In like manner, the count value of field signal counter is no more than total line number total length of synchronizing signal on the spot of the current resolution next frame of regulation, if the count value of field signal counter reaches total line number of a frame, then zero clearing is since 0 counting again;
Also include capable signal output level judge module, field signal output level judge module and data useful signal output level judge module in the field sync signal of the being expert at generation module;
Row signal output level judge module is according to blanking crop, row synchronous head, blanking back porch, the sequential of effective coverage and the clock number of width correspondence separately of line synchronizing signal, count value according to the row event counter, determine a certain position in line synchronizing signal, output high level or low level obtain line synchronizing signal;
Field signal output level judge module is according to blanking crop, field synchronization head, blanking back porch, the sequential of effective coverage and the line number of width correspondence separately of field signal, count value according to the field signal counter, determine a certain position in field sync signal, output high level or low level obtain field sync signal;
Data useful signal output level judge module, blanking crop, row synchronous head, blanking back porch, the sequential of effective coverage and the clock number of width correspondence separately according to the row signal, count value according to the row event counter, determine a certain position at the data useful signal, output high level or low level obtain the line data useful signal; Blanking crop, field synchronization head, blanking back porch, the sequential of effective coverage and the line number of width correspondence separately according to field signal, the count value of root field signal counter, determine a certain position at the data useful signal, output high level or low level, obtain the field data useful signal, then with the field data useful signal as enable signal, the output of line data useful signal is controlled, output obtained the data useful signal when only the presence data useful signal was effective.
2. according to the capable field sync signal generation device shown in the claim 1, it is characterized in that, realize with FPGA, adopt two counters of Verilog language description and each judge module, adopt corresponding if statement to carry out electrical level judging according to count value.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN108347599A (en) * | 2018-01-26 | 2018-07-31 | 郑州云海信息技术有限公司 | A kind of vision signal Effective judgement method and system based on FPGA |
| CN108616674A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Two-way video-signal timing sequence generating circuit structure with outer synchronizing function |
| CN109981925A (en) * | 2019-03-06 | 2019-07-05 | 深兰科技（上海）有限公司 | A kind of image data generator based on Video Graphics Array VGA timing standard |
| CN113257169A (en) * | 2021-06-01 | 2021-08-13 | 南京初芯集成电路有限公司 | Method, controller and system for changing Y-axis resolution |
| CN116758855A (en) * | 2023-08-22 | 2023-09-15 | 联士光电（深圳）有限公司 | Input signal phase relation self-adapting circuit in micro display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103915063A (en) * | 2014-04-17 | 2014-07-09 | 西安诺瓦电子科技有限公司 | LED display screen control card, control system and resolution ratio self-adaption adjusting method |
| CN104822040A (en) * | 2015-04-28 | 2015-08-05 | 深圳市载德光电技术开发有限公司 | Multi-format video sequence generation system based on FPGA and method thereof |
| CN104822040B (en) * | 2015-04-28 | 2018-06-19 | 深圳市载德光电技术开发有限公司 | A kind of multiple format video sequence generation system and method based on FPGA |
| CN108616674A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Two-way video-signal timing sequence generating circuit structure with outer synchronizing function |
| CN108616674B (en) * | 2016-12-12 | 2020-10-20 | 中国航空工业集团公司西安航空计算技术研究所 | Double-channel video signal time sequence generating circuit structure with external synchronization function |
| CN108347599A (en) * | 2018-01-26 | 2018-07-31 | 郑州云海信息技术有限公司 | A kind of vision signal Effective judgement method and system based on FPGA |
| CN108347599B (en) * | 2018-01-26 | 2019-07-30 | 郑州云海信息技术有限公司 | A kind of vision signal Effective judgement method and system based on FPGA |
| CN109981925A (en) * | 2019-03-06 | 2019-07-05 | 深兰科技（上海）有限公司 | A kind of image data generator based on Video Graphics Array VGA timing standard |
| CN113257169A (en) * | 2021-06-01 | 2021-08-13 | 南京初芯集成电路有限公司 | Method, controller and system for changing Y-axis resolution |
| CN113257169B (en) * | 2021-06-01 | 2021-09-24 | 南京初芯集成电路有限公司 | Method, controller and system for changing Y-axis resolution |
| CN116758855A (en) * | 2023-08-22 | 2023-09-15 | 联士光电（深圳）有限公司 | Input signal phase relation self-adapting circuit in micro display panel |
| CN116758855B (en) * | 2023-08-22 | 2023-11-03 | 联士光电（深圳）有限公司 | Input signal phase relation self-adapting circuit in micro display panel |
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