CN103248566B - A kind of fault-tolerance approach and structure of stopping model based on mistake being applied to network-on-chip - Google Patents
A kind of fault-tolerance approach and structure of stopping model based on mistake being applied to network-on-chip Download PDFInfo
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Abstract
The invention belongs to Calculation of Reliability machine network-on-chip System design technology field, be specially a kind of fault-tolerance approach and the structure that stop model based on mistake that are applied to network-on-chip.The mistake that the present invention is based on network-on-chip stops model, proposes a kind of Fault-tolerant Routing Algorithm of binary channels twocouese of partial adaptivity, realizes the fault tolerance rout ing of the network-on-chip of partial failure according to this Fault-tolerant Routing Algorithm.This Fault-tolerant Routing Algorithm, under the inefficacy latus rectum that can there is failed link and some at network-on-chip, transmit data with shortest path, realize exempting from deadlock, exempting from livelock and exempt from hunger of route, also there is the characteristics such as restructural, easily extensible and high-throughput, thus realize higher pseudo-core utilance.The present invention can not only be contained in the inefficacy latus rectum of some in the failed link of network-on-chip center and route, has same fault-tolerant ability to the inefficacy latus rectum of some in the failed link of network-on-chip border and corner location and route.
Description
Technical field
The invention belongs to Calculation of Reliability machine network-on-chip System design technology field, be specifically related to a kind of fault-tolerance approach and the structure that stop model based on mistake that are applied to network-on-chip.
Background technology
Along with manufacturing process is growing, the operating voltage of very lagre scale integrated circuit (VLSIC) constantly reduces, and operating frequency progressively raises, and integrated level also progressively expands.Along with the proposition of network-on-chip and flourish, single chip area and transistor gate number also present the trend of increase, if Fudan University 16 core processor chip area is 9.10mm
2, 24 cores " multiple core " processor chips area is 18.8mm
2, transistor size is 3.21 hundred ten thousand, and 8 cores " Godson " area of the Chinese Academy of Sciences is 299.8mm
2, transistor size is 5.826 hundred million, and 167 core process chip areas of University of California Davis are 39.4mm
2, transistor size is 5.5 thousand ten thousand, and 48 cores and 80 core processors of Intel are respectively 576mm
2and 275mm
2, and comprising 1,300,000,000 and 100,000,000 transistors respectively, the CELL that IBM, SONY and TOSHIBA develop jointly then comprises 9 processor cores and comprises 2.34 hundred million transistors etc.
So large single chip area and number of transistors, as the prediction from Intel, in ensuing ten years, we it will be appreciated that the single-chip being integrated with 1,000 hundred million transistors.But the expansion of scale, the increase of integrated level, the raising of frequency etc. all can cause increasing of chip internal defect.Integrated hundreds of kernel, makes chip complete various required function; But wherein the transistor of 20% can produce defect in the fabrication process, in 1 year of work, will the transistor of 10% be had to lose efficacy again.So the effective ways addressed these problems are exactly the design of fault tolerance rout ing.The design of fault tolerance rout ing mainly comprises two aspects.One is hold chip internal physical imperfection (hard error), and two is hold due to a variety of causes in Data within the chip transmitting procedure, as crosstalk, noise, cosmic ray etc., causes signal to overturn (soft error).For hard error, redundancy is generally had to substitute and the fault-tolerant way such as algorithm fault avoidance; For soft error, generally solve by error correcting code.By fault-tolerant, the yields of network-on-a-chip chip increases, and the useful life of chip extends, and the stability of system strengthens, and the performance of system also can be improved.
Summary of the invention
For overcoming the deficiencies in the prior art, the object of the invention is to propose a kind ofly be applied to stopping the fault-tolerance approach of model based on mistake and realizing the circuit structure of the method for network-on-chip.
The present invention proposes a kind of fault-tolerance approach stopping model based on mistake being applied to network-on-chip, and concrete steps comprise:
(1) obtained the Fault Distribution figure of network-on-chip by test, the Fault Distribution figure of described network-on-chip comprises the failed link distribution map between the distribution map of each router failure latus rectum, router and the failed link distribution map between router and pseudo-core;
(2) according to the Fault Distribution figure of Fault-tolerant Routing Algorithm of the present invention and network-on-chip, calculate 8 information of each port of each router, each router has east, south, west, north and local totally 5 ports, needs 40 information;
(3) a corner router in network-on-chip sends 40 information of each router needs to configuration router, and effective information part, according to these configuration informations, is sent to the route computing unit of router by the Data Analysis unit of this router;
(4) 40 configuration informations received are preserved in a register by the route computing unit in router, the information that route computing unit is preserved according to these, by Fault-tolerant Routing Algorithm, select the output port of data, send data to destination with the shortest path existed;
Wherein: Fault-tolerant Routing Algorithm described in step (2) and (4) can be divided into three large steps: mistake stops the foundation of model; Calculate 8 information of each port of router; According to 8 information of a port, select the output port of input data.
1) set up mistake according to the Fault Distribution figure of network-on-chip and stop model.
According to Fault Distribution figure, for non-border and corner router, the router that coordinate is (i, j) can be calculated
whether can use, " 1 ", " 0 " represents unavailable if representing available,
the input port I of router (i, j) can be interpreted as, if the neighboring router of IX access failures or X-direction is
unavailable, and the neighboring router of IY access failures or Y-direction is
unavailable.Concrete account form can with following iterative (1):
（1）
Wherein, for the network-on-chip of m × n, 1 < i < m, 1 < j < n,
denotation coordination is the router of (i, j)
iXpath,
denotation coordination is the router of (i, j)
iYpath; Its value is obtained by the Fault Distribution figure of network-on-chip, I ∈ { E, S, W, N, L}, X ∈ { E, W}, Y ∈ { S, N}.Wherein the value of a and b is as following table:
Be in the router of border and corner, need to do some special processings, specific as follows:
For coboundary router, y=n, XN path and XN latus rectum lost efficacy, wherein X ∈ { E, S, W, L}; For lower boundary router, y=1, XS path and XS latus rectum lost efficacy, wherein X ∈ { E, N, W, L}; For left margin router, x=1, XW path and XW latus rectum lost efficacy, wherein X ∈ { E, N, S, L}; For right margin router, x=m, XE path and XE latus rectum lost efficacy, wherein X ∈ { W, N, S, L}.
For corner router, need the two kinds of special processings as above doing adjacent two border routers.
Border and corner router can be represented with formula (2) ~ (5)
whether can use.
（2）
（3）
（4）
（5）
2) method of 8 configuration informations of each port of router is calculated.In all-router, except not having the port of input link and not needing 8 configuration informations, all the other ports all need configuration.Utilize the data that step 1) obtains, calculate 8 configuration informations.
,
,
,
with
denotation coordination is the configuration information of five ports in router east, south, west, north and local of (i, j) respectively, calculates by formula (6).
（6）
Wherein
expression router (i, j)
keep away latus rectum ring whether effective, I ∈ { E, S, W, N}, X ∈ { E, S, W, N} and X ≠ I, Y ∈ { E, S, W, N} and Y=
.Concrete calculating is as formula (7).
(7)
The principle that " ± " in formula chooses is the closed-loop making the path related on the right of equation form the local pseudo-core of arrival.
3) output port of input data is selected.Specifically can be divided into following steps:
1. according to the direction of data destination relative to data source, determine that possible output port is one or more in E1, S1, W1, N1 and L1;
2. according to the configuration information of 8 and the input port at current data place, the output port of calculated candidate is one or more in E2, S2, W2, N2 and L2, and concrete calculating sees formula (8) ~ (12);
Input data are at router the east mouth:
(8) data are inputted at router south mouth:
（9）
Input data are at the western port of router:
（10）
Input data are at router the North mouth:
（11）
Input data are at router local port:
（12）
3. final output port E3, S3, W3, N3 or L3 is determined:
（13）
Wherein, X ∈ { when E, S, W, N, L}, X get different value, represents that the output port that input data should be selected when X port is X.
In the present invention, each router comprises five input/output ports, and wherein four ports communicate with the neighbor router on the four direction of all directions, and another port communicates with the pseudo-core in this locality.
Fault-tolerance approach of the present invention, to network-on-chip exist wrong link and route in erroneous path set up one mistake stop model, packet from each input port of router needs router-level topology to determine down hop direction when forwarding, the data of each input port only need 8 information when router-level topology in the present invention, totally 5 input ports, so a router needs 40 routing iinformations altogether.
For the west input port of router (other directions are similar), store 8 and be: whether three O direction neighboring router OOX except west can use, wherein O ∈ E, S, N}, X ∈ E, S, W, N} and
, easily know that the neighboring router in each direction has two attribute and needs local router to store, so totally 6; The possible path of meaning representation pseudo-core from this port to this locality of other 2.
The present invention proposes a kind of Fault-tolerant Routing Algorithm of binary channels twocouese of partial adaptivity of two-dimentional mesh structure, the circuit structure realizing this algorithm is made up of the routing unit repeated.Each routing unit is made up of two parts: router and pseudo-core.Communicated by input buffer cell between router and pseudo-core.Concrete structure is as Fig. 3.
(1) router comprises input buffer cell, route computing unit, wavefront moderator and exchanges data switch;
Router and neighbor router carry out exchanges data by twin-channel input buffer cell, carry out exchanges data with the pseudo-core in this locality by single pass input buffer cell.Input data are through route computing unit, wavefront moderator and exchanges data switch to neighbor router or pseudo-core, and its Fault-tolerant Routing Algorithm according to the present invention selects specific port to export, and can not export from the input port of these data.
Input buffer cell mainly carries out buffer memory to data, thus can alleviate the routing pressure of router.
Input buffer cell between router and router is binary channels, realizes the partial adaptivity of routing algorithm, thus arrives destination address with possible shortest path, realizes the high-throughput of network-on-chip.
Input buffer cell between the pseudo-core of router and this locality is single channel route, mainly considers that the traffic of local pseudo-core is not very large.
Route computing unit according to the occupied information etc. of source address, destination address, adjacent node link and latus rectum information and current router output port, the output port that determination data is possible.
The output port that wavefront moderator requires according to five input ports, make arbitration, determination data from which port exports, occur to prevent the hunger of router, every two clock cycle, the Priority Inversions of input FPDP, can effectively prevent the hunger of router from occurring like this; Why being called wavefront moderator, is because adopt wavefront (wavefront) mechanism of " poll ".
Exchanges data switch, according to the arbitration result of wavefront moderator, selects the data of input port to output port.
(2) pseudo-core comprises input buffer cell and controller, and its middle controller is made up of Data Analysis unit, data generating unit and data transmission unit.
Input data are introduced into Data Analysis unit and resolve, then produce packet by data generating unit to data after parsing, finally data are sent by data transmission unit.
The data of the Data Analysis unit resolves input in pseudo-core, can make corresponding operation, these operate and comprise the clock closedown that the interval appointment clock cycle specifies number microplate (flit) to the transmission of appointment pseudo-core, interval specifies the clock cycle to specify number microplate to random pseudo-core transmission, specify number microplate in the appointment moment and will receive the pseudo-core of these data to the pseudo-core transmission of appointment.
Wherein the moment is being specified to contain to specifying pseudo-core to send the microplate specified number the number of data packets that number of data packets that this pseudo-core receives before this moment sends before this moment with this pseudo-core.A data handbag draws together a data head, zero or one or more data volume and a data tail.
Data generating unit produces packet according to the data message received, and comprises the information such as the source address of data and destination address in packet.
Data sent in particular moment by data transmission unit, and particular moment is determined by the information of the data received.
Data channel between router of the present invention and router is binary channels, form VC0 network and VC1 network respectively, and the transfer of data between router and router, between router and pseudo-core is two-way.The routing mode adopted between different passages is not the same, adopts the routing mode of expansion east orientation last (Extended-East-Last) in VC0 network; In VC1 network, adopt expansion west to the routing mode of last (Extended-West-Last), as Fig. 5, and data can only uniaxially from VC0 network transitions to VC1 network, and can not from VC1 network transitions to VC0 network, thus the partial adaptivity of implementation algorithm and exempt from livelock, as Fig. 6.
Beneficial effect of the present invention is
:
The inventive method can realize higher pseudo-core utilance, it can not only be contained in the inefficacy latus rectum of some in the failed link of network-on-chip center and route, has same fault-tolerant ability to the inefficacy latus rectum of some in the failed link of network-on-chip border and corner location and route; Fault-tolerant architecture in the present invention realizes Fault-tolerant Routing Algorithm by configuration information, and adopts 2 dimension grid on-chip network structure, can the restructural of implementation structure and easily extensible.
Accompanying drawing explanation
Fig. 1 is the coordinate definition of network-on-chip.
Fig. 2 is path, latus rectum and link instance in network-on-chip.
Fig. 3 is fault-tolerant unit circuit structure.
Fig. 4 is for keeping away latus rectum ring example.
Fig. 5 is dual data channels structure.
Fig. 6 is the data transmission network that dual data channels is formed.
Fig. 7 is router link and the latus rectum validity example of part network-on-chip.
Fig. 8 is the data throughput of two-dimensional grid 10 × 10 network-on-chip under different router access failures probability.
Embodiment
below in conjunction with drawings and Examples, the present invention is described in further detail.
Figure 1 shows that the coordinate definition of network-on-chip; Fig. 2 is path, latus rectum and link instance in network-on-chip.
Before telling about mistake and stopping model, be defined as follows:
(1) E represents east, and S represents south, and W represents west, and N represents north, and L represents local.And have as X=E,
=W; As X=S,
=N; As X=W,
=E; As X=N,
=S.
(2) link be connected with router input mouth is referred to as the input link of this router; The link be connected with router output mouth is referred to as the output link of this router.XY link refers to input port from the output port of a router to neighboring router or one paths of the input port of pseudo-core to this locality, uses
represent the XY link of router (i, j), wherein X ∈ { E, S, W, N, L}, Y ∈ { E, S, W, N, L}, and Y=
.Disabled link is called failed link,
, no person is active link,
.
(3) XY latus rectum refers to the paths from the input port of same router to its output port, uses
represent the XY latus rectum of router (i, j), wherein X ∈ { E, S, W, N}, Y ∈ { E, S, W, N, L}, and Y ≠ X.Disabled latus rectum is called inefficacy latus rectum, and value is 0, otherwise is effective drift diameter, and value is 1.
(4) XY path refers to input port from the input port of a router to neighboring router or one paths of the input port of pseudo-core to this locality, uses
represent the XY path of router (i, j), wherein X ∈ { E, S, W, N, L}, Y ∈ { E, S, W, N, L}, and Y ≠ X.Disabled path is called inefficacy path, and value is 0, and no person is effective path, and value is 1.Path is made up of latus rectum and corresponding link, as ES latus rectum and SN link composition ES path.
(5) the disabled meaning of the IXY of router is that Designated Router cannot send data by input port I to the neighboring router of X-direction and Y-direction, uses
represent whether the IXY of router (i, j) can use, wherein I ∈ { E, S, W, N, L}, X ∈ { E, W}, Y ∈ { S, N}.
As X ≠ I, and during Y ≠ I, the input port I of (A) routers, if IX access failures and IY access failures, we claim router to be that IXY is unavailable; (B) the input port I of routers, if the neighboring router of IX access failures or X-direction is
unavailable, and the neighboring router of IY access failures or Y-direction is
unavailable, we claim router to be that IXY is unavailable.
Work as X=I, and during Y ≠ I, the input port I of (A) routers, if IY access failures, we claim router to be that IXY is unavailable; (B) the input port I of routers, if the neighboring router of IY access failures or Y-direction is
unavailable, we claim router to be that IXY is unavailable.
As X ≠ I, and during Y=I, the input port I of (A) routers, if IX access failures, we claim router to be that IXY is unavailable; (B) the input port I of routers, if the neighboring router of IX access failures or X-direction is
unavailable, we claim router to be that IXY is unavailable.
Router is that non-IXY is unavailable, being then referred to as IXY can use.
(6) IOD of router (i, j) keeps away latus rectum ring, is designated as
, wherein I ∈ E, S, W, N}, O ∈ E, S, W, N} and O ≠ I, D ∈ E, S, W, N} and
, refer to equally one by multiple IXY available routers and between line and a path led to local router path and form, its composition expression formula is:
The principle that " ± " in formula chooses is the closed-loop making the path related on the right of equation form the local pseudo-core of arrival.
If IOD keeps away in latus rectum ring and was lost efficacy or can not find corresponding IXY available routers by any link failure or latus rectum and form IOD and keep away latus rectum ring, we claim router to be that IOD keeps away latus rectum ring and lost efficacy, otherwise are referred to as IOD and keep away latus rectum ring and not lose efficacy or effectively.Latus rectum ring is kept away and WSE keeps away latus rectum ring as the path that is 3 and 4 of label in Fig. 4 WNE that is router R2.
There is above definition, told about the job step of fault-tolerance approach of the present invention and fault-tolerant architecture below in detail.
1) obtain the link of each router and each pseudo-core and the distribution map of latus rectum inefficacy by certain method of testing, the failed link of network-on-chip and the distribution map of latus rectum, also can be called the Fault Distribution figure of network-on-chip.
2) according to the Fault Distribution figure of Fault-tolerant Routing Algorithm of the present invention and network-on-chip, 8 information of each port of each router are calculated.For the R1 router in Fig. 7, routing iinformation is stored by the form of formula (6), front 6 information that the western port of router R1 stores are " 111011 ", and wherein " 10 " represent that input port, router west can not send data with the shortest path to the north and west.Because the WL latus rectum of R1 is effective, so 8 information that the western port of R1 stores are " 11101111 ".If it is noted that router itself to be WX obstructed, wherein { E, S, N}, then the attribute of the corresponding X-direction router stored is X ∈ entirely " 0 ", because router itself cannot send data with shortest path toward the neighboring router in this direction.As R2 in Fig. 7, although router R3 is that EEN can be able to use with EES in the east, because the WE of R2 lost efficacy, R2 cannot send out data with shortest path to R3,6 bit data positions " 001101 " of therefore input port, R2 west storage.
3) a corner router in network-on-chip sends the configuration information of configuration router.Each router also has oneself Data Analysis unit, according to data message, makes corresponding operation.The port in each direction needs 8 information, has 5 ports, totally 40 information.Divide two microplates configurations, each microplate is 32.The data packet format of a configuration router port, need two packets, the implication of representative is respectively:
First microplate form of router configuration data:
Second microplate form of router configuration data:
| 31-24 position | 23-14 position | 13-5 position | 4-0 position |
| Local | Null(NUL) | Whether close 9 input FIFO clocks | Whether close 5 and export FIFO clock |
4) router is according to the information of configuration, send data to destination with the shortest path existed.Concrete method of testing is send data by the method for configuration router to pseudo-core, these data tell pseudo-core should to the pseudo-core of which address, how many at interval time the clock cycle send the data of how many microplates.As long as configure the microplate of pseudo-core one 32, form is as follows:
5) after some time, the transmission data manipulation of each pseudo-core terminates, the reception of each pseudo-core can be added up and send data number, thus obtain the data throughput of whole network-on-chip under Fault-tolerant Routing Algorithm of the present invention, Fig. 8 lists in two-dimensional grid 10 × 10 network-on-chip, data throughput under different router access failures probability, simulation time under often kind of failure probability is 10000 clock cycle, it is inject 0.1 microplate each clock cycle that the packet of each available pseudo-core injects probability, can find out, under Fault-tolerant Routing Algorithm of the present invention, data throughput has had large increase.
Claims (3)
1. be applied to the fault-tolerance approach stopping model based on mistake of network-on-chip, it is characterized in that, concrete steps are as follows:
(1) obtained the Fault Distribution figure of network-on-chip by test, the Fault Distribution figure of described network-on-chip comprises the failed link distribution map between the distribution map of each router failure latus rectum, router and the failed link distribution map between router and pseudo-core;
(2) according to the Fault Distribution figure of Fault-tolerant Routing Algorithm and network-on-chip, calculate 8 information of each port of each router, each router has east, south, west, north and local totally 5 ports, needs 40 information;
(3) a corner router in network-on-chip sends 40 information of each router needs to configuration router, and effective information part, according to these configuration informations, is sent to the route computing unit of router by the Data Analysis unit of this router;
(4) 40 configuration informations received are preserved in a register by the route computing unit in router, the information that route computing unit is preserved according to these, by Fault-tolerant Routing Algorithm, select the output port of data, send data to destination with the shortest path existed;
Wherein, Fault-tolerant Routing Algorithm described in step (2) and (4) is divided into three steps: mistake stops the foundation of model; Calculate 8 information of each port of router; According to 8 information of a port, select the output port of input data; Specific as follows:
1) set up mistake according to the Fault Distribution figure of network-on-chip and stop model;
According to Fault Distribution figure, for non-border and corner router, calculate the router that coordinate is (i, j)
whether can use, " 1 ", " 0 " represents unavailable if representing available,
be interpreted as the input port I of router (i, j), if the neighboring router of IX access failures or X-direction is
unavailable, and the neighboring router of IY access failures or Y-direction is
unavailable; Concrete account form can with following iterative (1):
（1）
Wherein, for the network-on-chip of m × n, 1 < i < m, 1 < j < n,
denotation coordination is the router of (i, j)
iXpath,
denotation coordination is the router of (i, j)
iYpath; Its value is obtained by the Fault Distribution figure of network-on-chip, and { { { S, N}, E represent east to E, W}, Y ∈ to E, S, W, N, L}, X ∈ to I ∈, and S represents south, and W represents west, and N represents north, and L represents local; Wherein the value of a and b is as following table:
Be in the router of border and corner, need to do following process:
For coboundary router, y=n, XN path and XN latus rectum lost efficacy, wherein X ∈ { E, S, W, L}; For lower boundary router, y=1, XS path and XS latus rectum lost efficacy, wherein X ∈ { E, N, W, L}; For left margin router, x=1, XW path and XW latus rectum lost efficacy, wherein X ∈ { E, N, S, L}; For right margin router, x=m, XE path and XE latus rectum lost efficacy, wherein X ∈ { W, N, S, L};
For corner router, need the two kinds of the same process doing adjacent two border routers;
Border and corner router is represented with formula (2) ~ (5)
whether can use;
（2）
（3）
（4）
（5）
2) calculate 8 configuration informations of each port of router: in all-router, except not having the port of input link and not needing 8 configuration informations, all the other ports all need configuration; Utilize the data that step 1) obtains, calculate 8 configuration informations;
,
,
,
with
denotation coordination is the configuration information of five ports in router east, south, west, north and local of (i, j) respectively, calculates by formula (6):
（6）
Wherein
expression router (i, j)
keep away latus rectum ring whether effective, I ∈ { E, S, W, N}, X ∈ { E, S, W, N} and X ≠ I, Y ∈ { E, S, W, N} and Y=
, specifically calculate as formula (7):
(7)
The principle that " ± " in formula chooses is the closed-loop making the path related on the right of equation form the local pseudo-core of arrival;
3) select the output port of input data, be specifically divided into following steps:
1. according to the direction of data destination relative to data source, determine that possible output port is one or more in E1, S1, W1, N1 and L1;
2. according to the configuration information of 8 and the input port at current data place, the output port of calculated candidate is one or more in E2, S2, W2, N2 and L2, and concrete calculating sees formula (8) ~ (12);
Input data are at router the east mouth:
(8) data are inputted at router south mouth:
（9）
Input data are at the western port of router:
（10）
Input data are at router the North mouth:
（11）
Input data are at router local port:
（12）
3. final output port E3, S3, W3, N3 or L3 is determined:
（13）
Wherein, X ∈ { when E, S, W, N, L}, X get different value, represents that the output port that input data should be selected when X port is X;
Wherein: based on mistake, what be applied to network-on-chip stops that the routing unit that the device of the fault-tolerance approach of model is repeated by several forms, each routing unit comprises router and pseudo-core, carries out connection communication between described router and described pseudo-core by input buffer cell.
2. the fault-tolerance approach stopping model based on mistake being applied to network-on-chip according to claim 1, is characterized in that: described network-on-chip comprises VC0 network and VC1 network, and data uniaxially is from VC0 network transitions to VC1 network.
3. the fault-tolerance approach stopping model based on mistake being applied to network-on-chip according to claim 2, is characterized in that: in described VC0 network, adopt the routing mode that expansion east orientation is last; In described VC1 network, adopt expansion west to last routing mode.
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| CN104202241A (en) * | 2014-08-06 | 2014-12-10 | 长春理工大学 | Deflection fault-tolerant routing algorithm for network-on-chip with 2D-Mesh topology structure |
| CN105591910B (en) * | 2016-03-04 | 2018-06-12 | 北京交通大学 | A kind of fault-tolerant Manhattan method for routing for route direction monotone variation network |
| CN107171954B (en) * | 2016-03-08 | 2020-06-26 | 华为技术有限公司 | Fault-tolerant routing method and device and network on chip |
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