CN117951079A - Network on chip, chip and data transmission method in chip - Google Patents

Abstract

The embodiment of the application provides a network-on-chip, a chip and a data transmission method in the chip, wherein the network-on-chip comprises at least two sub-networks which comprise a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks; the routing module is used for following the data forwarding rule of the sub-network on the chip to which the routing module belongs and forwarding the data; the data comes from the function modules connected to themselves in the chip or from adjacent routing modules belonging to the same sub-network on the chip. When the functional module of the chip has regional failure, for the data which needs to be sent to the target functional module by the source functional module, if one of the on-chip sub-networks can not realize data forwarding according to the data forwarding rules, the on-chip sub-networks with different data forwarding rules can realize data forwarding. Thus, in the case of partial functional module shielding, low latency and high connectivity of accesses between functional modules are still guaranteed.

Description

Network on chip, chip and data transmission method in chip

Technical Field

The present application relates to the field of communications technologies, and in particular, to a network on chip, a chip, and a data transmission method in the chip.

Background

Network On Chip (NoC) is a major component of multi-core technology, and gradually becomes a ubiquitous communication structure in multi-core chips. The network on chip consists of transport channels and router nodes (routers). The network topology determines the physical layout and connections between nodes and channels in the network.

In designing a network on chip, the following basic requirements need to be considered: 1) Communication delay between cores is reduced as much as possible. 2) The data transmission among cores is ensured to be free from deadlock as much as possible. When the basic requirements are met, the traditional network-on-chip often ignores the interconnection among cores when the chips are in regional failure.

Disclosure of Invention

The embodiment of the application aims to provide a network on chip, a chip and a data transmission method in the chip, which are used for improving connectivity among functional modules on the premise of reducing communication delay among the functional modules as much as possible and ensuring that data transmission is not deadlocked when regional timeliness occurs in the chip.

In a first aspect of the application, a network on chip is provided,

The network on chip comprises at least two sub-networks on chip; the on-chip subnetwork comprises a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks;

The routing module is used for following the data forwarding rule of the sub-network on the chip to which the routing module belongs and forwarding data; the data comes from the function modules connected to themselves in the chip or from adjacent routing modules belonging to the same sub-network on chip.

Optionally, the on-chip subnetwork is in a mesh topology.

Optionally, the data forwarding rule is used for limiting the forwarding direction of the data forwarded by the routing module, so that the data transmission of the on-chip subnetwork is free from deadlock; the steering includes: turning from the first direction to the second direction and turning from the second direction to the first direction; wherein the first direction is a horizontal direction of the grid topology; the second direction is a vertical direction of the grid topology.

Optionally, the on-chip network includes a first on-chip subnetwork and a second on-chip subnetwork.

Optionally, for a first routing module and a second routing module connected to the same functional module, the data forwarding rule of the first on-chip subnetwork limits the steering of the first routing module, and the data forwarding rule of the second on-chip subnetwork is different from the data forwarding rule of the second on-chip subnetwork limits the steering of the second routing module; wherein the first routing module belongs to the first on-chip subnetwork and the second routing module belongs to the second on-chip subnetwork.

Optionally, the data forwarding rules configured for different on-chip subnetworks fulfil the following conditions:

For any first data sent from the source functional module to the destination functional module, when there is a blocked functional module, at least one target on-chip sub-network can complete forwarding of the first data according to a configured data forwarding rule, and a forwarding path does not pass through the blocked functional module.

Optionally, when the function module is used as a source function module for sending data, the function module is used for determining a target on-chip subnetwork according to the routing table; a target path following a data forwarding rule exists in the target on-chip sub-network; the target path is a path from the source functional module to the destination functional module; the routing table maintains the reachable paths following the data forwarding rule in each on-chip sub-network;

the function module is also used for sending the data to a self-connected routing module belonging to the target on-chip subnetwork; the data carries forwarding instructions generated based on the target path;

the routing module is specifically configured to forward data according to the forwarding instruction.

Optionally, when there is a blocked functional module in the chip; the routing table maintains the reachable paths of the function modules which follow the data forwarding rule and do not go through blocking in each on-chip sub-network;

The source function module is specifically configured to determine a target on-chip sub-network according to reachable paths of function modules that follow a data forwarding rule and do not pass through a block in each on-chip sub-network maintained in the routing table, where the target on-chip sub-network has a target path of function modules that follow the data forwarding rule and do not pass through the block; the target path is a path from the source functional module to the destination functional module.

In a second aspect of the present application, a chip is provided, including a functional module, any of the networks on chip described above.

In a third aspect of the present application, there is provided a data transmission method in a chip,

The chip comprises: the system comprises a functional module and a network-on-chip, wherein the network-on-chip comprises a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks;

The method comprises the following steps:

The source function module determines a target on-chip subnetwork according to the routing table; a target path following a data forwarding rule exists in the target on-chip sub-network; the target path is a path from the source functional module to the destination functional module; the routing table maintains the reachable paths following the data forwarding rule in each on-chip sub-network;

The source function module sends data to a self-connected routing module belonging to the target on-chip subnetwork; and the data carries a forwarding instruction generated based on the target path, so that the routing module of the target on-chip subnetwork sends the data to the target functional module according to the forwarding instruction.

Optionally, when there is a blocked functional module in the chip;

the routing table maintains the reachable paths of the function modules which follow the data forwarding rule and do not go through blocking in each on-chip sub-network;

The step of determining the target on-chip subnetwork by the source functional module according to the routing table comprises the following steps:

the source function module determines a target on-chip sub-network according to the reachable paths of the function modules which follow the data forwarding rules and do not pass through the blocking in each on-chip sub-network maintained in the routing table, wherein the target paths of the function modules which follow the data forwarding rules and do not pass through the blocking exist in the target on-chip sub-network; the target path is a path from the source functional module to the destination functional module.

The on-chip network provided by the embodiment of the application comprises at least two on-chip subnetworks, and different data forwarding rules are configured for different on-chip subnetworks. And the routing module is used for forwarding data according to the data forwarding rule of the sub-network on the chip. When the functional module of the chip has regional failure, for the data which needs to be sent to the target functional module by the source functional module, if one of the on-chip sub-networks can not realize data forwarding according to the data forwarding rules, the on-chip sub-networks with different data forwarding rules can realize data forwarding. Thus, in the case of partial functional module shielding, low latency and high connectivity of accesses between functional modules are still guaranteed.

Of course, it is not necessary for any one product or method of practicing the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other embodiments may be obtained according to these drawings to those skilled in the art.

FIG. 1 is a schematic diagram of a through-chip structure;

FIG. 2 is a schematic diagram of a memory forwarding chip structure;

FIG. 3 is a schematic diagram of a related art network on chip;

FIG. 4 is a schematic diagram of another architecture of a related art network on chip;

FIG. 5 is a schematic diagram of a data deadlock in a network on chip;

Fig. 6 is a schematic structural diagram of a network on chip according to an embodiment of the present application;

FIG. 7 is a schematic diagram of data transmission when a block occurs in a functional module in the network on chip;

FIG. 8 is another schematic diagram of data transmission when a block occurs in a functional module in the network on chip;

Fig. 9 is a schematic flow chart of a method for transmitting data in a chip according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by the person skilled in the art based on the present invention are included in the scope of protection of the present invention.

For ease of understanding, the related art will be described first.

For the most core network processing chip in a network forwarding device, there are generally two data processing schemes:

1) Through-type. The through-type is to directly transmit message data between each internal module, and is simple to implement, as shown in fig. 1, fig. 1 is a schematic diagram of a through-type chip structure, and modules 1,2 and 3 are shown. However, the requirement on the internal data bandwidth is higher, and bandwidth waste exists for the processing flow which only needs part of the message information, for example, the module 2 only needs part of the message data, but acquires all the message data; meanwhile, since there is no external memory such as DRAM (Dynamic Random Access Memory ), the memory capacity inside the chip is limited by the chip area, and it is difficult for the processing chip of this mode to satisfy the service processing requiring a large buffering capacity.

2) And storing the forwarding type. The store-and-forward type utilizes external storage such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory ), HBM (High Bandwidth Memory, high broadband memory) and the like, firstly, a message is stored in the external storage, and simplified description information is generated by an edge module for transmission, see fig. 2, fig. 2 is a schematic diagram of a memory forwarding type chip structure, as shown in fig. 2, if the data of the message is 200Byte in total, the module 1 only transmits a very small part of data, such as10 Byte, to the module 2. This extracted information is sufficient to complete the data processing of most modules. The line width between modules only needs to meet the description Fu Kuandu, and the chip area saved by the scheme can be used for more complex processing flows. And after the processing is finished, extracting and transmitting the message from an external storage.

Gradually, part of modules in the network chip realize the generalized design and introduce software instructions to realize service flexibility, and some processing modules in the middle are converted from special hardware design to general software cores.

The more complex the processing flow, the longer the processing time of a single message, the more complex router service introduces a large amount of software operation, and the processing parallelism of the chip needs to be improved to the greatest extent to meet the forwarding performance of high bandwidth. Where bandwidth = message length/processing duration x processing parallelism. How to organize the interconnection relation among a large number of processing cores in the network chip and the connection relation between the processing cores and the external storage, so that access conflict is avoided as much as possible under the condition of reasonable connection quantity, and the method becomes a difficult point and a key point of the design of the network processing chip.

Referring to fig. 3, a schematic diagram of a network on chip in the related art is shown, and as shown in fig. 3, a bus structure is created between a processing core and a peripheral module, and access of packet data and interaction between the module and the core, and between the core and the core are all performed through a bus, where the bus has a natural broadcasting attribute, so that multiple data reception can be realized without copying data. In implementation, the bus is composed of two unidirectional data paths with opposite directions, so that the data transmission is ensured not to generate conflict and deadlock. The transmission destination is determined by addressing the bus access point, and the transmission direction with shorter path is calculated and determined by the sender.

However, the network-on-chip structure shown in fig. 3 is not easy to expand, and as the number of processing cores increases, the number of routing points through which the bus passes increases, resulting in higher delay of a single data transmission.

Referring to fig. 4, another structure diagram of a network on chip in the related art is shown in fig. 4, and a mesh route is created between processing cores, where the mesh refers to a mesh topology. The routing points in regular arrangement are connected with each other through a bidirectional transmission channel, and each routing point can execute three operations of left turn, right turn and straight run. The routing points are marked by coordinates, and the sender creates a series of steering and straight-going instructions, carries the instructions in data, and removes one instruction message every time a routing point passes until reaching a transmission destination.

However, the network-on-chip architecture shown in fig. 4 presents a risk of path deadlock. Referring to fig. 5, a schematic diagram of a path deadlock in a mesh structure is shown in fig. 5, at the same moment, data sent by a routing module S1 to a routing module D1 arrives at a routing module a, data sent by a routing module S2 to a routing module D2 arrives at a routing module b, data sent by a routing module S3 to a routing module D3 arrives at a routing module c, data sent by a routing module S4 to a routing module D4 arrives at a routing module D, and each group of data needs to wait for the next group of data to be forwarded, so that cyclic waiting occurs, resulting in a path deadlock.

In addition, as the functional modules in the chip may be blocked, when the functional modules are blocked, interconnection between other functional modules is ensured as much as possible, which is also important for the design of the network on chip. At present, the network on chip often ignores the connectivity among functional modules when the chip has regional failure.

In order to solve the technical problems, the embodiment of the application provides a network on chip, a chip and a data transmission method in the chip.

The network on chip is also called an on-chip bus, and the network on chip includes a transmission channel and a routing module, where the routing module may also be understood as a router node (router) for connecting each functional module in a chip, where the functional modules in the chip are modules that combine software and hardware to implement a specific function, such as a CPU core, a Packet parser (Packet Decoder), a storage controller (Memory Controller), a Queue Manager (Queue Manager), and so on.

The network-on-chip provided by the embodiment of the application comprises at least two sub-networks on-chip; the on-chip subnetwork comprises a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks; the routing module is used for following the data forwarding rule of the sub-network on the chip to which the routing module belongs and forwarding the data; the data comes from the function modules connected to themselves in the chip or from adjacent routing modules belonging to the same sub-network on the chip.

As an example, referring to fig. 6, fig. 6 is a schematic structural diagram of a network on chip provided by an embodiment of the present application, and fig. 6 shows a functional module 601 and two sub-networks on chip.

Each on-chip subnetwork comprises a routing module 602 and transmission channels for connecting adjacent routing modules 602.

In the example shown in fig. 6, in order to more intuitively distinguish between the first on-chip sub-network and the second on-chip sub-network, the transmission channel of the first on-chip sub-network and the transmission channel of the second on-chip sub-network are represented by solid lines and dashed lines, respectively. As shown in fig. 6, the first on-chip subnetwork includes 9 routing modules interconnected by solid lines, and the second on-chip subnetwork includes 9 routing modules interconnected by dashed lines.

In addition, the routing module 602 is connected with a specific functional module 601 through a transmission channel, so that data transmission between the routing module 602 and the functional module 601 is realized.

In the embodiment of the application, the routing module is used for following the data forwarding rule of the sub-network on the chip to which the routing module belongs and forwarding the data; the data comes from the function modules connected to themselves in the chip or from adjacent routing modules belonging to the same sub-network on the chip.

In the embodiment of the application, each functional module can be connected with at least two routing modules belonging to different on-chip subnetworks.

Fig. 6 shows 9 functional modules 601, wherein each functional module 601 connects routing modules belonging to a first on-chip sub-network and a second on-chip sub-network, respectively.

In the embodiment of the application, different data forwarding rules are preconfigured for different on-chip sub-networks. Specifically, to avoid the deadlock situation shown in fig. 5, a data forwarding rule may be configured in advance for each on-chip sub-network, so as to ensure that the data deadlock situation does not occur in each on-chip sub-network.

Namely, the data forwarding rule configured for the on-chip subnetwork is used for ensuring that: the routing module of the sub-network on the chip does not have data deadlock when forwarding data according to the data forwarding rule. The embodiment of the application is not limited to specific data forwarding rules.

Because the data forwarding rule for preventing the data deadlock is configured, connectivity among other functional modules in the chip is greatly affected when the functional modules in the chip are blocked. It should be noted that the blocking of the functional module means that the functional module has regional failure, that is, the data channels in the area where the functional module is located cannot be connected, including the data channels passing through the area in the on-chip bus.

For ease of understanding, the following description is provided in connection with FIG. 7. Fig. 7 is a schematic diagram of data transmission when a functional module in the network on chip is blocked. In fig. 7 9 routing modules are shown, as well as the data channels between the individual routing modules. To prevent data deadlock, assume that the configured data forwarding rules include: the routing modules of the odd columns only allow horizontal to vertical steering and the routing modules of the even columns only allow vertical to horizontal steering. If the data transmission from the routing module a to the routing module D is required, the data can be transmitted to the routing module B only when the functional modules in the dashed line frame in fig. 7 are blocked, and the routing module B cannot transmit the data to the routing module C because the routing module B is in even number row and does not allow horizontal to vertical steering. If the routing module B transmits data to the routing module E, the routing module E may further transmit data to the routing module F or the routing module G, but the routing module F and the routing module G are in odd columns, and do not allow vertical and horizontal steering, so that data cannot be transmitted to the routing module C and the routing module D.

Therefore, when the functional modules in the dashed line frame are blocked, the routing module A and the routing module C cannot be communicated, and the routing module A and the routing module D cannot be communicated, so that the communication between the functional modules is greatly affected.

In the embodiment of the application, different data forwarding rules are preconfigured for different on-chip sub-networks. When the function module is blocked, for the data which needs to be sent to the target function module by the source function module, if one of the on-chip sub-networks can not realize the data forwarding according to the data forwarding rules, the on-chip sub-networks with different data forwarding rules can realize the data forwarding.

For ease of understanding, the following description is provided in connection with fig. 7 and 8. Fig. 8 is another schematic diagram of data transmission when a block occurs in a functional module in the network on chip. Fig. 7 and 8 show a sub-network on chip, respectively, as a network on chip belonging to the same chip. The 9 routing modules shown in fig. 8 correspond one-to-one to the 9 routing modules in fig. 7. For example, the routing module a in fig. 8 and the routing module a in fig. 7 are connected to the same functional module, the routing module B in fig. 8 and the routing module B in fig. 7 are connected to the same functional module, and so on.

For the on-chip subnetwork shown in fig. 8, to prevent data deadlock, it is assumed that the configured data forwarding rules include: the routing modules of the odd columns allow only vertical to horizontal steering, and the routing modules of the even columns allow only horizontal to vertical steering. If the data transmission from the routing module a to the routing module d is required, the data can be transmitted to the routing module b first, and the routing module b can transmit the data to the routing module c and then the routing module c can transmit the data to the routing module d because the routing module b is in even number row and allows the horizontal to vertical direction change in the figure 8.

It can be seen that when the functional modules in the dashed frame are blocked, the routing module a and the routing module c can be communicated, and the routing module a and the routing module d can also be communicated.

The on-chip network provided by the embodiment of the application comprises at least two on-chip subnetworks, and different data forwarding rules are configured for different on-chip subnetworks. And the routing module is used for forwarding data according to the data forwarding rule of the sub-network on the chip. When the functional module of the chip has regional failure, for the data which needs to be sent to the target functional module by the source functional module, if one of the on-chip sub-networks can not realize data forwarding according to the data forwarding rules, the on-chip sub-networks with different data forwarding rules can realize data forwarding. Thus, in the case of partial functional module shielding, low latency and high connectivity of accesses between functional modules are still guaranteed.

In one embodiment of the application, the on-chip subnetwork is a mesh topology.

Specifically, the mesh topological structure is adopted, so that the expansion is convenient, and the access time delay cannot be multiplied along with the expansion of the core scale.

In one embodiment of the application, the data forwarding rule is used for limiting the forwarding direction of the data forwarded by the routing module so as to enable the data transmission of the sub-network on the chip to be deadlock-free; the steering includes: turning from the first direction to the second direction and turning from the second direction to the first direction; wherein the first direction is the horizontal direction of the grid topological structure; the second direction is the vertical direction of the grid topology.

Specifically, the on-chip subnetwork is in a grid topological structure, so that the horizontal direction and the vertical direction exist, and the steering of forwarding data by the routing module can be limited when the data forwarding rule is configured.

Since the grid topology has both horizontal and vertical directions, the steering of data includes two types: turning from the horizontal direction to the vertical direction and turning from the vertical direction to the horizontal direction.

When the data forwarding rule is configured, the data transmission of a single sub-network on a chip can be guaranteed to be free from deadlock by limiting the forwarding direction of the data forwarded by the routing module.

As an example, for a single sub-network on chip, limiting the data transfer of the routing module only supports turning from horizontal to vertical, then the sub-network on chip will not have a deadlock of the data transfer.

Therefore, in the embodiment of the application, when the on-chip subnetwork is in a grid topological structure, the data transmission of the on-chip subnetwork is free from deadlock by limiting the steering of forwarding data of the routing module, so that a cyclic deadlock waiting scene is avoided.

In one embodiment of the application, the network-on-chip includes a first sub-network-on-chip and a second sub-network-on-chip. When the network-on-chip comprises a first sub-network-on-chip and a second sub-network-on-chip, aiming at a first routing module and a second routing module which are connected with the same functional module, the data forwarding rule of the first sub-network-on-chip limits the turning of the first routing module, and the data forwarding rule of the sub-network-on-chip is different from the turning of the second routing module; wherein the first routing module belongs to a first on-chip subnetwork and the second routing module belongs to a second on-chip subnetwork.

As one example, the data forwarding rule limiting routing module of the first on-chip subnetwork only supports forwarding data in a first direction of rotation and the data forwarding rule limiting routing module of the second on-chip subnetwork only supports forwarding data in a second direction of rotation, wherein the first direction of rotation is different from the second direction of rotation.

For example, the routing module of the first on-chip sub-network only supports the change from the horizontal direction to the vertical direction, so that no data deadlock exists inside the first on-chip sub-network; and the routing module of the second on-chip sub-network only supports the direction change from the vertical direction to the horizontal direction, so that the data deadlock does not occur in the second on-chip sub-network.

As another example, the data forwarding rules of the first on-chip subnetwork restrict the routing modules of the odd columns to support forwarding data only in a first direction of rotation, and the routing modules of the even columns to support forwarding data only in a second direction of rotation; the data forwarding rules of the second on-chip subnetwork limit that the routing modules of the odd columns only support forwarding data in the second direction and that the routing modules of the even columns only support forwarding data in the first direction.

Likewise, neither the first on-chip subnetwork nor the second on-chip subnetwork will have a data deadlock.

And, because the data forwarding rules of the first on-chip sub-network and the second on-chip sub-network are different, the data forwarding path of the first on-chip sub-network and the data forwarding path of the second on-chip sub-network can compensate each other. If one of the on-chip sub-networks cannot realize data forwarding according to the data forwarding rules, the on-chip sub-networks with different data forwarding rules can be configured to realize data forwarding. Thus, in the case of partial functional module shielding, low latency and high connectivity of accesses between functional modules are still guaranteed.

In one embodiment of the present application, the data forwarding rules configured for different on-chip subnetworks satisfy the following conditions:

For any first data sent from the source functional module to the destination functional module, when there is a blocked functional module, at least one target on-chip sub-network can complete forwarding of the first data according to the configured data forwarding rule, and the forwarding path does not pass through the blocked functional module.

In a possible embodiment, the blocked functional module in the chip is determined at the time of delivery, so that the position of the blocked functional module can be considered when the data forwarding rule is configured, for any first data sent from the source functional module to the destination functional module, at least one target on-chip sub-network is ensured, the target on-chip sub-network can complete forwarding of the first data according to the configured data forwarding rule, and the forwarding path does not pass through the blocked functional module.

Furthermore, it should be noted that, to ensure that the first data sent from the source functional module to the destination functional module is transmitted through only one target on-chip sub-network, more on-chip sub-networks may need to be built, which increases complexity and cost of the on-chip network to some extent.

Therefore, when designing the on-chip sub-network and the data forwarding rule, connectivity of most routing nodes in a single on-chip sub-network is guaranteed, and data to be transmitted with a far path between the source functional module and the destination functional module can be transmitted through a plurality of on-chip sub-networks, see below.

In one embodiment of the present application, when the functional module is used as a source functional module for transmitting data, the functional module is used for determining a target on-chip subnetwork according to a routing table; a target path following a data forwarding rule exists in the target on-chip subnetwork; the target path is a path from the source functional module to the destination functional module; an reachable path following the data forwarding rules in each sub-network on chip is maintained in the routing table.

Specifically, since the topology structure and the data forwarding rule of each on-chip sub-network are determined, the reachable path in each on-chip sub-network following the data forwarding rule, that is, the determined reachable path in each on-chip sub-network following the data forwarding rule, may be maintained in the routing table.

The routing table can be stored in each functional module, or a storage module for storing the routing table is arranged in the chip, and the functional module accesses the storage module when needed to read the information in the routing table.

When the function module is used as a source function module for transmitting data, the source function module determines a target on-chip sub-network according to the information maintained in the routing table, namely, the data transmitted by the source function module can be transmitted to the target function module on the premise of following the data transmission rule of the target on-chip sub-network.

The determined target on-chip sub-network may be more than one, and the hop count with the smallest hop count may be preferentially selected, or load sharing of a plurality of on-chip sub-networks is considered, i.e. the data to be forwarded is dispersed into different on-chip sub-networks as much as possible.

After determining the target on-chip sub-network and the target path, the source function module generates a forwarding instruction based on the target path, wherein the forwarding instruction can comprise continuous left-turn operation instructions, right-turn operation instructions and straight-going operation instructions, data containing the forwarding instruction are sent to a routing module of the target on-chip sub-network connected with the source function module, and the routing module forwards according to the forwarding instruction. For example, the routing module performs data forwarding according to the operation instruction, and removes one operation instruction every time a routing module passes through, until the data is forwarded to the routing module connected to the destination functional module, and the routing module forwards the data to the destination functional module.

In the embodiment of the application, the on-chip network includes a plurality of on-chip sub-networks, and the configured data forwarding rules are different for each on-chip sub-network, so that the reachable paths of each on-chip sub-network following the data forwarding rules are different, and when the source function module needs to forward the data to the destination function module, the on-chip sub-network capable of completing the data forwarding can be selected according to the reachable paths of each on-chip sub-network maintained in the routing table. It can be seen that the reachable paths of different on-chip sub-networks compensate each other, and on the premise that deadlock does not occur in each on-chip sub-network, low delay and high connectivity of access between the functional modules are ensured.

In one embodiment of the application, when there is a blocked functional module in the chip; the routing table maintains the reachable paths of the function modules which follow the data forwarding rule and do not pass through the blocking in each on-chip sub-network.

Specifically, when there is a blocked functional module in the chip, the data channel included in the on-chip subnetwork cannot pass through the area where the blocked functional module is located, resulting in a reduction of the reachable paths, in this case, the routing table maintains the reachable paths of the functional modules that follow the data forwarding rule and do not pass through the blocked functional module in each on-chip subnetwork, and only these reachable paths are capable of forwarding data.

In one possible embodiment, the blocked functional module in the chip is determined at the time of shipment, in which case the maintenance reachable path in the routing table may be preconfigured.

Correspondingly, the source function module determines the target sub-network on chip according to the reachable paths of the function modules which follow the data forwarding rule and do not pass through the blocking in each sub-network on chip maintained in the routing table. Namely, the data sent by the source function module can be forwarded to the target function module on the premise of following the data forwarding rule of the target on-chip sub-network and not passing through the area where the blocking function module is located.

It can be seen that, in the embodiment of the present application, the on-chip network includes a plurality of on-chip sub-networks, and for each on-chip sub-network, the configured data forwarding rules are different, so that the reachable paths of each on-chip sub-network following the data forwarding rules are different, and if one of the on-chip sub-networks cannot implement data forwarding following the data forwarding rules, the on-chip sub-network configured with the different data forwarding rules can implement data forwarding. And under the condition that part of the functional modules are shielded, the reachable paths of the functional modules which follow the data forwarding rule and do not pass through the blocking can be selected according to the routing table, so that the low delay and the high connectivity of the access among the functional modules are ensured.

In one embodiment of the application, the functional module is further configured to: and forwarding the data from the self-connected routing module belonging to the first on-chip subnetwork to the self-connected routing module belonging to the second on-chip subnetwork.

Specifically, for the data sent from the source functional module to the destination functional module, if the data transmission cannot be completed only through a single on-chip sub-network, the data is allowed to be transmitted through more than one on-chip sub-network, that is, the functional module can be used as a relay node for data transmission, and the data from one on-chip sub-network is forwarded to the data of another on-chip sub-network.

As an example, the source functional module a needs to send data to the destination functional module B, and according to the information maintained in the routing table, the reachable paths of any on-chip subnetwork cannot complete data transmission, but by means of the reachable paths of the first on-chip subnetwork, data can be sent from the source functional module a to the functional module C, by means of the reachable paths of the second on-chip subnetwork, data can be sent from the functional module C to the destination functional module B, and then the functional module C can act as a relay node to forward data from the first on-chip subnetwork to the second on-chip subnetwork, so that data can be forwarded through more than one on-chip subnetwork.

Therefore, in the embodiment of the application, the functional modules can be used as relay nodes to forward the data from one on-chip sub-network to another on-chip sub-network, so that the data is transmitted through more than one on-chip sub-network, the high connectivity between the functional modules can be further improved, and too many on-chip sub-networks are not required to be configured, thereby reducing the complexity and cost of the on-chip network.

The embodiment of the application also provides a chip, which comprises a functional module and a network-on-chip, wherein the network-on-chip comprises at least two sub-networks; the on-chip subnetwork comprises a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks;

The routing module is used for following the data forwarding rule of the sub-network on the chip to which the routing module belongs and forwarding the data; the data come from the function modules connected to themselves in the chip or from adjacent routing modules belonging to the same sub-network on chip.

When the functional module of the chip has regional failure, for the data which needs to be sent to the target functional module by the source functional module, if one of the on-chip sub-networks can not realize data forwarding according to the data forwarding rules, the on-chip sub-networks with different data forwarding rules can realize data forwarding. Thus, in the case of partial functional module shielding, low latency and high connectivity of accesses between functional modules are still guaranteed.

Referring to fig. 9, a schematic flow chart of a method for transmitting data in a chip according to an embodiment of the present application includes the following steps:

S901: the source function module determines a target on-chip subnetwork according to the routing table; a target path following a data forwarding rule exists in the target on-chip subnetwork; the target path is a path from the source functional module to the destination functional module; an reachable path following the data forwarding rules in each sub-network on chip is maintained in the routing table.

S902: the source function module sends the data to a self-connected routing module belonging to the target on-chip sub-network; the data carries a forwarding instruction generated based on the target path, so that the routing module of the target on-chip subnetwork sends the data to the target functional module according to the forwarding instruction.

In the embodiment of the application, the on-chip network comprises a plurality of on-chip sub-networks, and the configured data forwarding rules are different for each on-chip sub-network, so that the reachable paths of the on-chip sub-networks following the data forwarding rules are different, and when the source function module needs to forward the data to the destination function module, the on-chip sub-network capable of completing the data forwarding can be selected according to the reachable paths of the on-chip sub-networks maintained in the routing table. It can be seen that the reachable paths of different on-chip sub-networks compensate each other, and on the premise that deadlock does not occur in each on-chip sub-network, low delay and high connectivity of access between the functional modules are ensured.

In one embodiment of the application, when there is a blocked functional module in the chip; the routing table maintains the reachable paths of the function modules which follow the data forwarding rule and do not pass through the blocking in each on-chip sub-network.

Correspondingly, the step of determining the target on-chip subnetwork by the source functional module according to the routing table comprises the following steps:

The source function module determines a target sub-network on chip according to the reachable paths of the function modules which follow the data forwarding rules and do not pass through the blocking in each sub-network on chip maintained in the routing table, wherein the target paths of the function modules which follow the data forwarding rules and do not pass through the blocking exist in the target sub-network on chip; the target path is the path from the source functional module to the destination functional module.

Specifically, when there is a blocked functional module in the chip, the routing table may maintain reachable paths of the functional modules that follow the data forwarding rule and do not pass through the blocked functional module in each on-chip subnetwork.

Therefore, when the target on-chip sub-network is determined, the on-chip sub-network which follows the data forwarding rule and does not pass through the target path of the blocked functional module is determined, that is, the data is transmitted through the target on-chip sub-network, so that the blocked functional module can be avoided, and the normal data transmission between the source functional module and the target functional module can be realized.

Therefore, when the functional module of the chip has regional failure, for the data which needs to be sent to the target functional module by the source functional module, if one of the on-chip sub-networks can not realize the data forwarding according to the data forwarding rule, the on-chip sub-network with different data forwarding rules can realize the data forwarding. Thus, in the case of partial functional module shielding, low latency and high connectivity of accesses between functional modules are still guaranteed.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk Solid STATE DISK (SSD)), etc.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the apparatus, electronic device, storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and references to the parts of the description of the method embodiments are only needed.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (11)

1. A network-on-chip, characterized in that,

The network on chip comprises at least two sub-networks on chip; the on-chip subnetwork comprises a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks;

The routing module is used for following the data forwarding rule of the sub-network on the chip to which the routing module belongs and forwarding data; the data comes from the function modules connected to themselves in the chip or from adjacent routing modules belonging to the same sub-network on chip.

2. The network on chip of claim 1, wherein the sub-network on chip is a mesh topology.

3. The network on chip of claim 2, wherein the network on chip is configured to,

The data forwarding rule is used for limiting the forwarding direction of the data forwarded by the routing module so as to enable the data transmission of the on-chip sub-network to be free from deadlock; the steering includes: turning from the first direction to the second direction and turning from the second direction to the first direction; wherein the first direction is a horizontal direction of the grid topology; the second direction is a vertical direction of the grid topology.

4. The network on chip of claim 2, wherein the network on chip is configured to,

The network-on-chip includes a first sub-network-on-chip and a second sub-network-on-chip.

5. The network on chip of claim 4, wherein the network on chip comprises a plurality of network elements,

For a first routing module and a second routing module which are connected with the same functional module, the data forwarding rule of the first on-chip sub-network limits the turning of the first routing module, and the data forwarding rule of the second on-chip sub-network is different from the turning of the second routing module; wherein the first routing module belongs to the first on-chip subnetwork and the second routing module belongs to the second on-chip subnetwork.

6. The network on chip of claim 1, wherein the network on chip is configured to,

The data forwarding rules configured for different on-chip subnetworks fulfil the following conditions:

For any first data sent from the source functional module to the destination functional module, when there is a blocked functional module, at least one target on-chip sub-network can complete forwarding of the first data according to a configured data forwarding rule, and a forwarding path does not pass through the blocked functional module.

7. The network on chip of any one of claims 1-6, wherein,

When the function module is used as a source function module for sending data, the function module is used for determining a target on-chip subnetwork according to a routing table; a target path following a data forwarding rule exists in the target on-chip sub-network; the target path is a path from the source functional module to the destination functional module; the routing table maintains the reachable paths following the data forwarding rule in each on-chip sub-network;

the function module is also used for sending the data to a self-connected routing module belonging to the target on-chip subnetwork; the data carries forwarding instructions generated based on the target path;

the routing module is specifically configured to forward data according to the forwarding instruction.

8. The network on chip of claim 7, wherein the network on chip is configured to,

When a blocked functional module exists in the chip; the routing table maintains the reachable paths of the function modules which follow the data forwarding rule and do not go through blocking in each on-chip sub-network;

The source function module is specifically configured to determine a target on-chip sub-network according to reachable paths of function modules that follow a data forwarding rule and do not pass through a block in each on-chip sub-network maintained in the routing table, where the target on-chip sub-network has a target path of function modules that follow the data forwarding rule and do not pass through the block; the target path is a path from the source functional module to the destination functional module.

9. A chip comprising a functional module, a network on chip according to any of claims 1-8.

10. A data transmission method in a chip is characterized in that,

The chip comprises: the system comprises a functional module and a network-on-chip, wherein the network-on-chip comprises a routing module; different data forwarding rules are pre-configured for different on-chip sub-networks;

The method comprises the following steps:

The source function module determines a target on-chip subnetwork according to the routing table; a target path following a data forwarding rule exists in the target on-chip sub-network; the target path is a path from the source functional module to the destination functional module; the routing table maintains the reachable paths following the data forwarding rule in each on-chip sub-network;

The source function module sends data to a self-connected routing module belonging to the target on-chip subnetwork; and the data carries a forwarding instruction generated based on the target path, so that the routing module of the target on-chip subnetwork sends the data to the target functional module according to the forwarding instruction.

11. The method of claim 10, wherein the step of determining the position of the first electrode is performed,

When a blocked functional module exists in the chip;

the routing table maintains the reachable paths of the function modules which follow the data forwarding rule and do not go through blocking in each on-chip sub-network;

The step of determining the target on-chip subnetwork by the source functional module according to the routing table comprises the following steps:

the source function module determines a target on-chip sub-network according to the reachable paths of the function modules which follow the data forwarding rules and do not pass through the blocking in each on-chip sub-network maintained in the routing table, wherein the target paths of the function modules which follow the data forwarding rules and do not pass through the blocking exist in the target on-chip sub-network; the target path is a path from the source functional module to the destination functional module.