CN110351192B - On-chip network oriented multi-level dynamic selectable composite routing control method - Google Patents
On-chip network oriented multi-level dynamic selectable composite routing control method Download PDFInfo
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- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
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Abstract
The invention discloses a multilayer dynamic selectable composite routing control method facing network on chip, which comprises the following steps: detecting bits marking the fault conditions of a local port and a downstream port, and determining the current data transmission condition; and an information bit extraction step: calculating and storing the routing information of the current data packet by a basic routing algorithm, and extracting the content of the required information bit according to the current data transmission condition; algorithm selection and information injection: on the basis of the basic routing algorithm, dynamically selecting a corresponding advanced routing algorithm according to the detection result of the flag bit, and injecting corresponding information into the algorithm for calculation; information refreshing and transmitting: the stored information is refreshed and transferred to the neighboring nodes. A multi-level dynamic selectable composite routing control method is provided, optimization is performed in the aspects of fault information layering processing, algorithm and circuit module coupling and the like, and the communication performance and the fault tolerance performance of the network on chip are effectively improved.
Description
Technical Field
The invention relates to the technical field of network on chip, in particular to a multilayer dynamically selectable composite routing control method facing to the network on chip.
Background
With the progress of integrated circuit technology and the expansion of interconnection scale of network on chip (NoC), the reliability problem of NoC becomes more and more serious, the design of the reliability of router structure and its fault-tolerant routing algorithm becomes hot, and the research classification for fault types is gradually formed: in the aspect of instantaneous faults, software regulation and electrical parameter regulation are mainly used; in the aspect of permanent faults, algorithm design and circuit fault tolerance design are mainly used. At present, the mainstream routing algorithm and the structure design of the router, such as an XY dimension order routing algorithm, a dynamic perception routing algorithm, a bypass routing structure, a cache-free routing structure, a granularity fragmentation routing structure and the like, have a single processing method and have the problem of unilateral over-design, such as a simple algorithm + a complex structure or a complex algorithm + a simple structure, which not only makes the algorithm and the structure design weakly coupled, but also wastes design resources. Meanwhile, the design relates to a single layer, and at present, a lot of algorithms and structural researches are only concentrated on a top network layer or a bottom circuit layer, and some defects exist in the aspect of effective layers of data transmission and fault processing.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a multilayer dynamically selectable composite routing control method facing to a network on chip, so that the communication performance and the fault tolerance performance of the network on chip are effectively improved.
The purpose of the invention is realized by the following technical scheme: a multi-level dynamic selectable composite type route control method facing network on chip comprises the following contents:
and (3) flag bit detection: detecting bits marking the fault conditions of a local port and a downstream port, and determining the current data transmission condition;
and an information bit extraction step: calculating and storing the routing information of the current data packet by a basic routing algorithm, and extracting the content of the required information bit according to the current data transmission condition;
algorithm selection and information injection: on the basis of the basic routing algorithm, dynamically selecting a corresponding advanced routing algorithm according to the detection result of the flag bit, and injecting corresponding information into the algorithm for calculation;
information refreshing and transmitting: the stored information is refreshed and transferred to the neighboring nodes.
The flag bit detection step comprises the following steps:
traversing the fault information of X and Y dimensions of the local port and the downstream port stored in the fixed position of the preparation caching module;
and determining the current data transmission condition according to the fault information, and recording the current data transmission condition in a flag.
The preparation cache module refers to a redundancy cache block designed in each routing node, is controlled by a clock, and is used for storing necessary information and dealing with the condition of single-point aggregation of a large amount of data when a fault occurs. The X and Y dimensions refer to the division of the positions of the routing nodes according to the direction of data transmission in the network-on-chip topology.
The information bit extraction step comprises the following steps:
calculating the routing information of the data packet by using an X-dimensional and Y-dimensional sequence routing algorithm as a basic algorithm;
storing the routing information and the local node information in a fixed position of a prepared cache module;
and comparing the flag information of the current data transmission condition, and extracting the corresponding information bit content.
The routing information comprises coordinate information of the node, a next hop fault node and a destination node; the local node information includes another port name information of the same dimension in the node.
The other port of the same dimension in the node is that the ports of the node are divided in X and Y dimension positions according to the direction of data transmitted in the network-on-chip topological structure in the routing node, and a pair of ports in the same dimension position correspond to each other.
The algorithm selection and information injection step comprises the following steps:
according to flag information for recording the current data transmission condition, when a local port fails, injecting the name information of another port with the same dimensionality in the node, and adopting an air bridge route;
according to the flag information for recording the current data transmission condition, when the downstream port is only the next hop port and has a fault, injecting the routing information, and adopting an improved Dy-XY routing;
if the two situations are not the same, the routing information is still used, and XY dimension order routing is adopted.
The flyover bridge is characterized in that when a local port fails, all arriving data except the data arriving at the local PE are transmitted to the other port with the same dimension in the corresponding node by using a designed simplified backup RC circuit module and then output; in the aspect of data transmission, it is equivalent to directly establish a transmission channel without arbitration between the pair of ports.
The information refreshing and transferring step comprises the following steps:
refreshing the content of the flag bit in the prepared cache module, transmitting the content to the adjacent node and covering the whole node;
judging the change of the zone bit, and when the local port and the downstream port both have faults, not refreshing the zone bit;
and refreshing the content of the information bits in the preparation cache module.
The refreshing action refers to that when a data packet is completely transmitted and a new data packet arrives, the content in the fixed position of the preparation cache module is updated after information extraction is carried out.
The invention has the beneficial effects that: the invention utilizes three routing algorithms in a compounding way, closely combines a top layer routing design and a bottom layer circuit module, unifies data transmission and fault processing, provides a multilayer dynamic selectable compound routing control method facing to the network on chip, optimizes the aspects of fault information layering processing, algorithm and circuit module coupling and the like, and effectively improves the communication performance and fault tolerance performance of the network on chip.
Drawings
FIG. 1 is a flow chart of a method of the present invention;
FIG. 2 is a diagram of a pre-caching module according to the present invention;
FIG. 3 is a flag signal throughout the entire control method of the present invention;
FIG. 4 is a schematic diagram illustrating a process of information bit extraction according to the present invention;
FIG. 5 is a schematic flow chart of algorithm selection and information injection according to the present invention;
FIG. 6 is a schematic diagram of a reduced backup RC module and flyover routing in accordance with the present invention;
fig. 7 is a schematic flow chart of an improved Dy-XY routing algorithm of the present invention;
FIG. 8 is a diagram of an information relay module for transmitting flag bits according to the present invention;
fig. 9 is a schematic diagram for illustrating the transmission manner of data and signals in the topology structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "upper", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings or orientations or positional relationships that the products of the present invention conventionally use, which are merely for convenience of description and simplification of description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
As shown in fig. 1, a multi-level dynamically selectable composite routing control method for a network on chip includes the following steps:
l1, flag bit detection: detecting bits marking the fault conditions of a local port and a downstream port, and determining the current data transmission condition;
l2, information bit extraction: calculating and storing the routing information of the current data packet by a basic routing algorithm, and extracting the content of the required information bit according to the current data transmission condition;
l3, algorithm selection and information injection: on the basis of the basic routing algorithm, dynamically selecting a corresponding advanced routing algorithm according to the detection result of the flag bit, and injecting corresponding information into the algorithm for calculation;
l4, information refreshing and transferring: the stored information is refreshed and transferred to the neighboring nodes.
Wherein the step L1 includes the following sub-steps:
l101, traversing the fault information of the local port and the downstream port (X and Y dimensions) stored in the fixed position of the preparation caching module;
and L102, determining the current data transmission condition according to the fault information, wherein 2 conditions needing to be judged exist: 1. whether the local port fails; 2. whether the downstream port failed. The current data transmission condition is recorded in flag.
The preparation cache module is a redundant cache block designed in each routing node, is controlled by a clock, and is used for storing necessary information and dealing with the condition of single-point aggregation of a large amount of data when a fault occurs. The XY dimension refers to the division of the position of each routing node according to the direction of data when the data is transmitted in the network-on-chip topology structure.
The detection of the fault information is the premise of fault-tolerant design, and the judgment of the fault condition is the main basis for adopting a fault-tolerant means. In the present invention, the collection of fault information is not the focus of discussion, and for all fault-tolerant designs, the key point is to have a clear understanding of the fault conditions at the beginning. Here, as shown in fig. 2, in the port design of the routing node, a storage space is additionally opened up as a preliminary cache under the condition of the original buffer, and preliminary cache modules are set up for all ports of the node except for NI. The module is 1/2 of the original buffer, is regulated and controlled by a clock, and generates data communication with a control module and an RC module in a port.
The determination of the data transmission condition occurs in the control module, the flag signal is a 3-bit binary signal, as shown in fig. 3, where the highest bit to the lowest bit sequentially represent the local port fault condition, the X-dimension downstream port fault condition, and the Y-dimension downstream port fault condition, and the high bit represents the occurrence of a fault: 1xx represents a local port fault, 010 represents an X-dimensional downstream port fault, 001 represents a Y-dimensional downstream port fault, and the remaining values all represent non-determination conditions. The flag signal plays a crucial role in the design of the present invention throughout the entire method steps.
Wherein the step L2 includes:
l201, calculating routing information of the data packet by using an XY dimension order routing algorithm as a basic algorithm;
l202, storing the routing information including the local node, the next hop fault node (X and Y dimensions), the coordinate information of the destination node and the information of the local node including the other port name information of the same dimension in the nodes in the fixed position of the preparation cache module;
l203, comparing the flag information of the current data transmission state, extracting the corresponding information bit content: 1. extracting local node information as long as the local port fails; 2. extracting routing information as long as the downstream port is a next hop port fault, and expanding a flag signal to mark the condition; 3. and when no fault exists, extracting the routing information.
The ports of the same dimension in the node are divided in XY dimension positions according to the direction of data transmitted in the network-on-chip topological structure in the routing node, and a pair of ports in the same dimension position correspond to each other.
The XY dimension sequence routing algorithm is a classic representative of a deterministic routing algorithm, and when no fault exists in a routing network, the XY dimension sequence routing algorithm is the most efficient and practical routing algorithm. In the invention, an XY dimension sequence routing algorithm is used as a basic algorithm, namely once a data packet enters (a first microchip arrives) a buffer of a port, XY dimension sequence routing algorithm calculation is firstly carried out in an RC module to obtain routing information and store the routing information, and as the XY dimension sequence routing algorithm executes a routing rule of 'X first and Y second' and considers the uncertainty of the position of an arrival node in the topology, namely the next hop can be X or Y, flag information needs to be compared, so that after the fault condition is further determined, accurate information is extracted and the flag information can be expanded possibly, and a basis is provided for subsequent algorithm selection and calculation, and the specific flow is shown in FIG. 4. Meanwhile, the routing information is also a required calculation value of a subsequent advanced algorithm. Meanwhile, the ports are divided in XY dimensions in each routing node, and the division is closely coupled with a basic XY dimension sequence routing algorithm and is also closely coupled with an advanced algorithm and circuit module design.
Wherein, the order rule of the algorithm selection and the information injection in the step L3 is:
firstly, according to flag information for recording the current data transmission condition, when a local port fails, injecting the name information of another port with the same dimensionality in a node, and adopting an 'flyover' route;
secondly, injecting coordinate information of a local node, a next hop fault node (X and Y dimensions) and a destination node according to flag information for recording the current data transmission condition when a downstream port is in fault for the next hop port, and adopting an improved Dy-XY route;
thirdly, the first and second conditions are removed, and in other conditions, the route information is injected, and the XY dimension order route is still adopted.
The 'flybridge' means that when a local port fails, all the arriving data, except the data arriving at the local PE, are all transmitted to the corresponding port with the same dimension in the node for output by using a designed reduced backup RC (route-Calculator) circuit module, and on the data transmission level, it is equivalent to directly establishing a transmission channel between the pair of ports without arbitration. Each "flyover" is a channel for unidirectional transmission.
The invention adopts a dynamic selectable composite routing algorithm, the general flow is shown in figure 5, and three routing algorithms are as follows: the 'flying bridge' routing algorithm, the improved Dy-XY routing algorithm and the XY dimension sequence routing calculation are started and converted by the control module according to the fault information and the data transmission condition. As shown in fig. 6, a reduced backup RC module is designed on the basis of the RC module existing in the node port, and the "flybridge" routing algorithm is executed separately. The other two algorithms are selectively executed in the original RC module. Due to the hardware design of the circuit module, the 'flying bridge' routing algorithm indicates that the local port has a permanent fault once enabled, and the 'flying bridge' routing algorithm focuses on data transmission on the local node, is irreversible and non-transferable, and permanently exists matchable other algorithms once enabled. The improved Dy-XY routing algorithm and the XY dimension sequence routing algorithm focus on data transmission of a next hop node, and a tightly coupled hardware design does not exist, so that the improved Dy-XY routing algorithm and the XY dimension sequence routing algorithm can be mutually converted under certain conditions. The simulation diagram of the 'flying bridge' route in the figure forms a transmission channel which avoids arbitration and is similar to a first-level pipeline, has advantages in time delay, and simultaneously activates the unused preparation cache at two ends of the same dimension to deal with single-point data burst. The design of the dynamic selectable composite algorithm enables the routing mechanism to play a role in multiple layers and cross layers, and fault tolerance is not limited to a single circuit level or a communication level any more, but is combined, so that the integral fault tolerance effect is obtained.
When the downstream port fault is matched with the next hop port, namely the next hop port fault, starting an improved Dy-XY routing algorithm, wherein the algorithm flow is as shown in FIG. 7, injecting routing information for calculation, judging whether a target node has a certain one-dimensional coordinate which is the same as that of the next hop node and is completely different from the coordinates of each dimension of the current node, and if not, continuing to execute a basic routing algorithm; if yes, judging whether the dimension of the next hop in the routing information is in X dimension, if not, executing XY dimension order routing, and if so, executing YX dimension order routing.
Wherein the step L4 includes:
l401, refreshing the content of the flag bit in the preliminary cache module, transmitting the content to an adjacent node and covering the whole node;
l402, judging the change of the zone bit, and when the local port and the downstream port both have faults, not refreshing the zone bit;
and L403, refreshing the content of the information bits in the preparation cache module.
The refreshing action refers to that after information extraction is carried out when one data packet is completely transmitted (the transmission of the tail microchip is finished) and a new data packet arrives (a head fragment and a tail fragment arrive at nodes), the content in the fixed position of the preparation cache module is updated.
In the invention, the updating of the information bit depends on the calculation of the microchip information of the data packet head, the updating of the flag bit depends on fault detection, a local BIST built-in self-test method is used for fault detection, and if and only if a permanent fault occurs, the fault is marked and updated, although other fault-tolerant designs exist in the circuit to preliminarily deal with the fault such as a redundant module, which does not belong to the scope of the invention. In order to achieve the purpose of information transmission, a ping-pong mechanism is established between the node and the adjacent nodes, and flag bit information is transmitted and responded under the control of a clock. Because the invention aims at permanent failure, when the local port and the downstream port in the zone bit fail, the irreversible change occurs, and similarly, the zone bit is not refreshed and ping-pong is stopped. As shown in fig. 8, an information transfer module is designed in each node, and receives the flag bit refresh information from the port of the peripheral node in response and transfers the flag bit refresh information to the port in the local node, and the module generates data communication with the port preparation storage module and the control module. Fig. 9 shows a 2X2 NoC topology, which shows a graph of data and related signals passing patterns between nodes when the multi-layer dynamically selectable composite routing control method is applied.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A multi-level dynamic selectable composite routing control method facing network on chip is characterized in that: the control method comprises the following steps:
and (3) flag bit detection: detecting bits marking the fault conditions of a local port and a downstream port, and determining the current data transmission condition;
extracting information bits: calculating and storing the routing information of the current data packet by a basic routing algorithm, and extracting the content of the required information bit according to the current data transmission condition;
the information bit extraction step specifically comprises:
l201, calculating routing information of the data packet by using an XY dimension order routing algorithm as a basic algorithm;
l202, storing the routing information including the coordinate information of the node, the next hop fault node, the destination node and the information of the local node including the other port name information of the same dimension in the node in a fixed position of a preparation cache module;
l203, comparing the flag information of the current data transmission state, extracting the corresponding information bit content: (1) extracting local node information as long as the local port fails; (2) extracting routing information as long as the downstream port is a next hop port fault, and expanding a flag signal to mark the condition; (3) when no fault exists, extracting routing information;
algorithm selection and information injection: on the basis of the basic routing algorithm, dynamically selecting a corresponding advanced routing algorithm according to the detection result of the flag bit, and injecting corresponding information into the algorithm for calculation;
the order rule in the algorithm selection and information injection steps is:
firstly, according to flag information for recording the current data transmission condition, when a local port fails, injecting the name information of another port with the same dimensionality in a node, and adopting an 'flyover' route;
secondly, injecting coordinate information of a local node, a next hop fault node and a destination node according to flag information for recording the current data transmission condition when a downstream port is in fault for the next hop port, and adopting an improved Dy-XY route;
thirdly, removing the first and second conditions, and injecting routing information under other conditions, and still adopting XY dimension order routing;
information refreshing and transferring: the stored information is refreshed and transferred to the neighboring nodes.
2. The on-chip network-oriented multi-level dynamic selectable composite routing control method according to claim 1, characterized in that: the flag bit detection comprises the following sub-steps:
traversing the fault information of X and Y dimensions of the local port and the downstream port stored in the fixed position of the preparation caching module;
and determining the current data transmission condition according to the fault information, and recording the current data transmission condition in a flag.
3. The on-chip network-oriented multilayer dynamically selectable composite routing control method according to claim 2, characterized in that: the preliminary cache module is a redundant cache block designed in each routing node, is controlled by a clock, is used for storing necessary information and is used for dealing with the condition of single-point aggregation of a large amount of data when a fault occurs, and the X dimension and the Y dimension are the position division of each routing node according to the direction of data transmission in a network-on-chip topology structure.
4. The on-chip network-oriented multi-level dynamic selectable composite routing control method according to claim 1, characterized in that: the routing information comprises coordinate information of the node, a next hop fault node and a destination node; the local node information includes another port name information of the same dimension in the node.
5. The on-chip network-oriented multilayer dynamically selectable composite routing control method according to claim 4, characterized in that: the other port of the same dimension in the node is that the ports of the node are divided in X and Y dimension positions according to the direction of data transmitted in the network-on-chip topological structure in the routing node, and a pair of ports in the same dimension position correspond to each other.
6. The on-chip network-oriented multi-level dynamic selectable composite routing control method according to claim 1, characterized in that: the information refreshing and transferring step comprises the sub-steps of:
refreshing the content of the flag bit in the prepared cache module, transmitting the content to the adjacent node and covering the whole node;
judging the change of the zone bit, and when the local port and the downstream port both have faults, not refreshing the zone bit;
and refreshing the content of the information bits in the preparation cache module.
7. The on-chip network-oriented multilayer dynamically selectable composite routing control method according to claim 6, characterized in that: the refreshing action refers to that when a data packet is completely transmitted and a new data packet arrives, the content in the fixed position of the preparation cache module is updated after information extraction is carried out.
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