CN103248465B - A kind of terminal processing device and terminal processing method - Google Patents
A kind of terminal processing device and terminal processing method Download PDFInfo
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Abstract
The invention provides a kind of terminal processing device and terminal processing method. Soft bit result after the demodulation of the terminal processing device of the present invention not buffer memory, this terminal processing device includes: channel equalization module; Fast retransmission merges memory element, and the process number corresponding to corresponding transmission mode is divided into many sub-memory element; Control module, carry out solving physical resource coupling, and merge the data of corresponding process number in memory element with described Fast retransmission and merge or write direct solving the physical resource present sub-frame data that obtain of coupling to described Fast retransmission and merge memory element, and carry out solving physical resource and map according to solving channel equalization block described in the data sequential control that physical resource coupling obtains, multiple-input and multiple-output detection, demodulate, unscramble; And channel decoding module, merge from described Fast retransmission and memory element reads previous sub-frame data and it is decoded.
Description
Technical field
The present invention relates to terminal processing techniques, more particularly, to suitable in LTE (LongTermEvolution, Long Term Evolution), the apparatus and method that can effectively reduce amount of storage.
Background technology
Long Term Evolution (LongTermEvolution, LTE) system descending speed can reach 100Mbps, up can reach 50Mbps, so big data rate is higher to the Capability Requirement of terminal data processing, due to data cached needs, therefore, the memory space required for terminal is also very big.
Fig. 1 illustrates the base band block diagram of terminal receiver conventional at present. This terminal receiver 10 includes Fast Fourier Transform Block 12, channel estimation module 14, channel equalization module 16, channel decoding module 18. Wherein Fast Fourier Transform Block 12 performs the FFT to time domain data and removes Cyclic Prefix (CyclicPrefix, the operation such as CP), channel estimation module 14 performs channel estimating, channel equalization module 16 performs multiple-input, multiple-output (MultipleInput-MultipleOutput, MIMO) operation such as detection, demodulation, channel decoding module performs channel decoding associative operation.
In addition, traditional terminal receiver 10 also includes multiple memory element to coordinate the process of above-mentioned module, including frequency domain data memory element (FD_RAM) 11, channel estimation results memory element (H_RAM) 13, for storing the memory element (SB_RAM) 17 of the soft bit result after demodulation, for storing the memory element (IR_RAM) 15 of descending Fast retransmission (HARQ) soft bit result, and decoding result memory element (D_RAM).
Generally, except Fast Fourier Transform Block 12 (Fast Fourier Transform Block is in units of OFDM symbol), the process unit of time of LTE is all in units of subframe. Therefore above-mentioned RAM, including the size that the size of FD_RAM, H_RAM, SB_RAM, D_RAM is all a sub-frame data amount, additionally consider the requirement processed in real time, process needs flowing water to carry out, therefore usual above-mentioned RAM needs to adopt the form of ping-pong buffer, say, that above-mentioned RAM is required for the size become twice as.
Owing to LTE data volume is big, needed for above-mentioned RAM, memory space is generally at about 20Mbit, and the area of baseband chip is a very big test by so big memory space, also considerably increases the cost of chip.
Therefore, need badly a kind of can save memory space and and then reduce baseband chip area scheme.
Summary of the invention
The invention provides a kind of terminal processing device and terminal processing method, it is therefore intended that reduce the memory element between symbol level and bit-level, by partial symbols level and partial bit level function are merged, directly utilize IR_RAM and store data. Relative to prior art, the present invention can greatly reduce the size of RAM, such that it is able to reduce baseband chip area, and and then reduces chip cost. The access conflict of RAM is avoided additionally by the IR_RAM method divided.
In one embodiment, the invention provides a kind of terminal processing device. Soft bit result after the demodulation of described terminal processing device not buffer memory, described terminal processing device includes:
Channel equalization module, carries out input signal solving physical resource mapping, multiple-input and multiple-output detection, demodulation and descrambling;
Fast retransmission merges memory element, is used for storing the soft bit result of descending Fast retransmission, and wherein said Fast retransmission merges memory element process number corresponding to corresponding transmission mode and is divided into many sub-memory element;
Control module, including solving physical channel capacity matching module, described solution physical channel capacity matching module connects described channel equalization module, the soft bit result that the demodulation of described channel equalization module obtains is not buffered and is directly entered described solution physical channel capacity matching module and carries out solving physical resource coupling, and merge the data merging of corresponding process number in memory element with described Fast retransmission by solving the physical resource present sub-frame data that obtain of coupling or write direct to described Fast retransmission merging memory element, described control module carries out solving channel equalization module described in the data sequential control that physical resource coupling obtains according to described solution physical channel capacity matching module and carries out solving physical resource mapping, multiple-input and multiple-output detects, demodulation, descrambling, and
Channel decoding module, merges from described Fast retransmission and reads previous sub-frame data memory element and it is decoded.
In one embodiment, this terminal processing device is applied to Long Term Evolution (LTE) standard.
In one embodiment, when described transmission mode is FDD, described Fast retransmission merges memory element and is divided into 8 sub-memory element corresponding to 8 processes.
In one embodiment, when described transmission mode is time division duplex, described Fast retransmission merges memory element and is divided into 168 sub-memory element, corresponding to the least common multiple of 4,6,7,8 processes.
In one embodiment, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into 56 sub-memory element, and on this basis, being further added by 4 sub-memory element, the described Fast retransmission that is sized to of every sub-memory element merges the 1/56 of memory element.
In one embodiment, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into first group of sub-memory element and second group of sub-memory element, described first group of sub-memory element includes 21 and is sized to the sub-memory element that described Fast retransmission merges the 1/24 of memory element, and described second group of sub-memory element includes 7 and be sized to the sub-memory element that described Fast retransmission merges the 1/56 of memory element.
In one embodiment, described terminal processing device also includes scrambler memory element, the scrambler that the storage of described scrambler memory element is precalculated, described channel equalization module directly reads described scrambler for described descrambling when physical channel capacity coupling has repetition. Wherein, described scrambler is hard bit.
In one embodiment, described control device also includes scrambler computing module, for when physical channel capacity coupling has repetition, scrambler sequence being divided into several sections and calculates in real time concurrently.
In one embodiment, described terminal processing device also includes buffer memory, for the rate-matched between described channel equalization module and described solution physical channel capacity matching module.
Present invention also offers a kind of terminal processing method. The method includes providing a Fast retransmission to merge memory element, is used for storing the soft bit result of descending Fast retransmission; Process number corresponding to corresponding transmission mode, merges described Fast retransmission memory element and is divided into many sub-memory element; The one control module including solving physical channel capacity matching module is provided, not buffered and be directly entered described solution physical channel capacity matching module after demodulation received data; Carry out solving physical resource coupling at described solution physical channel capacity matching module; At described solution physical channel capacity matching module, the data that the present sub-frame data that solution physical resource coupling obtains merge in memory element in the sub-memory element of corresponding same process number with described Fast retransmission are merged or write direct to described sub-memory element; Solve physical resource described in the data sequential control mated according to described solution physical resource in described control module to map, multiple-input and multiple-output detection, solve harmonic solution and disturb; And read previous sub-frame data from described Fast retransmission merging memory element and it is decoded.
In one embodiment, the method is applicable to Long Term Evolution (LTE) standard.
In one embodiment, when described transmission mode is FDD, described Fast retransmission is merged memory element and is divided into 8 sub-memory element corresponding to 8 processes.
In one embodiment, when described transmission mode is time division duplex, described Fast retransmission being merged memory element and is divided into 168 sub-memory element, described 168 sub-memory element are corresponding to the least common multiple of 4,6,7,8 processes.
In one embodiment, when described transmission mode is time division duplex, Fast retransmission described in 1 is merged memory element and is divided into 56 sub-memory element, and on this basis, be further added by the sub-memory element of 4 1/56 sizes merging memory element for original described Fast retransmission.
In one embodiment, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into first group of sub-memory element and second group of sub-memory element, described first group of sub-memory element includes 21 and is sized to the sub-memory element that described Fast retransmission merges the 1/24 of memory element, and described second group of sub-memory element includes 7 and be sized to the sub-memory element that described Fast retransmission merges the 1/56 of memory element.
In one embodiment, when physical channel capacity coupling has repetition, can storing precalculated scrambler, directly read described scrambler for descrambling when physical channel capacity coupling has repetition, wherein said scrambler is hard bit. Or, when physical channel capacity coupling has repetition, scrambler sequence is divided into several sections and calculates in real time concurrently.
Accompanying drawing explanation
Fig. 1 illustrates the base band block diagram of terminal receiver of the prior art;
Fig. 2 illustrates the block diagram of terminal processing device according to an embodiment of the invention; And.
Fig. 3 illustrates terminal processes flow chart according to an embodiment of the invention.
Detailed description of the invention
Develop simultaneously embodiment with reference to the accompanying drawings, and technical scheme is described in further detail.
Fig. 2 illustrates the block diagram of terminal processing device according to an embodiment of the invention. This terminal processing device 20 includes Fast Fourier Transform Block 22, channel estimation module 24, channel equalization module 26, controls module 27, channel decoding module 28. Wherein the framework of Fast Fourier Transform Block 22 and channel estimation module 24 and function are same as the prior art, repeat no more herein.
Additionally, the terminal processing device 20 of the present invention also includes frequency domain data memory element (FD_RAM) 21, channel estimation results memory element (H_RAM) 23, Fast retransmission merging memory element (IR_RAM') 25 and decoding result memory element (D_RAM) 29. Wherein, FD_RAM, the function of H_RAM and D_RAM is same as the prior art, repeats no more herein.
In this embodiment, increased one newly and controlled module 27, and eliminated the memory element (SB_RAM) 17 for storing the soft bit result after demodulation. The partial function of channel equalization module 26 is same as the prior art, but has partial function to move on in control module 27 and carry out. The partial function of channel decoding module 28 is also same as the prior art, but has partial function to move on in control module 27 and carry out. This control module 27 includes solving physical channel capacity matching module 280, complete the part of functions of original channel decoding module, namely solution physical resource coupling (including merging or the zero padding of physical resource) merges (during re-transmission) or the IR_RAM'25 that writes direct with the data of same process number in IR_RAM'25, controls module 27 according to the order solving the data sequential control channel equalization module solution physical resource mapping of physical resource coupling, MIMO detection, demodulation, descrambling.
Terminal processing device provided by the invention does not need the soft bit of buffer memory demodulation, but after the demodulation, directly carry out soft bit solving physical resource coupling, then (re-transmission data) or the IR_RAM'25 correspondence position (new data) that writes direct directly is merged with the data of the corresponding process in IR_RAM'25, channel decoding module carries out the function of all the other bit-level, including rate de-matching, Turbo decoding etc. Relative to prior art, the present invention can reduce the size of RAM and be about: for two aerial space multiplexings (13 [OFDMSymbols] * 12 [SC]-12 [RS]) * 100 [RB] * 6 [64QAM] * 2 [codeword] * 2 [table tennis] * 6 [bits/SoftBit] �� 2Mbit. Such that it is able to reduce baseband chip area, and and then reduce chip cost. The access conflict of RAM is avoided additionally by the method dividing Fast retransmission merging memory element 25.
Owing to the stream treatment of decoding needs, the present invention needs IR_RAM'25 is divided into sub-memory element several pieces more slightly smaller, and concrete division principle is in units of process.
For TDD mode (TDD), due to the difference of uplink-downlink configuration, descending process number is also different, as shown in the table. But LTE specification specifies again, IR_RAM stores up to the data of 8 processes, therefore the division to TDD, IR_RAM'25 size, it is necessary to meet 4,6,7,8 four kind of process number time control molding block 27 writes and channel decoding module 28 reads not conflicting mutually of data. The apparatus and method of the application solve be in harmonious proportion decoding time with decoding TTI (Transmission Time Interval) be stream treatment unit.
| TDD uplink/downlink configures | The maximum process number of Fast retransmission |
| 0 | 4 |
| 1 | 7 |
| 2 | 10 |
| 3 | 9 |
| 4 | 12 |
| 5 | 15 |
| 6 | 6 |
For the mode of frequency division duplexing (FDD) of LTE system, because descending the fixing of FDD is 8 processes, therefore having only to an IR_RAM'25 mean allocation, namely IR_RAM'25 replaces with 8 an equal amount of sub-memory element (sub-RAM). Control module 27 when processing current n-th sub-frame data, the data of the n-th subframe can be write in the sub-RAM that in IR_RAM', process number is identical with the current n-th corresponding process number of son. If it is required, the data first and in IR_RAM'25 should merge and then write again. Meanwhile, channel decoding module 28 is in the decoding of previous the sub-frame data carrying out the n-th subframe, and it needs to read data from IR_RAM'25. Characteristic according to Fast retransmission (HARQ), the sub-RAM of channel decoding module 28 data streams read and the sub-RAM RAM of certainly not same controlling 27 write data of module, namely will not produce conflict.
TDD mode (TDD) for LTE system, process basic identical with fdd mode, it is distinctive in that the division of IR_RAM'25, the division of TDD should meet access and not conflict, meet again and be conveniently used for storage 4, 6, 7, the data of 8 processes, simplest method is to take the least common multiple 168 of these numbers, it is divided into 168 equal sub-RAM by IR_RAM'25, then time actually used, if only four processes, then each process takies 42 sub-RAM, when having 6 processes, each process takies 28 sub-RAM, when having 7 processes, each process takies 24 sub-RAM, when having 8 process above, each process takies 21 sub-RAM. certainly, above-mentioned division methods is likely to excessively little, and too many little RAM area also can strengthen many by the area than an original whole RAM. another division methods is to stay certain redundancy to IR_RAM', such as original IR_RAM' is divided into 56 pieces of sub-RAM, additionally at the sub-RAM increasing by 4 pieces of formed objects, namely altogether with the sub-RAM of 60 block sizes are IR_RAM' 1/56, so, if process number is 4, each process takies 14 pieces of sub-RAM, if process number is 6, each process takies 10 sub-RAM, if process number is 7, each process takies 8 sub-RAM, if process number is more than 8, each process takies 7 sub-RAM, this division needs additionally to increase partial RAM (as increased 4/56IR_RAM' size in this example), this method needs to consider SB_RAM17 and IR_RAM'25 that new method saves and divides introduced area and increase, choose a kind of suitable division methods. another division methods is each sub-RAM size can not to wait, such as can with the sub-RAM (being designated as RAMA) of 21 block sizes are IR_RAM'25 1/24, be sized to plus 7 IR_RAM'25 1/56 sub-RAM (being designated as RAMB), so total size is also identical with original IR_RAM, this division methods, if process number is 4, three processes take 6 A respectively, and another one process takies 3 A+7B, if process number 6, five processes take 4 A respectively, and another one takies 1A+7B, if process number is 7, each process takies 3A+1B, if process number is more than 8, wherein 7 processes are each takies 3 A, and another one takies 7 B. therefore this division methods is being that block number is less, and RAM waste also a kind of less method.
Control module 27 and determine that channel equalization module 26 processes the order of data according to the data order solving physical channel capacity matching module, channel equalization module 26 carries out the demapping of data (finding the physical location that data are corresponding, take out data and corresponding channel estimating) according to this order, MIMO detects, solve harmonic solution disturbs. If be not repeated during physical channel capacity coupling, then the processing sequence of channel equalization module 26 is basic with existing method sequence consensus, and the order namely mapped according to physical resource carries out. If there being the process of repetition during physical channel capacity coupling, then the data by same bit difference repeatable position are needed to merge when solving physical channel capacity coupling, therefore the processing sequence of channel equalization module 26 is not just order (needing interval skip), interval is needed to process, each data symbol can individually be carried out by demapping, MIMO detection and demodulation, therefore order can also carry out according to the order of above-mentioned interval skip, but the scrambler needed due to descrambling is sequentially generated, it is therefore desirable to special handling. A kind of method is precalculated scrambler, and store, directly scrambler is taken from correspondence position during descrambling, this method needs storage scrambler, it is also required to certain memory space, but owing to scrambler has only to store hard bit (0/1), adopt compared with the soft bit after the demodulation of SB_RAM buffer memory with existing method, or memory space can be greatly saved, have only to 1/12 size (need 6 bits to be expressed as example with each soft bit, and existing method need not adopt ping-pong buffer) of SB_RAM. Another kind of method individually adopts scrambler computing module to calculate scrambler in real time, it is possible to scrambler sequence is divided into several sections of parallel computations, and the memory space so needed is only small, can obtain again the scrambler of interval skip position simultaneously.
Additionally, owing to channel equalization module 26 is symbol level processing module, and solving physical channel capacity matching module 280 is bit-level processing module, for the rate-matched between two modules, channel equalization module is also required to increase certain buffer memory, but the size of this buffer memory is the magnitude of several symbol, it is possible to ignore.
Fig. 3 illustrates terminal processes flow chart according to an embodiment of the invention. This terminal stream handling process includes, but not limited to following steps.
In step 302, it is provided that a Fast retransmission merges memory element, is used for storing the soft bit result of descending Fast retransmission.
In step 304, the process number corresponding to corresponding transmission mode, described Fast retransmission is merged memory element and is divided into many sub-memory element. When transmission mode is FDD, described Fast retransmission merges memory element and is divided into 8 sub-memory element corresponding to 8 processes. When described transmission mode is time division duplex, described Fast retransmission merges memory element and is divided into 168 sub-memory element, corresponding to the least common multiple of 4,6,7,8 processes. Or, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into 56 sub-memory element, and on this basis, being further added by 4 sub-memory element, the described Fast retransmission that is sized to of every sub-memory element merges the 1/56 of memory element. Or, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into first group of sub-memory element and second group of sub-memory element, described first group of sub-memory element includes 21 and is sized to the sub-memory element that described Fast retransmission merges the 1/24 of memory element, and described second group of sub-memory element includes 7 and be sized to the sub-memory element that described Fast retransmission merges the 1/56 of memory element.
Within step 306, after demodulation received data, directly obtain soft bit result input of demodulation is solved physical channel capacity matching module and not after demodulation described in buffer memory soft bit result.
In step 308, physical channel capacity matching module solution physical resource coupling is being solved.
In the step 310, the data that the present sub-frame data that solution physical resource coupling obtains merge in memory element in the sub-memory element of corresponding same process number with described Fast retransmission are merged or write direct to described sub-memory element.
In step 312, solve physical resource mapping according to the data sequential control of described solution physical resource coupling, multiple-input and multiple-output detects, solution harmonic solution is disturbed. if be not repeated during physical channel capacity coupling, then the order mapped according to physical resource carries out. if there being the process of repetition during physical channel capacity coupling, then the data by same bit difference repeatable position are needed to merge when solving physical channel capacity coupling, therefore demapping, multiple-input and multiple-output detects, the processing sequence that solution harmonic solution is disturbed is not just order, interval is needed to process, one of which method is precalculated scrambler, and store, directly scrambler is taken from correspondence position during descrambling, another kind of method is individually to adopt scrambler computing module to calculate scrambler in real time, scrambler sequence can be divided into several sections of parallel computations, the memory space so needed is only small, the scrambler of interval skip position can be obtained again simultaneously.
In a step 314, merging the memory element previous sub-frame data of reading from described Fast retransmission and it is being decoded. This makes the sub-RAM RAM of certainly not same that the sub-RAM the read data mated with solution physical resource write, and namely will not produce conflict.
The purpose of the present invention, technical scheme and beneficial effect have been carried out further detailed description by the above; it is it should be understood that; the above is not in order to limit the present invention; all within the spirit and principles in the present invention; any amendment of being made, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (19)
1. a terminal processing device, it is characterised in that the soft bit result after the demodulation of described terminal processing device not buffer memory, described terminal processing device includes:
Channel equalization module, carries out input signal solving physical resource mapping, multiple-input and multiple-output detection, demodulation and descrambling;
Fast retransmission merges memory element, is used for storing the soft bit result of descending Fast retransmission, and wherein said Fast retransmission merges memory element process number corresponding to corresponding transmission mode and is divided into many sub-memory element;
Control module, including solving physical channel capacity matching module, described solution physical channel capacity matching module connects described channel equalization module, the soft bit result that the demodulation of described channel equalization module obtains is not buffered and is directly entered described solution physical channel capacity matching module and carries out solving physical resource coupling, and merge the data merging of corresponding process number in memory element with described Fast retransmission by solving the physical resource present sub-frame data that obtain of coupling or write direct to described Fast retransmission merging memory element, described control module carries out solving channel equalization module described in the data sequential control that physical resource coupling obtains according to described solution physical channel capacity matching module and carries out solving physical resource mapping, soon enter and go out soon detection, demodulation, descrambling, and
Channel decoding module, merges from described Fast retransmission and reads previous sub-frame data memory element and it is decoded.
2. terminal processing device as claimed in claim 1, it is characterised in that described terminal processing device is applied to Long Term Evolution (LTE) standard.
3. terminal processing device as claimed in claim 2, it is characterised in that when described transmission mode is FDD, described Fast retransmission merges memory element and is divided into 8 sub-memory element corresponding to 8 processes.
4. terminal processing device as claimed in claim 2, it is characterised in that when described transmission mode is time division duplex, described Fast retransmission merges memory element and is divided into 168 sub-memory element, corresponding to the least common multiple of 4,6,7,8 processes.
5. terminal processing device as claimed in claim 2, it is characterized in that, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into 56 sub-memory element, and on this basis, being further added by 4 sub-memory element, the described Fast retransmission that is sized to of every sub-memory element merges the 1/56 of memory element.
6. terminal processing device as claimed in claim 2, it is characterized in that, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into first group of sub-memory element and second group of sub-memory element, described first group of sub-memory element includes 21 and is sized to the sub-memory element that described Fast retransmission merges the 1/24 of memory element, and described second group of sub-memory element includes 7 and be sized to the sub-memory element that described Fast retransmission merges the 1/56 of memory element.
7. terminal processing device as claimed in claim 1, it is characterized in that, described terminal processing device also includes scrambler memory element, the scrambler that the storage of described scrambler memory element is precalculated, described channel equalization module directly reads described scrambler for described descrambling when physical channel capacity coupling has repetition.
8. terminal processing device as claimed in claim 7, it is characterised in that described scrambler is hard bit.
9. terminal processing device as claimed in claim 1, it is characterised in that described control device also includes scrambler computing module, calculates concurrently in real time for scrambler sequence being divided into several sections when physical channel capacity coupling has repetition.
10. terminal processing device as claimed in claim 1, it is characterised in that described terminal processing device also includes a buffer memory, for the rate-matched between described channel equalization module and described solution physical channel capacity matching module.
11. a terminal processing method, it is characterised in that including:
There is provided a Fast retransmission to merge memory element, be used for storing the soft bit result of descending Fast retransmission;
Process number corresponding to corresponding transmission mode, merges described Fast retransmission memory element and is divided into many sub-memory element;
The one control module including solving physical channel capacity matching module is provided, not buffered and be directly entered described solution physical channel capacity matching module after demodulation received data;
Carry out solving physical resource coupling at described solution physical channel capacity matching module;
At described solution physical channel capacity matching module, the data that the present sub-frame data that solution physical resource coupling obtains merge in memory element in the sub-memory element of corresponding same process number with described Fast retransmission are merged or write direct to described sub-memory element;
Carry out solving solution physical resource mapping described in the data sequential control that physical resource mates, multiple-input and multiple-output detection, demodulation in described control module according to described solution physical channel capacity matching module, unscramble; And
Merge memory element from described Fast retransmission read previous sub-frame data and it is decoded.
12. method as claimed in claim 11, it is characterised in that described method is applied to Long Term Evolution (LTE) standard.
13. method as claimed in claim 12, it is characterised in that when described transmission mode is FDD, described Fast retransmission is merged memory element and is divided into 8 sub-memory element corresponding to 8 processes.
14. method as claimed in claim 12, it is characterised in that when described transmission mode is time division duplex, described Fast retransmission being merged memory element and is divided into 168 sub-memory element, described 168 sub-memory element correspond to 4,6, the least common multiple of 7,8 processes.
15. method as claimed in claim 12, it is characterized in that, when described transmission mode is time division duplex, Fast retransmission described in 1 is merged memory element and is divided into 56 sub-memory element, and on this basis, it is further added by the sub-memory element of 4 1/56 sizes merging memory element for original described Fast retransmission.
16. method as claimed in claim 12, it is characterized in that, when described transmission mode is time division duplex, described Fast retransmission is merged memory element and is divided into first group of sub-memory element and second group of sub-memory element, described first group of sub-memory element includes 21 and is sized to the sub-memory element that described Fast retransmission merges the 1/24 of memory element, and described second group of sub-memory element includes 7 and be sized to the sub-memory element that described Fast retransmission merges the 1/56 of memory element.
17. method as claimed in claim 11, it is characterised in that described method also includes the scrambler that storage is precalculated, directly read described scrambler for descrambling when physical channel capacity coupling has repetition.
18. method as claimed in claim 17, it is characterised in that described scrambler is hard bit.
19. method as claimed in claim 11, it is characterised in that described method also includes, when physical channel capacity coupling has repetition, scrambler sequence is divided into several sections and calculates in real time concurrently.
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| CN113452425B (en) * | 2020-03-24 | 2022-07-22 | 大唐移动通信设备有限公司 | Data processing method and device |
| WO2022061792A1 (en) * | 2020-09-27 | 2022-03-31 | Qualcomm Incorporated | Storage-free harq process |
| CN113225161B (en) * | 2021-04-14 | 2022-09-13 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | 5G terminal PDCCH MIMO detection accelerator and design method |
| CN118019119B (en) * | 2024-04-09 | 2024-06-25 | 南京创芯慧联技术有限公司 | Communication data processing device and method compatible with LTE standard and NR standard |
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