CN103248465A - Terminal processing device and terminal processing method - Google Patents
Terminal processing device and terminal processing method Download PDFInfo
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Abstract
The invention provides a terminal processing device and a terminal processing method. The terminal processing device does not cache a soft bit result after demodulation, and comprises a channel equalization module, a quick retransmission and merge storage unit, a control module and a channel decoding module, wherein the quick retransmission and merge storage unit is divided into a plurality of sub-storage units according to progresses corresponding to relevant transmission modes; the control module performs solution physical resource matching, merges current sub-frame data acquired by the solution physical resource matching and data with a corresponding progress number in the quick retransmission and merge storage unit, or directly writes the current sub-frame data in the quick retransmission and merge storage unit, and controls the channel equalization module to perform the solution physical resource mapping, multiple input multiple output detection, demodulation and descramble according to a data sequence acquired by the solution physical resource matching; and the channel decoding module reads the previous sub-frame data from the quick retransmission and merge storage unit and decodes the sub-frame data.
Description
Technical field
The present invention relates to the terminal processes technology, more specifically, relate to and be applicable to LTE apparatus and method (Long Term Evolution, Long Term Evolution), that can effectively reduce memory space.
Background technology
Long Term Evolution (Long Term Evolution, LTE) system descending speed can reach 100Mbps, uply can reach 50Mbps, the Capability Requirement that so big data rate is handled terminal data is than higher, because data cached needs, therefore, the needed memory space of terminal is also very big.
Fig. 1 illustrates the base band block diagram of terminal receiver commonly used at present.This terminal receiver 10 comprises fast fourier transform module 12, channel estimation module 14, channel equalization module 16, channel decoding module 18.Wherein fast fourier transform module 12 is carried out FFT conversion and removal Cyclic Prefix (the Cyclic Prefix to time domain data, operation such as CP), channel estimation module 14 is carried out channel estimating, channel estimation module 14 is carried out multiple-input, multiple-output (Multiple Input-Multiple Output, MIMO) operations such as detection, demodulation, the channel decoding module is carried out the channel decoding associative operation.
In addition, traditional terminal receiver 10 comprises that also a plurality of memory cell are to cooperate the processing of above-mentioned module, comprising frequency domain data memory cell (FD_RAM) 11, channel estimation results memory cell (H_RAM) 13, the memory cell (SB_RAM) 17 that is used for storage demodulation soft bit result afterwards, the memory cell (IR_RAM) 15 that is used for the soft bit result of storage descending quick re-transmission (HARQ), and decode results memory cell (D_RAM).
Usually, except fast fourier transform module 12 (the fast fourier transform module is unit with the OFDM symbol), the processing time unit of LTE all is to be unit with the subframe.So above-mentioned RAM, the size that comprises FD_RAM, H_RAM, SB_RAM, D_RAM all is the size of a sub-frame data amount, consider the requirement of processing in real time in addition, processing needs flowing water to carry out, therefore common above-mentioned RAM need adopt the form of ping-pong buffer, that is to say that above-mentioned RAM needs to become the size of twice.
Because the LTE data volume is big, about 20Mbit, so big memory space is a very big test to the area of baseband chip to the required memory space of above-mentioned RAM, has also increased the cost of chip greatly usually.
Therefore, need a kind of scheme that can save memory space also and then reduce the baseband chip area badly.
Summary of the invention
The invention provides a kind of terminal processes device and terminal processing method, purpose is to reduce the memory cell between symbol level and the bit-level, by part symbol level and partial bit level function are merged, directly utilizes IR_RAM storage data.With respect to prior art, the present invention can significantly reduce the size of RAM, thereby can reduce the baseband chip area, and and then reduction chip cost.The method of dividing by IR_RAM is avoided the access conflict of RAM in addition.
In one embodiment, the invention provides a kind of terminal processes device.Described terminal processes device is buffer memory demodulation soft bit result afterwards not, and described terminal processes device comprises:
The channel equalization module is separated physical resource mapping, multiple-input and multiple-output detection, demodulation and descrambling to input signal;
Re-transmission merges memory cell fast, is used for the soft bit result of the descending quick re-transmission of storage, and wherein said quick re-transmission merges the corresponding corresponding process number of transmission mode of memory cell basis and is divided into a plurality of sub-memory cell;
Control module, separate the physical resource coupling, and will separate data that current sub-frame data that physical resource coupling obtains and described quick re-transmission merge corresponding process number in the memory cell and merge or write direct to described quick re-transmission and merge memory cell, and mate the described channel equalization module of data sequential control that obtains and separate physical resource mapping, multiple-input and multiple-output detection, demodulation, descrambling according to separating physical resource; And
The channel decoding module merges from described quick re-transmission and to read previous sub-frame data the memory cell and it is deciphered.
In one embodiment, this terminal processes device is applied to Long Term Evolution (LTE) standard.
In one embodiment, when described transmission mode was Frequency Division Duplexing (FDD), described quick re-transmission merging memory cell was divided into 8 sub-memory cell corresponding to 8 processes.
In one embodiment, when described transmission mode was time division duplex, described quick re-transmission merged memory cell and is divided into 168 sub-memory cell, corresponding to 4,6, and the least common multiple of 7,8 processes.
In one embodiment, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into 56 sub-memory cell, and on this basis, increase by 4 sub-memory cell again, the size of each sub-memory cell is that described quick re-transmission merges 1/56 of memory cell.
In one embodiment, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into first group of sub-memory cell and second group of sub-memory cell, described first group of sub-memory cell comprises that 21 sizes are 1/24 the sub-memory cell that described quick re-transmission merges memory cell, and described second group of sub-memory cell comprises that 7 sizes are 1/56 the sub-memory cell that described quick re-transmission merges memory cell.
In one embodiment, described control module comprises separates physical channel capacity matching module, and the data that described channel equalization module is handled according to described solution physical channel capacity matching module are separated physical resource mapping, multiple-input and multiple-output detection, demodulation, descrambling in proper order.
In one embodiment, described terminal processes device also comprises the scrambler memory cell, the scrambler that described scrambler cell stores is calculated in advance, described channel equalization module directly read described scrambler to be used for described descrambling when physical channel capacity coupling has repetition.Wherein, described scrambler is hard bit.
In one embodiment, described control device also comprises the scrambler computing module, is used for when physical channel capacity coupling has repetition, scrambler sequence is divided into several sections calculates in real time concurrently.
In one embodiment, described terminal processes device also comprises buffer memory, is used for the rate-matched between described channel equalization module and the described solution physical channel capacity matching module.
The present invention also provides a kind of terminal processing method.This method comprises provides one to retransmit the merging memory cell fast, is used for the soft bit result of the descending quick re-transmission of storage; According to the corresponding process number of corresponding transmission mode, described quick re-transmission is merged memory cell be divided into a plurality of sub-memory cell; The soft bit result that directly demodulation is obtained after the data that demodulation receives is separated the physical resource mapping and the soft bit result after the described demodulation of buffer memory not; Solution physical resource coupling; Merge the data merging in the sub-memory cell of corresponding same process in the memory cell number or write direct to described sub-memory cell separating current sub-frame data that the physical resource coupling obtains and described quick re-transmission; Disturb according to the described solution physical resource mapping of the data sequential control of described solution physical resource coupling, multiple-input and multiple-output detection, demodulation; And merge memory cell from described quick re-transmission and read previous sub-frame data and it is deciphered.
In one embodiment, this method is applicable to Long Term Evolution (LTE) standard.
In one embodiment, when described transmission mode is Frequency Division Duplexing (FDD), described quick re-transmission is merged memory cell be divided into 8 sub-memory cell corresponding to 8 processes.
In one embodiment, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into 168 sub-memory cell, described 168 sub-memory cell are corresponding to 4,6, the least common multiple of 7,8 processes.
In one embodiment, when described transmission mode is time division duplex, 1 described quick re-transmission is merged memory cell be divided into 56 sub-memory cell, and on this basis, increase by 4 sub-memory cell that merge 1/56 size of memory cell for original described quick re-transmission again.
In one embodiment, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into first group of sub-memory cell and second group of sub-memory cell, described first group of sub-memory cell comprises that 21 sizes are 1/24 the sub-memory cell that described quick re-transmission merges memory cell, and described second group of sub-memory cell comprises that 7 sizes are 1/56 the sub-memory cell that described quick re-transmission merges memory cell.
In one embodiment, when physical channel capacity coupling has repetition, can store and calculate good scrambler in advance, directly read described scrambler to be used for descrambling when physical channel capacity coupling has repetition, wherein said scrambler is hard bit.Perhaps, when physical channel capacity coupling has repetition, scrambler sequence is divided into several sections calculates in real time concurrently.
Description of drawings
Fig. 1 illustrates the base band block diagram of terminal receiver of the prior art;
Fig. 2 illustrates the block diagram of terminal processes device according to an embodiment of the invention; And.
Fig. 3 illustrates terminal processes flow chart according to an embodiment of the invention.
Embodiment
The embodiment that develops simultaneously with reference to the accompanying drawings is described in further detail technical scheme of the present invention.
Fig. 2 illustrates the block diagram of terminal processes device according to an embodiment of the invention.This terminal processes device 20 comprises fast fourier transform module 22, channel estimation module 24, channel equalization module 26, control module 27, channel decoding module 28.Wherein framework and the function of fast fourier transform module 22 and channel estimation module 24 are same as the prior art, repeat no more herein.
In addition, terminal processes device 20 of the present invention also comprises frequency domain data memory cell (FD_RAM) 21, channel estimation results memory cell (H_RAM) 23, re-transmission merges memory cell (IR_RAM ') 25 and decode results memory cell (D_RAM) 29 fast.Wherein, FD_RAM, the function of H_RAM and D_RAM is same as the prior art, repeats no more herein.
In this embodiment, increase a control module 27 newly, and removed the memory cell (SB_RAM) 17 that is used for storage demodulation soft bit result afterwards.The partial function of channel equalization module 26 is same as the prior art, carries out but there is partial function to move on in the control module 27.The partial function of channel decoding module 28 is also same as the prior art, carries out but there is partial function to move on in the control module 27.This control module 27 comprises separates physical channel capacity matching module 280, finish the part of functions of original channel decoding module, namely separate physical resource coupling (comprising merging or the zero padding of physical resource), with IR_RAM ' 25 in the data of same process number merge (during re-transmission) or the IR_RAM ' 25 that writes direct, control module 27 is according to the order of the data sequential control channel equalization module solution physical resource mapping of separating the physical resource coupling, MIMO detection, demodulation, descrambling.
Terminal processes device provided by the invention does not need the soft bit of buffer memory demodulation, but after demodulation, directly soft bit is separated the physical resource mapping, then directly with IR_RAM ' 25 in the data of corresponding process merge (data retransmission) or write direct IR_RAM ' 25 correspondence positions (new data), the channel decoding module is carried out the function of all the other bit-level, comprises separating rate-matched, Turbo decoding etc.With respect to prior art, the size that the present invention can reduce RAM is about: with two aerial space multiplexings be example (13[OFDM Symbols] * 12[SC]-12[RS]) * 100[RB] * 6[64QAM] * 2[codeword] * 2[table tennis] * 6[bits/SoftBit] ≈ 2Mbit.Thereby can reduce the baseband chip area, and and then reduction chip cost.Avoid the access conflict of RAM in addition by the method for dividing quick re-transmission merging memory cell 25.
Because the stream treatment of decoding needs, the present invention need be divided into IR_RAM ' more than 25 a little bit smaller slightly sub-memory cell, and concrete division principle is to be unit with the process.
For TDD mode (TDD), because the difference of uplink-downlink configuration, descending process number is also different, as shown in the table.But the LTE standard stipulates that again IR_RAM stores the data of 8 processes at most, therefore to TDD, and the division of IR_RAM ' 25 sizes, needs satisfy 4,6,7, control module 27 write with channel decoding module 28 and reads not conflicting mutually of data when 8 four kind of process counted.The application's apparatus and method TTI (Transmission Time Interval) with decoding when separating mediation decoding is the unit of stream treatment.
| TDD is up/downstream arrangements | The quick maximum process number that retransmits |
| 0 | 4 |
| 1 | 7 |
| 2 | 10 |
| 3 | 9 |
| 4 | 12 |
| 5 | 15 |
| 6 | 6 |
For the mode of frequency division duplexing (FDD) of LTE system because FDD descending fixedly be 8 processes, therefore only need get final product IR_RAM ' 25 mean allocation i.e. 8 onesize sub-memory cell of IR_RAM ' 25 usefulness (sub-RAM) replacement.Control module 27 can write the data of n subframe among the middle process number of the IR_RAM ' sub-RAM identical with current n sub corresponding process number when handling current n sub-frame data.If desired, should be earlier and the data among the IR_RAM ' 25 merge and then write.Meanwhile, the decoding of channel decoding module 28 sub-frame data before carrying out n subframe, it need read data from IR_RAM ' 25.According to the characteristic of quick re-transmission (HARQ), the sub-RAM of the sub-RAM of channel decoding module 28 data streams reads and control module 27 data that write is same sub-RAM certainly not, namely can not produce conflict.
TDD mode (TDD) for the LTE system, handle basic identical with fdd mode, difference is the division of IR_RAM ' 25, the division of TDD should be satisfied visit and not conflict, satisfy the convenient storage 4 that is used for again, 6,7, the data of 8 processes, the simplest method is to get the least common multiple 168 of these several numbers, is about to IR_RAM ' 25 and is divided into 168 equal sub-RAM, when reality is used then, if have only four processes, then each process takies 42 sub-RAM, and when 6 processes were arranged, each process took 28 sub-RAM, when 7 processes are arranged, each process takies 24 sub-RAM, and when 8 above processes were arranged, each process took 21 sub-RAM.Certainly, above-mentioned division methods may be too little, and too many little RAM area also can strengthen many than the area of an original whole RAM.Another division methods is to stay certain redundancy to IR_RAM ', for example original IR_RAM ' is divided into 56 sub-RAM, in addition at the sub-RAM that increases by 4 identical sizes, namely be 1/56 the sub-RAM of IR_RAM ' altogether with 60 block sizes, like this, if the process number is 4, each process takies 14 sub-RAM, if the process number is 6, each process takies 10 sub-RAM, if the process number is 7, each process takies 8 sub-RAM, if the process number is more than 8, each process takies 7 sub-RAM, this division needs the extra partial RAM (as increasing 4/56IR_RAM ' size in this example) that increases, and this method need be taken all factors into consideration SB_RAM17 that new method saves and IR_RAM ' 25 and divides the area of introducing and increase, and chooses a kind of suitable division methods.Another division methods is each sub-RAM size can not wait, can be 1/24 the sub-RAM (being designated as RAMA) of IR_RAM ' 25 with 21 block sizes for example, add that 7 sizes are 1/56 the sub-RAM (being designated as RAM B) of IR_RAM ' 25, the total like this size also IR_RAM with original is identical, this division methods, take 6 A respectively if the process number is 4, three processes, the another one process takies 3 A+7B; If several 6, five processes of process take 4 A respectively, another one takies 1A+7B; If the process number is 7, each process takies 3A+1B; If the process number is greater than 8, wherein 7 processes each take 3 A, another one takies 7 B.Therefore this division methods is being that the block number is less, and RAM wastes also less a kind of method.
Control module 27 is determined the order of channel equalization module 26 deal with data in proper order according to the data of separating physical channel capacity matching module, channel equalization module 26 is disturbed according to solution mapping (find data corresponding physical position, take out data and corresponding channel estimating), MIMO detection, demodulation that this carries out data in proper order.If do not carry out repetition during physical channel capacity coupling, then basic the and existing method sequence consensus of the processing sequence of channel equalization module 26 namely carries out according to the order of physical resource mapping.If the process of repetition is arranged during physical channel capacity coupling, then when separating physical channel capacity coupling, the data of the different repeatable position of same bit need be merged, therefore the processing sequence of channel equalization module 26 just is not (the needing interval skip) of order, need to handle at interval, separating mapping, MIMO detection and demodulation can carry out each data symbol separately, therefore order also can be carried out according to the order of above-mentioned interval skip, but generate because the scrambler that descrambling needs is order, therefore need special processing.A kind of method is to have calculated scrambler in advance, and storage, directly getting scrambler from correspondence position during descrambling gets final product, this method need be stored scrambler, also needs certain memory space, but because scrambler only need be stored hard bit (0/1), compare with the soft bit after existing method adopts the demodulation of SB_RAM buffer memory, still can save memory space greatly, only need 1/12 size (be shown example with 6 table of bits of each soft bit needs, and existing method not needing to adopt ping-pong buffer) of SB_RAM.Another kind method adopts the scrambler computing module to calculate scrambler in real time separately, scrambler sequence can be divided into several sections parallel computations, and the memory space of Xu Yaoing is very little like this, can obtain the scrambler of interval skip position again simultaneously.
In addition, because channel equalization module 26 is-symbol level processing modules, and solution physical channel capacity matching module 280 is bit-level processing modules, for the rate-matched between two modules, in the channel equalization module, also need to increase certain buffer memory, but the size of this buffer memory is the magnitude of several symbols, can ignore.
Fig. 3 illustrates terminal processes flow chart according to an embodiment of the invention.This terminal stream handling process includes, but not limited to following steps.
In step 302, provide one to retransmit the merging memory cell fast, be used for the soft bit result of the descending quick re-transmission of storage.
In step 304, according to the corresponding process number of corresponding transmission mode, described quick re-transmission is merged memory cell be divided into a plurality of sub-memory cell.When transmission mode was Frequency Division Duplexing (FDD), described quick re-transmission merging memory cell was divided into 8 sub-memory cell corresponding to 8 processes.When described transmission mode was time division duplex, described quick re-transmission merged memory cell and is divided into 168 sub-memory cell, corresponding to 4,6, and the least common multiple of 7,8 processes.Perhaps, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into 56 sub-memory cell, and on this basis, increase by 4 sub-memory cell again, the size of each sub-memory cell is that described quick re-transmission merges 1/56 of memory cell.Perhaps, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into first group of sub-memory cell and second group of sub-memory cell, described first group of sub-memory cell comprises that 21 sizes are 1/24 the sub-memory cell that described quick re-transmission merges memory cell, and described second group of sub-memory cell comprises that 7 sizes are 1/56 the sub-memory cell that described quick re-transmission merges memory cell.
In step 306, the soft bit result that directly demodulation is obtained after the data that demodulation receives is separated the physical resource mapping and the soft bit result after the described demodulation of buffer memory not.
In step 308, separate the physical resource coupling.
In step 310, merge the data merging in the sub-memory cell of corresponding same process in the memory cell number or write direct to described sub-memory cell separating current sub-frame data that the physical resource coupling obtains and described quick re-transmission.
In step 312, disturb according to the described solution physical resource mapping of the data sequential control of described solution physical resource coupling, multiple-input and multiple-output detection, demodulation.If do not carry out repetition during physical channel capacity coupling, then carry out according to the order of physical resource mapping.If the process of repetition is arranged during physical channel capacity coupling, then when separating physical channel capacity coupling, the data of the different repeatable position of same bit need be merged, therefore separate mapping, multiple-input and multiple-output detects, the processing sequence that demodulation is disturbed just is not order, need to handle at interval, wherein a kind of method is to have calculated scrambler in advance, and storage, directly getting scrambler from correspondence position during descrambling gets final product, another kind method is to adopt the scrambler computing module to calculate scrambler in real time separately, scrambler sequence can be divided into several sections parallel computations, the memory space of Xu Yaoing is very little like this, can obtain the scrambler of interval skip position again simultaneously.
In step 314, reading previous sub-frame data from described quick re-transmission merging memory cell and it is being deciphered.The sub-RAM that the data of this feasible sub-RAM that reads and solution physical resource coupling write is same sub-RAM certainly not, namely can not produce conflict.
The above has carried out further detailed description to purpose of the present invention, technical scheme and beneficial effect; institute is understood that; the above is not in order to limit the present invention; within the spirit and principles in the present invention all; any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. a terminal processes device is characterized in that, described terminal processes device is buffer memory demodulation soft bit result afterwards not, and described terminal processes device comprises:
The channel equalization module is separated physical resource mapping, multiple-input and multiple-output detection, demodulation and descrambling to input signal;
Re-transmission merges memory cell fast, is used for the soft bit result of the descending quick re-transmission of storage, and wherein said quick re-transmission merges the corresponding corresponding process number of transmission mode of memory cell basis and is divided into a plurality of sub-memory cell;
Control module, separate the physical resource coupling, and will separate data that current sub-frame data that physical resource coupling obtains and described quick re-transmission merge corresponding process number in the memory cell and merge or write direct to described quick re-transmission and merge memory cell, and separate physical resource and shine upon, go into soon soon go out detection, demodulation, descrambling according to separating the described channel equalization module of data sequential control that the physical resource coupling obtains; And
The channel decoding module merges from described quick re-transmission and to read previous sub-frame data the memory cell and it is deciphered.
2. terminal processes device as claimed in claim 1 is characterized in that, described terminal processes device is applied to Long Term Evolution (LTE) standard.
3. terminal processes device as claimed in claim 2 is characterized in that, when described transmission mode was Frequency Division Duplexing (FDD), described quick re-transmission merging memory cell was divided into 8 sub-memory cell corresponding to 8 processes.
4. terminal processes device as claimed in claim 2 is characterized in that, when described transmission mode was time division duplex, described quick re-transmission merged memory cell and is divided into 168 sub-memory cell, corresponding to 4,6, and the least common multiple of 7,8 processes.
5. terminal processes device as claimed in claim 2, it is characterized in that, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into 56 sub-memory cell, and on this basis, increase by 4 sub-memory cell again, the size of each sub-memory cell is that described quick re-transmission merges 1/56 of memory cell.
6. terminal processes device as claimed in claim 2, it is characterized in that, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into first group of sub-memory cell and second group of sub-memory cell, described first group of sub-memory cell comprises that 21 sizes are 1/24 the sub-memory cell that described quick re-transmission merges memory cell, and described second group of sub-memory cell comprises that 7 sizes are 1/56 the sub-memory cell that described quick re-transmission merges memory cell.
7. terminal processes device as claimed in claim 1, it is characterized in that, described control module comprises separates physical channel capacity matching module, and the data that described channel equalization module is handled according to described solution physical channel capacity matching module are separated the physical resource mapping in proper order, gone into soon soon go out detection, demodulation, descrambling.
8. terminal processes device as claimed in claim 1, it is characterized in that, described terminal processes device also comprises the scrambler memory cell, the scrambler that described scrambler cell stores is calculated in advance, described channel equalization module directly read described scrambler to be used for described descrambling when physical channel capacity coupling has repetition.
9. terminal processes device as claimed in claim 8 is characterized in that, described scrambler is hard bit.
10. terminal processes device as claimed in claim 1 is characterized in that, described control device also comprises the scrambler computing module, is used for when physical channel capacity coupling has repetition scrambler sequence being divided into several sections and calculates in real time concurrently.
11. terminal processes device as claimed in claim 1 is characterized in that, described terminal processes device also comprises a buffer memory, is used for the rate-matched between described channel equalization module and the described solution physical channel capacity matching module.
12. a terminal processing method is characterized in that, comprising:
Provide one to retransmit the merging memory cell fast, be used for the soft bit result of the descending quick re-transmission of storage;
According to the corresponding process number of corresponding transmission mode, described quick re-transmission is merged memory cell be divided into a plurality of sub-memory cell;
The soft bit result that directly demodulation is obtained after the data that demodulation receives is separated the physical resource mapping and the soft bit result after the described demodulation of buffer memory not;
Solution physical resource coupling;
Merge the data merging in the sub-memory cell of corresponding same process in the memory cell number or write direct to described sub-memory cell separating current sub-frame data that the physical resource coupling obtains and described quick re-transmission;
The described solution physical resource mapping of data sequential control, multiple-input and multiple-output detection, demodulation, descrambling according to described solution physical resource coupling; And
Merging memory cell from described quick re-transmission reads previous sub-frame data and it is deciphered.
13. method as claimed in claim 12 is characterized in that, described method is applied to Long Term Evolution (LTE) standard.
14. method as claimed in claim 13 is characterized in that, when described transmission mode is Frequency Division Duplexing (FDD), described quick re-transmission is merged memory cell be divided into 8 sub-memory cell corresponding to 8 processes.
15. method as claimed in claim 13 is characterized in that, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into 168 sub-memory cell, described 168 sub-memory cell are corresponding to 4,6, the least common multiple of 7,8 processes.
16. method as claimed in claim 13, it is characterized in that, when described transmission mode is time division duplex, 1 described quick re-transmission is merged memory cell be divided into 56 sub-memory cell, and on this basis, increase by 4 sub-memory cell that merge 1/56 size of memory cell for original described quick re-transmission again.
17. method as claimed in claim 13, it is characterized in that, when described transmission mode is time division duplex, described quick re-transmission is merged memory cell be divided into first group of sub-memory cell and second group of sub-memory cell, described first group of sub-memory cell comprises that 21 sizes are 1/24 the sub-memory cell that described quick re-transmission merges memory cell, and described second group of sub-memory cell comprises that 7 sizes are 1/56 the sub-memory cell that described quick re-transmission merges memory cell.
18. method as claimed in claim 12 is characterized in that, described method also comprises the scrambler that storage is calculated in advance, directly reads described scrambler to be used for descrambling when physical channel capacity coupling has repetition.
19. method as claimed in claim 18 is characterized in that, described scrambler is hard bit.
20. method as claimed in claim 12 is characterized in that, described method also comprises, when physical channel capacity coupling has repetition, scrambler sequence is divided into several sections calculates in real time concurrently.
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| CN113225161A (en) * | 2021-04-14 | 2021-08-06 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | 5G terminal PDCCH MIMO detection accelerator and design method |
| CN113452425A (en) * | 2020-03-24 | 2021-09-28 | 大唐移动通信设备有限公司 | Data processing method and device |
| WO2022061792A1 (en) * | 2020-09-27 | 2022-03-31 | Qualcomm Incorporated | Storage-free harq process |
| CN118019119A (en) * | 2024-04-09 | 2024-05-10 | 南京创芯慧联技术有限公司 | Communication data processing device and method compatible with LTE standard and NR standard |
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