CN103248359A - Phase lock return circuit system - Google Patents
Phase lock return circuit system Download PDFInfo
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- CN103248359A CN103248359A CN2012100247202A CN201210024720A CN103248359A CN 103248359 A CN103248359 A CN 103248359A CN 2012100247202 A CN2012100247202 A CN 2012100247202A CN 201210024720 A CN201210024720 A CN 201210024720A CN 103248359 A CN103248359 A CN 103248359A
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Abstract
The invention relates to a phase lock return circuit system which comprises a charge pump, a voltage-controlled oscillator and a bias voltage convertor, wherein the charge pump outputs a control voltage based on a phase frequency detection signal, and produces an output current according to a bias voltage signal; the voltage-controlled oscillator produces an output signal according to the control voltage; and the bias voltage convertor is coupled between the voltage-controlled oscillator and the charge pump, and is used for producing the bias voltage signal according to the control voltage.
Description
Technical field
The invention relates to a kind of phase locked loop system.
Background technology
Phase locked loop system is widely used in simulation and digital circuit.These systems typically comprise a phase-frequency detector, a charge pump and a voltage controlled oscillator (voltage-controlled oscillator, VCO).VCO produces an output signal of phase locked loop system, and this output signal frequency trend also finally is locked in a target frequency, and this target frequency obtains based on a reference signal of input phase frequency detector.When phase locked loop system approached coupling, output signal frequency or phase place may produce shake.Minimizing or reducing uncontrolled shake is a significant design subject under discussion in the phase locked loop system.
Summary of the invention
The invention relates to a kind of phase locked loop system, can improve the unit gain frequency consistency.
According to a first aspect of the invention, propose a kind of phase locked loop system, comprise a charge pump, a voltage controlled oscillator and a bias voltage transducer.Charge pump is exported a control voltage based on a phase frequency detection signal, and produces an output current according to a bias voltage signal.Voltage controlled oscillator produces an output signal according to control voltage.The bias voltage transducer is coupled between voltage controlled oscillator and the charge pump, in order to produce bias voltage signal according to control voltage.
According to a second aspect of the invention, propose a kind of phase locked loop system, comprise a charge pump, a voltage controlled oscillator and a bias voltage transducer.Charge pump is exported a control voltage based on a phase frequency detection signal, and produces an output current according to a bias voltage signal.Voltage controlled oscillator produces an output signal according to control voltage.The bias voltage transducer is coupled between voltage controlled oscillator and the charge pump, and it comprises that a first transistor and an electric current change the voltage block.The first transistor is controlled voltage bias to produce and the proportional electric current of control voltage.Electric current changes voltage block received current, and according to electric current output bias signal.
For there is better understanding above-mentioned and other aspect of the present invention, an embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the calcspar according to the phase locked loop system of an enforcement example.
Fig. 2 A illustrates the circuit diagram according to the bias voltage transducer of an enforcement example.
Fig. 2 B illustrates the circuit diagram of implementing the bias voltage transducer of example according to another.
Fig. 3 illustrates the circuit diagram according to the charge pump of an enforcement example.
Fig. 4 illustrates according to one and implements the gain frequency of example and the schematic diagram in phase place limit.
[main element label declaration]
100: phase locked loop system 110: phase-frequency detector
120: 122: the first differential bias voltage current sources of charge pump
124: the second differential bias voltage current sources of active load in 123: the first
Initiatively load 130 in 125: the second: voltage controlled oscillator
140,140 ': bias voltage transducer 142: electric current changes the voltage block
144: current source block 150: filter
160: frequency eliminator
Embodiment
(phase-locked loop, PLL) system can improve unit gain frequency consistency (consistency) under different multiplier N values, so scope that can extension frequency multiplication and division computing in phase-locked loop proposed by the invention.
The present invention proposes a kind of phase locked loop system, comprises a charge pump, a voltage controlled oscillator and a bias voltage transducer.Charge pump is exported a control voltage based on a phase frequency detection signal, and produces an output current according to a bias voltage signal.Voltage controlled oscillator produces an output signal according to control voltage.The bias voltage transducer is coupled between voltage controlled oscillator and the charge pump, in order to produce bias voltage signal according to control voltage.
Please refer to Fig. 1, it illustrates the calcspar according to the phase locked loop system of an enforcement example.Phase locked loop system 100 comprises a phase-frequency detector (phase frequency detector, PFD) 110, one charge pump (charge pump), 120, one voltage controlled oscillator (voltage-controlledoscillator, VCO) 130, one bias voltage transducer (bias converter), 140, one filter 150 and a frequency eliminator (divider) 160.Wherein, filter 150 is coupled between charge pump 120 and the voltage controlled oscillator 130; Frequency eliminator 160 is coupled between voltage controlled oscillator 130 and the phase-frequency detector 110.
Phase locked loop system 100 can produce an output signal CKVCO, the frequency trend of this output signal CKVCO also finally is locked in a target frequency, this target frequency is based on a reference signal CKREF of input phase frequency detector 110 and obtain, for example the N for the frequency of reference signal CKREF doubly gets, as equation (1) institute formula.
F(CKVCO)＝N×F(CKREF)eq.(1)
Phase-frequency detector 110 receives reference signal CKREF and a feedback signal CKFB, and the frequency of comparison reference signal CKREF and feedback signal CKFB is to produce a phase frequency detection signal UP/DN to charge pump 120.Wherein feedback signal CKFB is for example produced output signal CKVCO by frequency eliminator 160 divided by the N frequency multiplication.Phase-frequency detector 110 can detect the difference between output signal frequency CKVCO and target frequency in fact.
VCNTL∝I
P eq.(2)
Voltage controlled oscillator 130 produces output signal CKVCO according to control voltage VCNTL, and the frequency of output signal CKVCO is proportional with control voltage VCNTL, and as equation (3) institute formula, wherein K is constant.
F(CKVCO)＝K×VCNTL eq.(3)
F(CKVCO)＝N×F(CKREF)＝K×VCNTL∝I
P eq.(4)
Now lift filter 150 and have a series connection capacitor C
S, series connection resistance R and a capacitor C in parallel
PFor example explains, and the phase locked loop system 100 in the supposition present embodiment is phase-locked loops, three rank.Hold, can obtain unit gain frequency ω
U, shown in equation (5).
Observing equation (5) can learn, because present embodiment is with output current I
PBe set at the multiplier N value of frequency eliminator 160 proportionally, can make unit gain frequency ω
UBe essentially and immobilize.In other words, even the N value changes unit gain frequency ω
UStill can be maintained definite value, further expand the scope of frequency multiplication and division computing or output frequency, and make phase locked loop system 100 keep good stable.
Preferably, bias voltage transducer 140 can be configured to according to control voltage VCNTL and produces one first electric current, first electric current and being arranged to control voltage VCNTL proportional wherein, bias voltage transducer 140 and according to the first electric current output bias signal BN.Please refer to Fig. 2 A, it illustrates the circuit diagram according to the bias voltage transducer of an enforcement example.Bias voltage transducer 140 comprises that a first transistor M1 and an electric current change voltage block 142.The first transistor M1 is controlled voltage VCNTL and is biased in one or three polar body districts to produce proportional one second electric current I with control voltage VCNTL
2Electric current changes voltage block 142 and receives second electric current I
2, and according to second electric current I
2Output bias signal BN.In other words, in this embodiment, second electric current I
2Be as first electric current I
1An electric current composition.
Fig. 2 A also shows that electric current changes the embodiment of a thin portion framework of voltage block 142.Shown in Fig. 2 A, electric current changes voltage block 142 can comprise a transistor seconds M2 and an amplifier 143.Transistor seconds M2 has one first end and is coupled to the first transistor M1 and receives second electric current I
2With as first electric current I
1The electric current composition.Amplifier 143 has first end that a first input end is coupled to transistor seconds M2, and one second input receives an input voltage VD, and an output is coupled to the control end of transistor seconds M2, and according to first electric current I
1Output bias signal BN.Bias voltage transducer 140 shown in Fig. 2 A is applicable to the fixed-frequency of reference signal CKREF, and corresponding to different N values so that the frequency of output signal CKVCO trends towards different target frequencies.
Please refer to Fig. 2 B, it illustrates the circuit diagram of implementing the bias voltage transducer of example according to another.Shown in Fig. 2 B, bias voltage transducer 140 can also comprise a current source block 144, is controlled by one and selects signal CSSEL, to copy second electric current I
2And produce one the 3rd electric current I
3As first electric current I
1Another electric current composition, and provide the 3rd electric current I
3To electric current commentaries on classics voltage block 142, so that electric current changes voltage block 142 according to first electric current I
1(be second electric current I this moment
2With the 3rd electric current I
3And) come output bias signal BN.
More specifically, current source block 144 can comprise as shown in Figure 2 by the first transistor M1 respectively with a plurality of transistor M
N～M
N+mBe in parallel and couple a plurality of current mirrors of forming.These a little current mirrors are controlled by selects signal CSSEL and conducting or close, and in order to copy second electric current I
2It is one the 3rd electric current I
3, and the 3rd electric current I is provided
3 Change voltage block 142 with as first electric current I to electric current
1In second electric current I
2Another outer electric current composition.
Select signal CSSEL to indicate the 3rd electric current I in fact
3With second electric current I
2Between one copy multiplying power, this copies multiplying power and for example is inversely proportional to the frequency of reference signal CKREF.For instance, when target frequency is determined, corresponding different reference signal CKREF then, the change of N value, output current I
PAlso will be along with the N value changes.And output current I
PSize be relevant to the conducting number of these current mirrors.In other words, the conducting number of these current mirrors is that frequency with reference signal CKREF is inversely proportional to.When the frequency of reference signal CKREF is bigger, the N value must be less, output current I
PAlso less, select signal CSSEL to control the current mirror decreased number of conducting; Less when the frequency of reference signal CKREF, the N value must be bigger, output current I
PAlso bigger, select the current mirror number of signal CSSEL control conducting to increase.Bias voltage transducer 140 ' shown in Fig. 2 B is applicable to that target frequency fixes, and corresponding to the frequency of different reference signal CKREF, adjusts N value/output current I
PSo that the frequency of output signal CKVCO trends towards target frequency.In other words, by making the output current I of charge pump 120
PBe inversely proportional to the frequency of input signal CKREF, can further make phase locked loop system 100 incoming frequency on a large scale in, keep good stable.
Once stated as preceding, bias voltage signal BN is output current mirroring circuit to the charge pump 120 in fact to copy first electric current I
1Be output current I
PPlease refer to Fig. 3, it illustrates the circuit diagram according to the charge pump of an enforcement example.Charge pump 120 comprises one first differential bias voltage current source 122 and one second differential bias voltage current source 124.The first differential bias voltage current source 122 is coupled to one first signal component DN and the bias voltage signal BN of phase frequency detection signal, and produces a gate-control signal.The second differential bias voltage current source 124 is coupled to a secondary signal composition UP, gate-control signal and the bias voltage signal BN of phase frequency detection signal, and produces control voltage VCNTL and output current I
P
The first differential bias voltage current source 122 can comprise that one first bias transistor B1, one first differential input are to (D
11, D
12) and one first initiatively load 123.The first bias transistor B1 has a grid and is coupled to bias voltage signal BN.The first differential input is to (D
11, D
12) be coupled to the first bias transistor B1, and receive the first signal component DN and its inversion signal DNB.The first active load 123 is coupled to the first differential input to (D
11, D
12), and produce gate-control signal.The second differential bias voltage current source 124 can comprise that one second bias transistor B2, one second differential input are to (D
21, D
22) and one second initiatively load 125.The second bias transistor B2 has a grid and is coupled to bias voltage signal BN.The second differential input is to (D
21, D
22) be coupled to the second bias transistor B2, and receive secondary signal composition UP and its inversion signal UPB.The second active load 125 is coupled to gate-control signal, and produces control voltage VCNTL and output current I
P
Comprehensively above-mentioned, because first electric current I
1VCNTL is proportional with control voltage, and output current I
PBy first electric current I
1Copy obtaining, so output current I
PVCNTL is proportional with control voltage.In addition, the frequency of output signal CKVCO is proportional with control voltage VCNTL, so output current I
PProportional with the frequency of output signal CKVCO, shown in the equation of carrying as described above (4).Please refer to Fig. 4, it illustrates according to one and implements the gain frequency of example and the schematic diagram in phase place limit.In phase locked loop system, unit gain frequency ω
UCan be required to correspond to maximum phase limit (phase margin), shown in curve C 10.Yet traditional phase locked loop system is under the situation that the N value changes, and curve can move and obtain as curve C 20, and makes unit gain frequency ω
UCan't correspond to the maximum phase limit.But bias voltage transducer 140 control output current I in the present embodiment,
PProportional with multiplier N value.Thus, when the N value changes, the output current I of charge pump 120
PCan change and compensate the amount that N changes, make unit gain frequency ω
UCan remain unchanged, correspond to the maximum phase limit and shown in curve C 10, be maintained at.As a result, the scope that phase locked loop system 100 medium frequency multiplication and division are handled, or the frequency range of output signal CKVCO can enlarge.
The disclosed phase locked loop system of the above embodiment of the present invention, by making the output current of charge pump be directly proportional with the N value, so the maximum phase limit can be kept and correspond to unit gain frequency, the unit gain frequency consistency of improvement under different multiplier N values, so can extension frequency multiplication and division computing or the scope of output frequency.In addition, by making the output current of charge pump and the frequency of input signal be inversely proportional to, can further make phase locked loop system incoming frequency on a large scale in, keep good stable.
In sum, though the present invention discloses as above with a plurality of embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (22)
1. phase locked loop system comprises:
One charge pump is exported a control voltage based on a phase frequency detection signal, and produces an output current according to a bias voltage signal;
One voltage controlled oscillator produces an output signal according to this control voltage; And
One bias voltage transducer is coupled between this voltage controlled oscillator and this charge pump, in order to produce this bias voltage signal according to this control voltage.
2. phase locked loop system according to claim 1, wherein this output current is to become a ratio with this control voltage.
3. phase locked loop system according to claim 1, wherein to produce one first electric current, this first electric current is to become a ratio with this control voltage to this bias voltage transducer according to this control voltage, this bias voltage transducer is also exported this bias voltage signal according to this first electric current.
4. phase locked loop system according to claim 3, wherein this bias voltage transducer comprises:
One the first transistor, by this control voltage bias to produce one second electric current as an electric current composition of this first electric current; And
One electric current changes the voltage block, receives this second electric current, and exports this bias voltage signal according to this second electric current.
5. phase locked loop system according to claim 4, wherein this first transistor by this control voltage bias in one or three polar body districts, to produce and proportional this second electric current of this control voltage.
6. phase locked loop system according to claim 4, wherein this electric current changes voltage block and comprises:
One transistor seconds has one first end and is coupled to this first transistor; And
One amplifier has first end that a first input end is coupled to this transistor seconds, and one second input receives an input voltage, and an output is coupled to the control end of this transistor seconds and exports this bias voltage signal.
7. phase locked loop system according to claim 4, wherein this bias voltage transducer also comprises:
One current source block, be controlled by one and select signal, produce one the 3rd electric current as another electric current composition of this first electric current to copy this second electric current, and provide the 3rd electric current to this electric current to change the voltage block, so that changeing the voltage block, this electric current exports this bias voltage signal according to this second electric current and the 3rd electric current.
8. phase locked loop system according to claim 7, wherein this current source block comprises a plurality of current mirrors, the conducting number of these a plurality of current mirrors is to be controlled by this selection signal.
9. phase locked loop system according to claim 7, also comprise a phase-frequency detector, receive reference signal and feedback signal, and produce this phase frequency detection signal to this charge pump, wherein this feedback signal is to produce according to this output signal, and this selection signal is the frequency that depends on this reference signal.
10. phase locked loop system according to claim 9, wherein this selection signal indicates one between the 3rd electric current and this second electric current to copy multiplying power, and this copies multiplying power is that frequency with this reference signal is inversely proportional to.
11. phase locked loop system according to claim 1 also comprises:
One phase-frequency detector receives a reference signal and a feedback signal, and produces this phase frequency detection signal to this charge pump, and wherein this feedback signal is to produce according to this output signal.
12. phase locked loop system according to claim 11 also comprises:
One frequency eliminator is coupled between this voltage controlled oscillator and this phase-frequency detector.
13. phase locked loop system according to claim 1 also comprises:
One filter is coupled between this charge pump and this voltage controlled oscillator.
14. phase locked loop system according to claim 1, wherein this bias voltage transducer comprises:
One the first transistor has a control end and is coupled to this control voltage;
One transistor seconds has one first end that one first end is coupled to this first transistor; And
One amplifier has first end that a first input end is coupled to this transistor seconds, and one second input couples an input voltage, and an output is coupled to a control end of this transistor seconds and exports this bias voltage signal.
15. phase locked loop system according to claim 14, wherein this bias voltage transducer also comprises:
A plurality of current mirrors, being in parallel with this first transistor couples, and is controlled by one and selects signal and conducting or close.
16. phase locked loop system according to claim 15, also comprise a phase-frequency detector, receive reference signal and feedback signal, and produce this phase frequency detection signal to this charge pump, wherein this feedback signal is to produce according to this output signal, this selection signal is the frequency that depends on this reference signal, and the conducting number of those current mirrors of this bias voltage transducer is that frequency with this reference signal is inversely proportional to.
17. phase locked loop system according to claim 1, wherein this charge pump comprises:
One first differential bias voltage current source is coupled to one first signal component and this bias voltage signal of this phase frequency detection signal, and produces a gate-control signal; And
One second differential bias voltage current source is coupled to a secondary signal composition, this gate-control signal and this bias voltage signal of this phase frequency detection signal, and produces this control voltage and this output current.
18. phase locked loop system according to claim 17, wherein this first differential bias voltage current source comprises:
One first bias transistor has a grid and is coupled to this bias voltage signal;
One first differential input is right, is coupled to this first bias transistor, and receives this first signal component and its inversion signal; And
One first initiatively load, it is right to be coupled to this first differential input, and produces this gate-control signal.
19. phase locked loop system according to claim 17, wherein this second differential bias voltage current source comprises:
One second bias transistor has a grid and is coupled to this bias voltage signal;
One second differential input is right, is coupled to this second bias transistor, and receives this secondary signal composition and its inversion signal; And
One second initiatively load is coupled to this gate-control signal, and produces this control voltage and this output current.
20. a phase locked loop system comprises:
One charge pump is exported a control voltage based on a phase frequency detection signal, and produces an output current according to a bias voltage signal;
One voltage controlled oscillator produces an output signal according to this control voltage; And
One bias voltage transducer is coupled between this voltage controlled oscillator and this charge pump, comprising:
One the first transistor is controlled the proportional electric current of voltage by this control voltage bias to produce with this; And
One electric current changes the voltage block, receives this electric current, and exports this bias voltage signal according to this electric current.
21. phase locked loop system according to claim 20, wherein this bias voltage transducer also comprises:
One current source block is controlled by one and selects signal, produces another electric current to copy this electric current, and provides this another electric current to this electric current to change the voltage block, exports this bias voltage signal so that this electric current changes the voltage block according to this electric current and this another electric current.
22. phase locked loop system according to claim 21 also comprises:
One phase-frequency detector receives a reference signal and a feedback signal, and produces a phase frequency detection signal to this charge pump;
Wherein, this current source block comprises a plurality of current mirrors, and the conducting number of these a plurality of current mirrors is that the frequency with this reference signal is inversely proportional to.
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|---|---|---|---|
| CN2012100247202A CN103248359A (en) | 2012-02-06 | 2012-02-06 | Phase lock return circuit system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100247202A CN103248359A (en) | 2012-02-06 | 2012-02-06 | Phase lock return circuit system |
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| CN103248359A true CN103248359A (en) | 2013-08-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734634A (en) * | 2013-12-24 | 2015-06-24 | 瑞昱半导体股份有限公司 | Controllable oscillator and method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020101292A1 (en) * | 2001-01-26 | 2002-08-01 | True Circuits, Inc. | Self-biasing phase-locked loop system |
| CN1613185A (en) * | 2002-05-22 | 2005-05-04 | 松下电器产业株式会社 | Low-pass filter,feedback system and semiconductor integrated circuit |
-
2012
- 2012-02-06 CN CN2012100247202A patent/CN103248359A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020101292A1 (en) * | 2001-01-26 | 2002-08-01 | True Circuits, Inc. | Self-biasing phase-locked loop system |
| CN1613185A (en) * | 2002-05-22 | 2005-05-04 | 松下电器产业株式会社 | Low-pass filter,feedback system and semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734634A (en) * | 2013-12-24 | 2015-06-24 | 瑞昱半导体股份有限公司 | Controllable oscillator and method thereof |
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Application publication date: 20130814 |