CN103248342B - A kind of pulse delay circuit and scan method - Google Patents
A kind of pulse delay circuit and scan method Download PDFInfo
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- CN103248342B CN103248342B CN201310181156.XA CN201310181156A CN103248342B CN 103248342 B CN103248342 B CN 103248342B CN 201310181156 A CN201310181156 A CN 201310181156A CN 103248342 B CN103248342 B CN 103248342B
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Abstract
Pulse delay circuit of the present invention and scan method, utilize FPGA to the time delay controlling trigger impulse and export between pulse, make pulse delay present dynamic change, solving existing pulse signal generator cannot to the problem of moving target radar echo signal simulation.
Description
Technical field
The present invention relates to Radar Technology field, particularly a kind of pulse delay circuit, also relate to a kind of pulse daley scan method.
Background technology
Along with the development of Radar Technology, radar is more and more extensive in the application of every profession and trade, the target of monitoring is complicated and changeable, in order to better meet radar test growth requirement, need the echo-signal of test source energy accurate simulation realistic objective, so not only requirement can be simulated the echo-signal of static object, also can simulate the echo-signal of moving target.Because the distance between moving target and radar is in continuous change, corresponding reflected signal and the time delay between transmitting are also in continuous change, in order to the whole motion process of simulated target, require that the time delay between test source output pulse signal and start pulse signal can constantly change, there is the function of delayed sweep.
Fig. 1 is the circuit diagram of existing pulse delay unit, delayer adopts 3 series connection counters to realize, at the rising edge trigger of trigger impulse, use the rising edge counting of clock, counter 1 is adopted to produce lock-out pulse, the length of counter 2 computation delay, counter 3 calculates the pulsewidth of the output pulse that will produce, and resets counter 2 sum counter 3 at the end of counting.When exporting series of pulse signals, the output pulsion phase of this pulser is constant for the delay time of trigger impulse.
The pulse signal that prior art generates is fixing relative to the delay time of trigger impulse, during for general radar signal simulation, can only simulate static target relative to the distance of radar, can not reflect the kinetic characteristic of target, the emulation for air route or other orbiting motion target cannot realize.
Summary of the invention
Pulse delay circuit of the present invention and scan method, utilize FPGA to the time delay controlling trigger impulse and export between pulse, make pulse delay present dynamic change, solving existing pulse signal generator cannot to the problem of moving target radar echo signal simulation.
Technical scheme of the present invention is achieved in that
A kind of pulse delay circuit, comprising: delay duration accumulator, pulse delay accumulator, pulse width counter, the first comparator and the second comparator;
The input of delay duration accumulator receives initial delay value, time delay step value, trigger impulse and counting clock, after the pulse-triggered that is triggered, time delay step value carries out being added or subtracting each other with the currency of delay duration accumulator by delay duration accumulator, obtain the delay duration data of this subpulse and trigger impulse, by delay duration data loading to the first comparator be connected with pulse delay accumulator output;
Pulse delay accumulator is under the effect of trigger impulse, the initial time counted using the time point of current triggering as delay accumulation, at the rising edge of each counting clock, pulse delay accumulator adds up a clock cycle, when the output of pulse delay accumulator equals the delay duration being loaded into the first comparator, pulse delay accumulator overflows, and overflows afterpulse delay accumulation device and stops accumulated counts, until the coming of next trigger impulse, the time delay exporting pulse reaches setting duration;
First comparator is when pulse delay accumulator overflows, produce a pulse signal, trigger pulse width counter starts counting, one-accumulate is carried out at each counting clock, until the width exporting pulse reaches the width of setting, export the pulse signal that time delay is variable, pulsewidth can be established, and when pulse delay accumulator overflows, the first comparator puts maximum to pulse delay accumulator;
Second comparator, the delay duration data that reception delay duration accumulator exports, compared with termination delay value, when delay duration data equal to stop delay value, delay duration accumulator overflows, and the second comparator puts initial value to delay duration accumulator.
Alternatively, described pulse delay circuit is integrated in fpga chip.
Alternatively, described fpga chip adopts the EP3C25Q240C8 chip of altera corp.
Alternatively, described FPGA internal processes uses VerilogHDL language compilation.
Alternatively, described delay duration accumulator, pulse delay accumulator and pulse width counter all adopt 32, clock 100MHz.
Based on above-mentioned pulse delay circuit, the present invention also provides a kind of pulse daley scan method, comprises the following steps:
After the pulse-triggered that is triggered, by delay duration accumulator, time delay step value is carried out being added or subtracting each other with the currency of delay duration accumulator, obtain the delay duration data of this subpulse and trigger impulse, by delay duration data loading in the first comparator be connected with pulse delay accumulator output, comparison value when overflowing as pulse delay accumulator;
Simultaneously, under the effect of trigger impulse, the initial time that pulse delay accumulator counts using the time point of current triggering as delay accumulation, at the rising edge of each counting clock, pulse delay accumulator adds up a clock cycle, when the output of pulse delay accumulator equals the delay duration being loaded into the first comparator, pulse delay accumulator overflows, overflow afterpulse delay accumulation device and stop accumulated counts, until the coming of next trigger impulse, the time delay exporting pulse reaches setting duration;
When pulse delay accumulator overflows, first comparator produces a pulse signal, trigger pulse width counter starts counting, one-accumulate is carried out at each counting clock, until the width exporting pulse reaches the width of setting, export the pulse signal that time delay is variable, pulsewidth can be established, and when pulse delay accumulator overflows, the first comparator puts maximum to pulse delay accumulator;
The delay duration Data import exported by delay duration accumulator is to the second comparator, and compared with termination delay value, when delay duration data equal to stop delay value, delay duration accumulator overflows, and the second comparator puts initial value to delay duration accumulator.
Alternatively, when described time delay step value is set to 0ns, export constant time lag.
The invention has the beneficial effects as follows:
(1) time delay of different pulse is continuous variable, and delay precision can reach 10ns;
(2) emulation for air route or other orbiting motion target can be realized, the kinetic characteristic of reflection target.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the circuit diagram of existing pulse delay unit;
Fig. 2 is the circuit block diagram of pulse delay circuit of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The pulse signal that prior art generates is fixing relative to the delay time of trigger impulse, during for general radar signal simulation, can only simulate static target relative to the distance of radar, can not reflect the kinetic characteristic of target, the emulation for air route or other orbiting motion target cannot realize.
Pulse delay circuit of the present invention can produce the delay time pulse signal variable relative to trigger impulse, as shown in Figure 2, comprising: delay duration accumulator 10, pulse delay accumulator 20, pulse width counter 30, first comparator 40 and the second comparator 50.
The input of delay duration accumulator 10 receives initial delay value, time delay step value, trigger impulse and counting clock, and during pulse scanning, delay duration accumulator 10 carries out cycle accumulor Counts under the driving of trigger impulse.After by certain trigger pulse triggers, time delay step value carries out being added or subtracting each other with the currency of delay duration accumulator by delay duration accumulator 10, obtain the delay duration data of this subpulse and trigger impulse, by delay duration data loading in the first comparator 40 be connected with pulse delay accumulator 20 output, comparison value when overflowing as pulse delay accumulator 20.Simultaneously, under the effect of trigger impulse, the initial time that pulse delay accumulator 20 counts using the time point of current triggering as delay accumulation, at the rising edge of each counting clock, a pulse delay accumulator 20 cumulative clock cycle, when the output of pulse delay accumulator 20 equals the delay duration of this subpulse, pulse delay accumulator 20 overflows, overflow afterpulse delay accumulation device 20 and stop accumulated counts, until the coming of next trigger impulse, the time delay now exporting pulse has reached setting duration.When pulse delay accumulator 20 overflows, first comparator 40 can produce a pulse signal, under the triggering of this pulse signal, pulse width counter 30 starts counting, carry out one-accumulate at each counting clock, until the width exporting pulse reaches the width of setting, export the pulse signal that time delay is variable, pulsewidth can be established, and when pulse delay accumulator 20 overflows, the first comparator 40 puts maximum to pulse delay accumulator 20.The delay duration data that delay duration accumulator 10 exports also are loaded into the second comparator 50, compared with termination delay value, when delay duration data equal to stop delay value, delay duration accumulator 10 overflows, and the second comparator 50 puts initial value to delay duration accumulator 10.
Pulse delay circuit of the present invention utilizes fpga chip to generate pulse delay signals, and fpga chip adopts the EP3C25Q240C8 chip of altera corp, and FPGA internal processes uses VerilogHDL language compilation.What start pulse signal was simulated is transmitting of radar, what pulse output signals was simulated is the echo-signal that target reflects, there is controlled time delay, the change of time delay dynamic between these two pulse signals, reflect the dynamic characteristic of the spacing of measured target and radar.
According to an embodiment of pulse delay circuit of the present invention, delay duration accumulator, pulse delay accumulator and pulse width counter all adopt 32, clock 100MHz, clock cycle 10ns, and can obtain reference time delay is 0ns ~ 42s.During work, time delay step value is sent in delay duration accumulator 10, and most I is set to 0ns, and now equivalent do not have time delay.When time delay step value is set to 0ns, export constant time lag.
Based on pulse delay circuit of the present invention, the invention allows for a kind of pulse daley scan method, comprise the following steps: after the pulse-triggered that is triggered, by delay duration accumulator, time delay step value is carried out being added or subtracting each other with the currency of delay duration accumulator, obtain the delay duration data of this subpulse and trigger impulse, by delay duration data loading in the first comparator be connected with pulse delay accumulator output, comparison value when overflowing as pulse delay accumulator; Simultaneously, under the effect of trigger impulse, the initial time that pulse delay accumulator counts using the time point of current triggering as delay accumulation, at the rising edge of each counting clock, pulse delay accumulator adds up a clock cycle, when the output of pulse delay accumulator equals the delay duration of this subpulse, pulse delay accumulator overflows, overflow afterpulse delay accumulation device and stop accumulated counts, until the coming of next trigger impulse, the time delay now exporting pulse has reached setting duration; When pulse delay accumulator overflows, first comparator produces a pulse signal, under the triggering of this pulse signal, pulse width counter starts counting, carry out one-accumulate at each counting clock, until the width exporting pulse reaches the width of setting, export the pulse signal that time delay is variable, pulsewidth can be established, and when pulse delay accumulator overflows, the first comparator puts maximum to pulse delay accumulator; The delay duration data that delay duration accumulator exports also are loaded into the second comparator, and compared with termination delay value, when delay duration data equal to stop delay value, delay duration accumulator overflows, and the second comparator puts initial value to delay duration accumulator.
Preferably, when time delay step value is set to 0ns, export constant time lag.
Pulse delay circuit of the present invention and pulse daley scan method, utilize the time delay that fpga chip comes between control synchronization reference pulse signal and pulse output signals, the time delay of different pulse is continuous variable, delay precision can reach 10ns, the emulation for air route or other orbiting motion target can be realized, the kinetic characteristic of reflection target.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a pulse delay circuit, is characterized in that, comprising: delay duration accumulator, pulse delay accumulator, pulse width counter, the first comparator and the second comparator;
The input of delay duration accumulator receives initial delay value, time delay step value, trigger impulse and counting clock, after the pulse-triggered that is triggered, time delay step value carries out being added or subtracting each other with the currency of delay duration accumulator by delay duration accumulator, obtain the delay duration data of this subpulse and trigger impulse, by delay duration data loading to the first comparator be connected with pulse delay accumulator output;
Pulse delay accumulator is under the effect of trigger impulse, the initial time counted using the time point of current triggering as delay accumulation, at the rising edge of each counting clock, pulse delay accumulator adds up a clock cycle, when the output of pulse delay accumulator equals the delay duration being loaded into the first comparator, pulse delay accumulator overflows, and overflows afterpulse delay accumulation device and stops accumulated counts, until the coming of next trigger impulse, the time delay exporting pulse reaches setting duration;
First comparator is when pulse delay accumulator overflows, produce a pulse signal, trigger pulse width counter starts counting, one-accumulate is carried out at each counting clock, until the width exporting pulse reaches the width of setting, export the pulse signal that time delay is variable, pulsewidth can be established, and when pulse delay accumulator overflows, the first comparator puts maximum to pulse delay accumulator;
Second comparator, the delay duration data that reception delay duration accumulator exports, compared with termination delay value, when delay duration data equal to stop delay value, delay duration accumulator overflows, and the second comparator puts initial value to delay duration accumulator.
2. pulse delay circuit as claimed in claim 1, it is characterized in that, described pulse delay circuit is integrated in fpga chip.
3. pulse delay circuit as claimed in claim 2, is characterized in that, described fpga chip adopts the EP3C25Q240C8 chip of altera corp.
4. pulse delay circuit as claimed in claim 3, is characterized in that, described fpga chip internal processes uses VerilogHDL language compilation.
5. pulse delay circuit as claimed in claim 4, it is characterized in that, described delay duration accumulator, pulse delay accumulator and pulse width counter all adopt 32, clock 100MHz.
6., based on a pulse daley scan method for pulse delay circuit according to claim 5, it is characterized in that, comprise the following steps:
After the pulse-triggered that is triggered, by delay duration accumulator, time delay step value is carried out being added or subtracting each other with the currency of delay duration accumulator, obtain the delay duration data of this subpulse and trigger impulse, by delay duration data loading in the first comparator be connected with pulse delay accumulator output, comparison value when overflowing as pulse delay accumulator;
Simultaneously, under the effect of trigger impulse, the initial time that pulse delay accumulator counts using the time point of current triggering as delay accumulation, at the rising edge of each counting clock, pulse delay accumulator adds up a clock cycle, when the output of pulse delay accumulator equals the delay duration being loaded into the first comparator, pulse delay accumulator overflows, overflow afterpulse delay accumulation device and stop accumulated counts, until the coming of next trigger impulse, the time delay exporting pulse reaches setting duration;
When pulse delay accumulator overflows, first comparator produces a pulse signal, trigger pulse width counter starts counting, one-accumulate is carried out at each counting clock, until the width exporting pulse reaches the width of setting, export the pulse signal that time delay is variable, pulsewidth can be established, and when pulse delay accumulator overflows, the first comparator puts maximum to pulse delay accumulator;
The delay duration Data import exported by delay duration accumulator is to the second comparator, and compared with termination delay value, when delay duration data equal to stop delay value, delay duration accumulator overflows, and the second comparator puts initial value to delay duration accumulator.
7. pulse daley scan method as claimed in claim 6, is characterized in that, when described time delay step value is set to 0ns, exports constant time lag.
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| CN104467756A (en) * | 2014-11-12 | 2015-03-25 | 深圳市大族激光科技股份有限公司 | Variable frequency pulse signal generation method and generation device |
| CN105897359B (en) * | 2016-06-12 | 2018-07-31 | 广州杰赛科技股份有限公司 | A kind of leakage of repeater in-band carrier inhibits test method and device |
| KR20180041319A (en) * | 2016-10-14 | 2018-04-24 | 엘에스산전 주식회사 | Apparatus for recognizing pulse signal |
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| US4168502A (en) * | 1978-03-15 | 1979-09-18 | Westinghouse Electric Corp. | Digitally controlled signal simulator |
| CN101056098A (en) * | 2007-04-16 | 2007-10-17 | 北京华欣北仪科技发展有限责任公司 | Broadband ultra high-precision digital impulse phase shift generator |
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| CN102063065A (en) * | 2010-11-26 | 2011-05-18 | 无锡市雷华科技有限公司 | Distance delay control circuit |
| CN102073033A (en) * | 2009-11-25 | 2011-05-25 | 中国科学院电子学研究所 | Method for generating high-precision stepping delay capable of dynamic calibration |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4168502A (en) * | 1978-03-15 | 1979-09-18 | Westinghouse Electric Corp. | Digitally controlled signal simulator |
| CN101056098A (en) * | 2007-04-16 | 2007-10-17 | 北京华欣北仪科技发展有限责任公司 | Broadband ultra high-precision digital impulse phase shift generator |
| CN102025350A (en) * | 2009-09-18 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Pulse attenuation loop and delay measuring device |
| CN102073033A (en) * | 2009-11-25 | 2011-05-25 | 中国科学院电子学研究所 | Method for generating high-precision stepping delay capable of dynamic calibration |
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