CN103247325A - Flash memory with serial I/O interface - Google Patents
Flash memory with serial I/O interface Download PDFInfo
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Abstract
The invention discloses a flash memory with a serial I/O interface, comprising: a bidirectional I/O interface and a memory cell; wherein the bidirectional I/O interface is used for receiving external clock signal and input signal, the input signal is sampled at a rising edge of the external clock signal, to obtain a first path data input result, and the input signal is sampled at a falling edge of the external clock signal, to obtain a second path data input result; the first and the second path data input results are stored in the memory cell; data in the memory cell is output. In the invention, a data transmission data of the flash memory with the serial I/O interface is raised.
Description
Technical field
The present invention relates to circuit field, relate in particular to a kind of serial i/O interface quick flash storage.
Background technology
Serial interface flash memory is a kind of widely used data storage device, but because all instructions such as read-write, address and data all are the serial input and output, message transmission rate becomes the shortcoming of serial interface flash memory more slowly.
In order to improve its transfer rate, existing scheme is mainly improved in raising clock frequency and pin multiplexing.Existing a kind of solution that improves the message transmission rate of serial interface buccal mass flash memory is: adopt circuit for switching between two clocks that rising edge and the negative edge of external clock are sampled, and sampled result exported as internal clock signal, thereby realized doubling the message transmission rate of external clock frequency.In addition, by being combined with technology such as multiplexed port, can also further improve the message transmission rate of serial interface flash memory.
The deficiency of such scheme is that the generation of internal clock signal is restricted to the frequency size of external clock.When half of the time-delay of delay circuit and clock period equates, will can not produce internal clock signal.In addition, the dutycycle of internal clock signal is also inequality under different external clock frequencies, and the dutycycle of the internal clock signal that generates under some situation is too little, will influence the sampling of data.
Summary of the invention
The technical problem to be solved in the present invention is how to improve the message transmission rate of serial i/O interface quick flash storage.
In order to address the above problem, the invention provides a kind of serial i/O interface quick flash storage, comprising:
Two-way I/O interface, storage unit;
Described two-way I/O interface is used for receiving external timing signal and input signal, externally rising edge of clock signal is sampled to described input signal, obtain the first via according to input results, at the negative edge of described external timing signal described input signal is sampled, obtain the second the tunnel according to input results; First, second circuit-switched data input results is preserved in the described storage unit; And export data in the described storage unit.
Further, the data exported in the described storage unit of described two-way I/O interface refer to:
Described two-way I/O interface receives first via data and second circuit-switched data from described storage unit, exports described first via data at the rising edge of described external timing signal, exports described second circuit-switched data at the negative edge of described external timing signal.
Further, described two-way I/O interface also is used for described first, second circuit-switched data input results is carried out synchronously.
Further, described two-way I/O interface is in the rising edge of described external timing signal is preserved described first, second circuit-switched data input results into described storage unit.
Further, described two-way I/O interface comprises:
Input interface and output interface;
Described input interface comprises:
First load module receives described external timing signal and input signal, is used for externally rising edge of clock signal described input signal is sampled, and obtains described first via data input results;
Second load module receives described external timing signal and input signal, is used for externally the negative edge of clock signal described input signal is sampled, and obtains the described second circuit-switched data input results;
The input synchronization module receives described external timing signal and first, second circuit-switched data input results, and being used for externally, described first, second circuit-switched data input results of rising edge of clock signal output arrives described storage unit.
Further, described first load module is first d type flip flop, and the CLK end directly connects described external timing signal, and the D end connects described input signal;
Described second load module comprises second d type flip flop and first phase inverter; The CLK end of described second d type flip flop connects described external timing signal by described first phase inverter, and the D end connects described input signal;
Described input synchronization module comprises 3d flip-flop and four d flip-flop; The described the 3rd CLK end directly connects described external timing signal, and the D end connects the Q end of described first d type flip flop, the described first via data input results of Q end output; The CLK end of described four d flip-flop directly connects described external timing signal, and the D end connects the Q end of described second d type flip flop, the described second circuit-switched data input results of Q end output.
Further, described output interface comprises:
The output synchronization module is used for according to described external timing signal the staggered data of two-way of storage unit output being carried out synchronously;
Select module, be used for selecting one tunnel output according to the two paths of data of described external timing signal after synchronously.
Further, described output synchronization module comprises the 5th d type flip flop, the 6th d type flip flop; The CLK end of described the 5th d type flip flop connects described external timing signal, and the D end connects from the first via data of described storage unit output; The CLK end of described the 6th d type flip flop connects described external timing signal, and the D end connects from second circuit-switched data of described storage unit output;
Described selection module is MUX; Two input ends of described MUX connect the Q end of described the 5th, the 6th d type flip flop respectively, the selecting side connects described external timing signal, when described external timing signal is high level, select the data output of described the 5th d type flip flop Q end, when described external timing signal is low level, select the data output of described the 6th d type flip flop Q end.
Further, in the present embodiment, described two-way I/O interface can also comprise that one switches unit and an IO channel, and described switch unit is used for input interface and output interface one and switches to described IO channel and link to each other.
Further, described switch unit comprises:
First, second triple gate and second phase inverter;
The Enable Pin of described first triple gate receives the I/O control signal, and input end connects described I/O passage, and output terminal connects described input interface;
The Enable Pin of described second triple gate receives the I/O control signal by described second phase inverter, and input end connects described output interface;
When the I/O control signal was high level, first triple gate was high-impedance state, and second triple gate is connected, and the I/O passage links to each other with output interface; When the I/O control signal was low level, second triple gate was high-impedance state, and first triple gate is connected, and the I/O passage links to each other with input interface.
Technical scheme of the present invention is carried out data sampling by rising edge and negative edge at clock under the situation that does not increase clock signal frequency, realized the message transmission rate of twice.Both can improve the message transmission rate of serial interface flash memory, can avoid increasing the frequency of clock signal again.
In addition, by using triple gate and input/output control signal, load module and output module can well be combined, thereby make the transmitted in both directions interface also can realize the message transmission rate of twice, the port definition of flash memory is more flexible.
Description of drawings
Fig. 1 is the schematic block diagram of serial i/O interface quick flash storage of embodiment one;
Fig. 2 is the input interface synoptic diagram of serial i/O interface quick flash storage of embodiment one;
Fig. 3 is the output interface synoptic diagram of serial i/O interface quick flash storage of embodiment one;
Fig. 4 is the I/O interface synoptic diagram of serial i/O interface quick flash storage of embodiment one.
Embodiment
Below in conjunction with drawings and Examples technical scheme of the present invention is described in detail.
Need to prove that if do not conflict, each feature among the embodiment of the invention and the embodiment can mutually combine, all within protection scope of the present invention.In addition, though there is shown logical order in flow process, in some cases, can carry out step shown or that describe with the order that is different from herein.
Embodiment one, and a kind of serial i/O (I/O) interface quick flash storage as shown in Figure 1, comprising:
Two-way I/O interface, storage unit;
Described two-way I/O interface is used for receiving external timing signal SCK and input signal, externally the rising edge of clock signal SCK is sampled to described input signal, obtain the first via according to input results SI_H, negative edge at described external timing signal is sampled to described input signal, obtains the second the tunnel according to input results SI_L; First, second circuit-switched data input results is preserved in the described storage unit; And export data in the described storage unit.
In the present embodiment, respectively input signal is sampled at rising edge and the negative edge of clock by described two-way I/O interface, realize the data input rate of twice under the low frequency clock.
In the present embodiment, the data that described two-way I/O interface is exported in the described storage unit can refer to:
Described two-way I/O interface receives first via data SO_H and the second circuit-switched data SO_L from described storage unit, export described first via data at the rising edge of described external timing signal SCK, export described second circuit-switched data at the negative edge of described external timing signal SCK; The output data that obtain are SO.
In the present embodiment, export two paths of data by described bidirectional interface respectively at rising edge and the negative edge of clock, realize the data output rate of twice under the low frequency clock.
Present embodiment mainly is that the I/O interface to serial interface flash memory improves, thereby can adopt double speed and extraneous exchange input/output signal I/O; Other ingredient of serial i/O interface quick flash storage, the transmission between the each several part, control implementation, and with the connectivity scenario of outside (such as also be connected among Fig. 1 high level Vcc, GND, signal CS#, W# and HOLD#) can same prior art.
In the present embodiment, described two-way I/O interface can also be used for described first, second circuit-switched data input results is carried out synchronously.
In the present embodiment, described two-way I/O interface can but be not limited in the rising edge of described external timing signal SCK is preserved described first, second circuit-switched data input results into described storage unit.
Can certainly be in the negative edge of described external timing signal SCK be preserved described first, second circuit-switched data input results into described storage unit.
In the present embodiment, described two-way I/O interface specifically can comprise input interface and output interface.
In the present embodiment, described input interface specifically can comprise:
First load module receives described external timing signal and input signal, is used for externally rising edge of clock signal described input signal is sampled, and obtains described first via data input results;
Second load module receives described external timing signal and input signal, is used for externally the negative edge of clock signal described input signal is sampled, and obtains the described second circuit-switched data input results;
The input synchronization module receives described external timing signal and first, second circuit-switched data input results, and being used for externally, described first, second circuit-switched data input results of rising edge of clock signal output arrives described storage unit.
In the present embodiment, a kind of embodiment of described input interface as shown in Figure 2, described first load module is the first d type flip flop D1, CLK end directly connects described external timing signal Clock, the described input signal Data_in of D end connection.
Described second load module comprises the second d type flip flop D2 and first phase inverter; The CLK end of described second d type flip flop connects described external timing signal Clock by described first phase inverter, and the D end connects described input signal Data_in.
Described input synchronization module comprises 3d flip-flop D3 and four d flip-flop D4; The described the 3rd CLK end directly connects described external timing signal Clock, and the D end connects the Q end of described first d type flip flop, the described first via data input results SI_H of Q end output; The CLK end of described four d flip-flop directly connects described external timing signal Clock, and the D end connects the Q end of described second d type flip flop, the described second circuit-switched data input results SI_L of Q end output.
Wherein, the data rate of described input signal Data_in can reach the twice of described external timing signal Clock speed.As seen, the first d type flip flop D1 is in the rising edge sampled data of described external timing signal Clock, and the second d type flip flop D2 is in the negative edge sampled data of described external timing signal Clock.3d flip-flop D3 and four d flip-flop D4 make two-way input data all output to storage unit synchronously at the rising edge of Clock the data sync of first, second d type flip flop D1 and D2 output; Therefore, can under the situation that does not change described external timing signal frequency, realize that the input message transmission rate doubles.Simultaneously, at chip internal data rate is reduced, be convenient to subsequent treatment.
Be a kind of implementation of the input interface of present embodiment above, also can adopt other scheme to realize the input interface of present embodiment during practical application, as long as guarantee externally rising edge of clock signal and the equal sampled input signal of negative edge, and preserve described storage unit synchronously at the rising edge (or negative edge) of described external timing signal together.
In the present embodiment, described output interface specifically can comprise:
The output synchronization module is used for according to described external timing signal the staggered data of two-way of storage unit output being carried out synchronously;
Select module, be used for selecting one tunnel output according to the two paths of data of described external timing signal after synchronously.
In the present embodiment, a kind of embodiment of described output interface as shown in Figure 3, described storage unit can be exported the staggered data of two-way, SO_H and SO_L; Described output synchronization module comprises the 5th d type flip flop D5, the 6th d type flip flop D6; The CLK end of described the 5th d type flip flop connects described external timing signal Clock, and the D end connects from the first via data SO_H of described storage unit output; The CLK end of described the 6th d type flip flop connects described external timing signal Clock, and the D end connects from the second circuit-switched data SO_L of described storage unit output.
Described selection module is MUX MUX; Two input ends of described MUX MUX connect the Q end of described the 5th, the 6th d type flip flop respectively, selecting side sel connects described external timing signal Clock, when described external timing signal Clock is high level, select the data output of described the 5th d type flip flop Q end, when described external timing signal Clock is low level, select the data output of described the 6th d type flip flop Q end, obtain described output data Data_out.
As seen, trigger D5 and D6 are synchronous with two paths of data.When MUX MUX is high level at clock, select the output data of D5; When clock is low level, select the output data of D6; Under the situation that does not change clock frequency, realized doubling of data output rate.
A kind of implementation of the output interface of present embodiment just also can adopt other scheme to realize the output interface of present embodiment during practical application above, as long as guarantee that externally rising edge of clock signal and negative edge are all exported data.
In the present embodiment, described two-way I/O interface can also comprise that one switches unit and an IO channel, and described switch unit is used for input interface and output interface one and switches to described IO channel and link to each other.
A kind of embodiment of present embodiment as shown in Figure 4, wherein input interface and output interface are respectively shown in Fig. 2,3; Described switch unit can but be not limited to comprise first, second triple gate (also can be described as three-state buffer) and second phase inverter; The Enable Pin ENB of described first triple gate receives I/O control signal I/O_ctl, input end connects described I/O passage, output terminal connects described input interface, specifically, is first, second load module (being first, second d type flip flop D1, the D2 among Fig. 4) that connects in the described input interface; The Enable Pin ENB of described second triple gate receives I/O control signal I/O_ctl by described second phase inverter, input end connects described output interface, specifically, be the selection module (being the MUX MUX among Fig. 4) that connects in the described output interface, output terminal connects described I/O passage.
In the example shown in Figure 4, when I/O control signal I/O_ctl was high level, first triple gate was high-impedance state, and second triple gate is connected, and this moment, the I/O passage linked to each other with output interface, and output channel is opened, and realized the data output rate of twice this moment; When I/O control signal I/O_ctl was low level, second triple gate was high-impedance state, and first triple gate is connected, and this moment, the I/O passage linked to each other with input interface, and input channel is opened, and realizes the data input rate of twice.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (10)
1. serial i/O interface quick flash storage comprises:
Two-way I/O interface, storage unit;
It is characterized in that:
Described two-way I/O interface is used for receiving external timing signal and input signal, externally rising edge of clock signal is sampled to described input signal, obtain the first via according to input results, at the negative edge of described external timing signal described input signal is sampled, obtain the second the tunnel according to input results; First, second circuit-switched data input results is preserved in the described storage unit; And export data in the described storage unit.
2. serial i as claimed in claim 1/O interface quick flash storage is characterized in that, the data that described two-way I/O interface is exported in the described storage unit refer to:
Described two-way I/O interface receives first via data and second circuit-switched data from described storage unit, exports described first via data at the rising edge of described external timing signal, exports described second circuit-switched data at the negative edge of described external timing signal.
3. serial i as claimed in claim 1/O interface quick flash storage is characterized in that:
Described two-way I/O interface also is used for described first, second circuit-switched data input results is carried out synchronously.
4. serial i as claimed in claim 1/O interface quick flash storage is characterized in that:
Described two-way I/O interface is in the rising edge of described external timing signal is preserved described first, second circuit-switched data input results into described storage unit.
5. serial i according to any one of claims 1 to 4/O interface quick flash storage is characterized in that, described two-way I/O interface comprises:
Input interface and output interface;
Described input interface comprises:
First load module receives described external timing signal and input signal, is used for externally rising edge of clock signal described input signal is sampled, and obtains described first via data input results;
Second load module receives described external timing signal and input signal, is used for externally the negative edge of clock signal described input signal is sampled, and obtains the described second circuit-switched data input results;
The input synchronization module receives described external timing signal and first, second circuit-switched data input results, and being used for externally, described first, second circuit-switched data input results of rising edge of clock signal output arrives described storage unit.
6. serial i as claimed in claim 5/O interface quick flash storage is characterized in that:
Described first load module is first d type flip flop, and the CLK end directly connects described external timing signal, and the D end connects described input signal;
Described second load module comprises second d type flip flop and first phase inverter; The CLK end of described second d type flip flop connects described external timing signal by described first phase inverter, and the D end connects described input signal;
Described input synchronization module comprises 3d flip-flop and four d flip-flop; The described the 3rd CLK end directly connects described external timing signal, and the D end connects the Q end of described first d type flip flop, the described first via data input results of Q end output; The CLK end of described four d flip-flop directly connects described external timing signal, and the D end connects the Q end of described second d type flip flop, the described second circuit-switched data input results of Q end output.
7. serial i as claimed in claim 5/O interface quick flash storage is characterized in that, described output interface comprises:
The output synchronization module is used for according to described external timing signal the staggered data of two-way of storage unit output being carried out synchronously;
Select module, be used for selecting one tunnel output according to the two paths of data of described external timing signal after synchronously.
8. serial i as claimed in claim 7/O interface quick flash storage is characterized in that:
Described output synchronization module comprises the 5th d type flip flop, the 6th d type flip flop; The CLK end of described the 5th d type flip flop connects described external timing signal, and the D end connects from the first via data of described storage unit output; The CLK end of described the 6th d type flip flop connects described external timing signal, and the D end connects from second circuit-switched data of described storage unit output;
Described selection module is MUX; Two input ends of described MUX connect the Q end of described the 5th, the 6th d type flip flop respectively, the selecting side connects described external timing signal, when described external timing signal is high level, select the data output of described the 5th d type flip flop Q end, when described external timing signal is low level, select the data output of described the 6th d type flip flop Q end.
9. serial i as claimed in claim 5/O interface quick flash storage is characterized in that:
In the present embodiment, described two-way I/O interface can also comprise that one switches unit and an IO channel, and described switch unit is used for input interface and output interface one and switches to described IO channel and link to each other.
10. serial i as claimed in claim 9/O interface quick flash storage is characterized in that, described switch unit comprises:
First, second triple gate and second phase inverter;
The Enable Pin of described first triple gate receives the I/O control signal, and input end connects described I/O passage, and output terminal connects described input interface;
The Enable Pin of described second triple gate receives the I/O control signal by described second phase inverter, and input end connects described output interface;
When the I/O control signal was high level, first triple gate was high-impedance state, and second triple gate is connected, and the I/O passage links to each other with output interface; When the I/O control signal was low level, second triple gate was high-impedance state, and first triple gate is connected, and the I/O passage links to each other with input interface.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111210861A (en) * | 2019-12-30 | 2020-05-29 | 深圳市芯天下技术有限公司 | Flash memory |
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| US20030053489A1 (en) * | 1997-10-10 | 2003-03-20 | Rambus, Inc. | Method and apparatus for fail-safe resynchronization with minimum latency |
| US20030194018A1 (en) * | 2002-04-15 | 2003-10-16 | Chi Chang | High speed data transmitter and transmitting method thereof |
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| CN111210861A (en) * | 2019-12-30 | 2020-05-29 | 深圳市芯天下技术有限公司 | Flash memory |
| WO2021135662A1 (en) * | 2019-12-30 | 2021-07-08 | 芯天下技术股份有限公司 | Flash memory |
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