CN103235534A - OTP (one time programmable) single chip microcomputer framework and method for realizing multi-time programming - Google Patents
OTP (one time programmable) single chip microcomputer framework and method for realizing multi-time programming Download PDFInfo
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- CN103235534A CN103235534A CN2013101072322A CN201310107232A CN103235534A CN 103235534 A CN103235534 A CN 103235534A CN 2013101072322 A CN2013101072322 A CN 2013101072322A CN 201310107232 A CN201310107232 A CN 201310107232A CN 103235534 A CN103235534 A CN 103235534A
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Abstract
The invention discloses an OTP (one time programmable) single chip microcomputer framework and a method for realizing multi-time programming. An offset address storage area is reserved in a program storage in the OTP single chip microcomputer. Every time the single chip microcomputer is programmed, an end address of programming of this time is written in the storage area after being added 1. When the single chip microcomputer is reset, an offset address reading module reads data from the area. By the single chip microcomputer framework and the method for realizing multi-time programming, the program storage of the single chip microcomputer can be used for many times without influencing normal operation of the single chip microcomputer, multi-time programming can be realized, and using efficiency of the single chip microcomputer can be improved.
Description
Technical field
The present invention relates to the single-chip microcomputer field, the inside structure of OTP single-chip microcomputer of saying so exactly and the implementation method of repeatedly programming.
Background technology
OTP type single-chip microcomputer, because stable performance, low price is widely used in the various electronic products.In traditional single-chip microcomputer framework, as shown in Figure 1, processor cores carries out procedure stores by instruction address, each programming, and the single-chip microcomputer course of work is as follows.
1, system powers on.
2, instruction address is reset to 0, and processor cores is started working.
3, processor cores is carried out the instruction that store 0 address, and produces the next instruction address.
4, processor is carried out the instruction of storing in the instruction address that upward one-period produces, and continues to produce the next instruction address.
5, repeat 4 steps.
The address of its program storage of single-chip microcomputer is instruction address in the prior art, is directly produced by processor cores.Therefore this class single-chip microcomputer is merely able to carry out one-time programming, even user's program code byte number seldom, has only taken a very little part in the otp memory, and remainder also can't re-use, and causes waste.
Summary of the invention
For addressing the above problem, the purpose of this utility model is, design a kind of OTP single-chip microcomputer framework and realize repeatedly programmed method, this single-chip microcomputer framework and realize that repeatedly programmed method makes the program storage of single-chip microcomputer can gradation use, and do not influence the operate as normal of single-chip microcomputer, and can realize repeatedly programming, improve the service efficiency of single-chip microcomputer.
Another purpose of the present utility model is to provide a kind of OTP single-chip microcomputer framework and realizes repeatedly programmed method, and this single-chip microcomputer framework and realize that repeatedly programmed method is simple in structure is easy to realize, can improve the work efficiency of single-chip microcomputer, reduces cost.
For achieving the above object, technical scheme of the present invention is as follows.
A kind of OTP single-chip microcomputer framework, it has processor cores, order register and program storage, it is characterized in that described program storage is provided with the offset address memory block, described single-chip microcomputer framework also includes offset address register and offset address read module, described offset address register is connected in processor cores, described offset address read module is connected in described offset address memory block, and described offset address read module is connected in the offset address register again.
In the single-chip microcomputer framework disclosed by the invention.In program storage, opened up an offset address memory block.After single-chip microcomputer being programmed at every turn, all to add one to the end address of this programming and be written in this memory block, when single-chip microcomputer resets, read data from this memory block.Adopt single-chip microcomputer framework of the present invention, the program storage of single-chip microcomputer is not as long as also use, remaining space is enough stored new program code, just can programme next time, and needn't as prior art, programme again, can save the resource of program storage greatly, improve the service efficiency of single-chip microcomputer.
Described single-chip microcomputer framework, also comprise a totalizer, totalizer is arranged between processor cores and the offset address register, the offset address that store the instruction address that last one-period is produced and offset address memory block carries out computing, the instruction address that obtains is input to program storage, carries out instruction accordingly.
The method that a kind of OTP chip microcontroller is repeatedly programmed, it is characterized in that system's electrifying startup after, instruction address resets, the instruction of the address pointer of program storage is not carried out since 0 address, but begins to carry out from pre-loaded offset address.
Described pre-loaded offset address, the end address when for the last time single-chip microcomputer being programmed adds one, if for the first time single-chip microcomputer is programmed, then offset address is 0.
Above-mentioned end address when once single-chip microcomputer being programmed is stored in the offset address memory block in the program storage, and the offset address read module reads offset address from the offset address memory block, the concurrent processing device kernel signal of starting working.
Further, in the processor cores course of normal operation, the address pointer of described program storage is not directly to be produced by processor cores, but is undertaken producing after the computing by the instruction address of processor cores generation and pre-loaded offset address.
Specifically, the detailed operation process of described OTP single-chip microcomputer is as follows.
101, system powers on;
102, instruction address is reset to 0, and processor cores is in reset mode, waits for the control signal of offset address read module;
103, the offset address read module reads offset address from the offset address memory block, and the concurrent processing device kernel signal of starting working is loaded into offset address the offset address register simultaneously;
104, the offset address with 0 address and offset address register carries out the program memory address that computing produces, and processor cores is carried out the instruction of this program memory address, and produces the next instruction address;
105, go up the new program memory address that instruction address that one-period produces and the computing of offset address register produce, processor cores is carried out the instruction of new program memory address, and generation next instruction address;
106, repeating step 105.
In described 103 steps, if the offset address read module only reads a data recording, illustrate that single-chip microcomputer only carried out one-time programming, need not to load offset address, in other words, offset address is 0.When data recording herein surpasses one, then read the second last bar offset address, and be loaded in the offset address register.
After programming finished, the end address of programming added one and is written in the offset address memory block.
After adopting structure of the present invention, the storer of single-chip microcomputer is not as long as also use, and remaining space enough stores new program code, just can programme next time.Can transfer OTP type MCU to MTP type MCU, make the program storage of single-chip microcomputer gradation to use, and not influence the operate as normal of single-chip microcomputer, and can realize repeatedly programming, improve the service efficiency of single-chip microcomputer greatly.
And the present invention is simple in structure, is easy to realize, can improve the work efficiency of single-chip microcomputer, reduces cost.
Description of drawings
Fig. 1 is the configuration diagram of prior art.
Fig. 2 is the configuration diagram of single-chip microcomputer that the present invention implements.
Fig. 3 is software control flow chart of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
Please refer to shown in Figure 2, a kind of OTP single-chip microcomputer framework that the present invention realizes, it has processor cores, order register and program storage, it is characterized in that described program storage is provided with the offset address memory block, described single-chip microcomputer framework also includes offset address register and offset address read module, described offset address register is connected in processor cores, described offset address read module is connected in described offset address memory block, and described offset address read module is connected in the offset address register again.
In the OTP single-chip microcomputer framework that the present invention implements, in program storage, opened up an offset address memory block.After single-chip microcomputer being programmed at every turn, all to add one to the end address of this programming and be written in this memory block, when single-chip microcomputer resets, read data from this memory block.
Please refer to shown in Figure 3ly, the control flow that the present invention repeatedly programmes by described OTP chip microcontroller is as follows.
101, system powers on.
102, instruction address is reset to 0, and processor cores is in reset mode, waits for the control signal of offset address read module.
103, the offset address read module reads offset address from the offset address memory block, the concurrent processing device kernel signal of starting working.
104, processor cores is carried out the instruction that store address that 0 address and the computing of offset address register value produce, and produces the next instruction address.
105, the instruction that store the address that the instruction address that one-period produced on processor was carried out and the computing of offset address register produce, and produce the next instruction address.
It is just constant that offset address in the offset address register is that 103 steps load the back, behind each system closedown, last end address is stored in the offset address memory block, so that read during the next time start.
106, repeating step 105.
After programming finished, the end address of programming added one and is written in the offset address memory block.
In 103 steps, if the offset address read module only reads a data recording, illustrate that single-chip microcomputer only carried out one-time programming, need not to load offset address, in other words, offset address is 0.When data recording herein surpasses one, then read the second last bar offset address, and be loaded in the offset address register.
If have only a data recording, illustrate that this single-chip microcomputer only carried out one-time programming, need not to load offset address, in other words, offset address is 0.When data recording herein surpasses one, then read last two offset addresss, and be loaded in the offset address register.After loading was finished, the offset address read module sent signal, allowed processor cores start working (before this, processor cores is in reset mode).In the processor cores course of normal operation, the address of program storage, the instruction address and the offset address register that are produced by processor cores obtain through after the computing.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. OTP single-chip microcomputer framework, it has processor cores, order register and program storage, it is characterized in that described program storage is provided with the offset address memory block, described single-chip microcomputer framework also includes offset address register and offset address read module, described offset address register is connected in processor cores, described offset address read module is connected in described offset address memory block, and described offset address read module is connected in the offset address register again.
2. OTP single-chip microcomputer framework as claimed in claim 1, it is characterized in that described single-chip microcomputer framework, also comprise a totalizer, totalizer is arranged between processor cores and the offset address register, the offset address that store the instruction address that last one-period is produced and offset address memory block carries out computing, the instruction address that obtains is input to program storage, carries out instruction accordingly.
3. method that the OTP chip microcontroller is repeatedly programmed, it is characterized in that system's electrifying startup after, instruction address resets, the instruction of the address pointer of program storage is not carried out since 0 address, but begins to carry out from pre-loaded offset address.
4. the OTP chip microcontroller as claimed in claim 3 method of repeatedly programming, it is characterized in that described pre-loaded offset address, end address when for the last time single-chip microcomputer being programmed adds one, if for the first time single-chip microcomputer is programmed, then offset address is 0.
5. the OTP chip microcontroller as claimed in claim 4 method of repeatedly programming, it is characterized in that above-mentioned end address when once single-chip microcomputer being programmed is stored in the offset address memory block in the program storage, the offset address read module reads offset address from the offset address memory block, the concurrent processing device kernel signal of starting working.
6. the OTP chip microcontroller as claimed in claim 3 method of repeatedly programming, it is characterized in that further, in the processor cores course of normal operation, the address pointer of described program storage is to be undertaken producing after the computing by the instruction address of processor cores generation and pre-loaded offset address.
7. the OTP chip microcontroller as claimed in claim 3 method of repeatedly programming is characterized in that specifically the detailed operation process of described OTP single-chip microcomputer is:
101, system powers on;
102, instruction address is reset to 0, and processor cores is in reset mode, waits for the control signal of offset address read module;
103, the offset address read module reads offset address from the offset address memory block, and the concurrent processing device kernel signal of starting working is loaded into offset address the offset address register simultaneously;
104, the offset address with 0 address and offset address register carries out the program memory address that computing produces, and processor cores is carried out the instruction of this program memory address, and produces the next instruction address;
105, go up the new program memory address that instruction address that one-period produces and the computing of offset address register produce, processor cores is carried out the instruction of new program memory address, and generation next instruction address;
106, repeating step 105.
8. the OTP chip microcontroller as claimed in claim 7 method of repeatedly programming, it is characterized in that in described 103 steps, if the offset address read module only reads a data recording, illustrate that single-chip microcomputer only carried out one-time programming, need not to load offset address, when data recording herein surpasses one, then read the second last bar offset address, and be loaded in the offset address register.
9. the OTP chip microcontroller as claimed in claim 8 method of repeatedly programming, it is characterized in that programming finishes after, the end address of programming adds one and is written in the offset address memory block.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59189407A (en) * | 1983-04-13 | 1984-10-27 | Hitachi Ltd | Sequence control device |
| CN1570869A (en) * | 2004-04-29 | 2005-01-26 | 中国科学院大气物理研究所 | Technology for increasing service efficiency of OTP type single-chip microcomputer |
| CN201508547U (en) * | 2009-05-18 | 2010-06-16 | 蚌埠依爱消防电子有限责任公司 | Handheld USB programming device |
| CN102364430A (en) * | 2010-09-17 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Microcontroller for supporting multi-programming on one time programmable memory and programming method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59189407A (en) * | 1983-04-13 | 1984-10-27 | Hitachi Ltd | Sequence control device |
| CN1570869A (en) * | 2004-04-29 | 2005-01-26 | 中国科学院大气物理研究所 | Technology for increasing service efficiency of OTP type single-chip microcomputer |
| CN201508547U (en) * | 2009-05-18 | 2010-06-16 | 蚌埠依爱消防电子有限责任公司 | Handheld USB programming device |
| CN102364430A (en) * | 2010-09-17 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Microcontroller for supporting multi-programming on one time programmable memory and programming method |
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Address after: 518000, A building, block 9, garden city digital garden, 1079 Nanhai Road, Guangdong, Shenzhen, Nanshan District Patentee after: Chipsea Technology (Shenzhen) Co., Ltd. Address before: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |