CN107844321B - MCU processing system - Google Patents
MCU processing system Download PDFInfo
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- CN107844321B CN107844321B CN201610837925.0A CN201610837925A CN107844321B CN 107844321 B CN107844321 B CN 107844321B CN 201610837925 A CN201610837925 A CN 201610837925A CN 107844321 B CN107844321 B CN 107844321B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/261—Microinstruction address formation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
Abstract
The invention provides an MCU processing system, comprising: the device comprises a data memory, an ALU arithmetic unit, a data selector and an address selector; the address selector is connected to the data memory, and the data memory is connected to the data selector through a data bus; the data selector is connected with the input end of the ALU arithmetic unit. The efficiency of the MCU processing system is higher.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to an MCU processing system.
Background
A Micro Control Unit (MCU), also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer (MCU), is a Chip-level computer that can properly reduce the frequency and specification of a Central Processing Unit (CPU), and can integrate peripheral interfaces such as a memory (memory), a counter (Timer), a USB, an a/D conversion, a UART, a PLC, a DMA, and even external circuits such as an LCD driving circuit, etc. on a Single Chip, to perform different combination control for different applications. Such as mobile phones, PC peripherals, remote controls, automotive electronics, industrial stepper motors, robotic arm controls, etc., see the silhouette of the MCU.
The efficiency of the existing MCU processing system in operating on data in the data memory needs to be improved.
Disclosure of Invention
The invention aims to improve the efficiency of the MCU processing system in operating the data in the data memory.
To solve the foregoing technical problem, an embodiment of the present invention provides an MCU processing system, including: the device comprises a data memory, an ALU arithmetic unit, a data selector and an address selector; the address selector is connected to the data memory, and the data memory is connected to the data selector through a data bus; the data selector is connected with the input end of the ALU arithmetic unit.
Optionally, the data memory includes a plurality of memory locations, and the address selector is adapted to select a memory location in the data memory based on a decoding result of the direct addressing instruction.
Optionally, the data selector is adapted to read data of the selected memory location through the data bus based on the decoding result of the direct addressing instruction, and provide the data of the memory location to the ALU unit.
Optionally, the output of the ALU unit is connected to the data memory via the data bus.
Optionally, the ALU unit is adapted to write the operation result to the memory location selected by the address selector through the data bus.
Optionally, the MCU processing system further includes: an instruction register coupled to the address selector and the data selector, respectively.
Optionally, the MCU processing system further includes: a register bank adapted to provide data to the ALU operation unit and/or to store operation results from the ALU operation unit.
Optionally, the address selector is adapted to obtain an address from the register set based on a decoding result of the indirect addressing instruction, so as to select a memory location in the data memory to which the address points according to the address.
Optionally, the MCU processing system is adapted to a reduced instruction set.
Optionally, the data memory is an SRAM.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, the MCU processing system comprises a data memory, an ALU arithmetic unit, a data selector and an address selector. The address selector is connected to the data memory, the data memory is connected to the data selector through a data bus, and the data selector is connected with the input end of the ALU arithmetic unit. Therefore, the address selector can directly select the data memory, and the data in the data memory can directly reach the ALU arithmetic unit through the data bus and the data selector, so that the ALU arithmetic unit can indirectly acquire the data in the data memory without a register set, and the MCU processing system can improve the efficiency of operating the data in the data memory.
Further, the data memory includes a plurality of memory locations, and the address selector may select a memory location in the data memory based on a result of the decoding of the direct addressing instruction. Therefore, the selecting process of the storage unit in the data storage can be simplified, and the efficiency of operating the data in the data storage is further improved.
Furthermore, the output end of the ALU arithmetic unit is connected to the data memory through the bus, the ALU arithmetic unit can directly write the arithmetic result into the memory cell selected by the address selector through the data bus, and the data in the register group is not required to be stored into the memory cell of the data memory after the arithmetic result is stored in the register group, so that the operation steps can be reduced, and the efficiency of operating the memory cell can be further improved.
Drawings
Fig. 1 is a schematic structural diagram of an MCU processing system according to an embodiment of the present invention.
Detailed Description
As mentioned above, the efficiency of the existing MCU processing system to operate on data in the data memory needs to be improved.
The inventor researches and discovers that the existing MCU processing system can not directly carry out operation on the data in the data memory, and the efficiency is low because a plurality of instructions are needed to realize the operation on the data in the data memory. For example, when data in the data register is added, the data in the data memory needs to be read out to the register group first, and then the data stored in the register group is used to perform the addition operation, which results in many operation steps.
In the embodiment of the invention, the MCU processing system comprises a data memory, an ALU arithmetic unit, a data selector and an address selector. The address selector is connected to the data memory, the data memory is connected to the data selector through a data bus, and the data selector is connected with the input end of the ALU arithmetic unit. Therefore, the address selector can directly select the data memory, and the data in the data memory can directly reach the ALU arithmetic unit through the data bus and the data selector, so that the ALU arithmetic unit can indirectly acquire the data in the data memory without a register set, and the MCU processing system can improve the efficiency of operating the data in the data memory.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic structural diagram of an MCU processing system according to an embodiment of the present invention.
As shown in fig. 1, the MCU processing system in this embodiment mainly includes: a data memory 11, an ALU operation unit 12, a data selector 13, and an address selector 14. The MCU processing system may also include a data bus 17 and a register set 16.
Wherein, the output end of the address selector 14 is connected to the data memory 11, and the data memory 11 is connected to the input end of the data selector 13 through a data bus 17; the output of the data selector 13 is connected to the input of the ALU operator 12.
Since the data memory 11 is connected to the data selector 13 through the data bus 17, and the data selector 13 is connected to the input end of the ALU arithmetic unit 12, the ALU arithmetic unit 12 can directly obtain the data in the data memory 11 through the data bus 17 and the data selector 13 without transferring through the register set 16, thereby improving the efficiency of the arithmetic operation on the data in the data memory 11.
In a specific implementation, the data storage 11 may include a plurality of storage units, and the storage units may be selected by the address selector 14, so as to perform data reading and writing operations on the selected storage units. The address selector 14 may select a memory location in the data memory 11 based on the direct addressing instruction decoding result.
In one implementation, the direct addressing instruction is decoded by instruction register 15 to generate a direct addressing instruction decoding result. The address in the data memory 11 of the data to be operated on is carried in the direct addressing instruction. The address may be transferred to the data memory 11 by the address selector 14, thereby selecting the memory location in the data memory 11 to which the address points. It should be noted that the direct addressing instruction may be any instruction in the instruction set that supports direct addressing of data memory 11, and is not limited to a particular instruction set.
When the existing MCU processing system calculates the data in the data memory, the address of the memory unit to be selected needs to be stored in the register group based on the indirect addressing instruction, and then the address selector acquires the address of the memory unit from the register group according to the decoding result of the indirect addressing instruction to select and operate the memory unit.
For example, when data in the data memory needs to be acquired, an address of the data needs to be assigned to a certain register in the register set, the data stored in the storage unit needs to be read to another register in the register set by using an indirect addressing mode, and then the data read to the register needs to be further operated.
In the embodiment of the present invention, the address selector 14 may directly select the memory location in the data memory 11 based on the direct addressing instruction, and the data of the selected memory location is transmitted to the ALU unit 12 via the data memory bus 17 and the data selector 13, without storing the address of the memory location to be selected in the register set 16. Therefore, the processes of selecting the storage units in the data storage 11 and acquiring the data can be simplified, and the efficiency of operating the data storage 11 is improved.
In a specific implementation, the data selector 13 may obtain the data of the selected memory location through the data bus 17 based on the decoding result of the direct addressing instruction, and provide the data of the memory location to the ALU operation unit 12.
In the existing MCU processing system, the ALU unit can only obtain the data in the data memory through the register set, but in the embodiment of the present invention, the ALU unit 12 can directly obtain the data in the data memory 11 through the data bus 17 and the data selector 13, so the efficiency of the MCU processing system can be improved.
In a specific implementation, the MCU processing system may further include an instruction register 15, and the instruction register 15 is connected to an input terminal of the address selector 14 and an input terminal of the data selector 13, respectively. The instruction register 15 may decode an instruction and may control the address selector 14 and the data selector 13, for example, the address selector 14 and the data selector 13 by a decoding result generated by the decoding.
More specifically, the decoding result may include an address and data, and the address is transmitted to the address selector 14 and the data is transmitted to the data selector 13. The decoding result may further include control signals to control the address selector 14 to select an appropriate address output from the addresses of the plurality of input terminals and to control the data selector 13 to select an appropriate data output from the data of the plurality of input terminals.
For example, the instruction register 15 may control the data selector 13 to communicate the data bus 17 and the ALU operation unit 12 by decoding the result or other suitable means, so that the ALU operation unit 12 may obtain the data in the data memory 11 from the data bus 17 for subsequent operations.
In particular implementations, the output of the ALU arithmetic unit 12 may be connected to the data memory 11 via the data bus 17. Accordingly, the operation result of the ALU operation unit 12 may be written into the memory location selected by the address selector 14 through the data bus 17.
In the existing MCU processing system, when calculating data in the data memory, it is necessary to read the data in the data memory to the register first; after the ALU arithmetic unit finishes the operation, the operation result is returned to the register; and writing the value in the register back to the data memory.
In the embodiment of the present invention, the ALU unit 12 may directly obtain the data in the data memory 11 through the data bus 17 without passing through a register, and after the ALU unit 12 completes the operation, the operation result may be directly written back to the original memory unit through the data bus 17. Therefore, the MCU processing system in the embodiment of the invention has simpler process of operating the data memory 11 and higher efficiency.
In particular implementations, the register sets 16 in the MCU processing system may provide data to the ALU arithmetic unit 12, store arithmetic results from the ALU arithmetic unit 12, and/or provide addresses to the address selector 14.
The MCU processing system in the embodiment of the present invention may also support an indirect addressing mode to select a storage unit in the data storage 11. Specifically, the address selector 14 may obtain an address from the register bank 16 based on a decoding result of the indirect addressing instruction, so as to select a memory location in the data memory 11, to which the address points, according to the address.
In particular implementations, the register banks 16 include multiple register banks that may be divided into main register bank and auxiliary register banks, where the main register bank supports access for all instructions related to operation of the register bank 16, and the auxiliary register bank supports access for only a portion of the instructions related to operation of the register bank 16.
In one non-limiting example, register set 16 includes a plurality of register sets R0-R7 that may be divided into main register sets R0-R3 and auxiliary register sets R4-R7. All instructions related to the operation of register set 16 may operate on the main register sets R0-R3; while only a portion of the instructions may operate on the auxiliary register sets R4-R7.
Only the main register set R0-R3 supports all operations involving the register set 16, so that the address of the register set 16 occupies a smaller number of bits in the instruction system; where necessary, partial instructions may operate on the auxiliary register sets R4-R7, such that the auxiliary register sets R4-R7 are in addition to the main register sets R0-R3. Therefore, the resource occupied by the register set 16 in the instruction system can be reduced while the system performance is ensured.
The MCU processing system in the embodiment of the present invention may be applicable to a reduced instruction set, wherein the data storage 11 may be an SRAM, for example, an on-chip SRAM. The MCU processing system may be fully integrated on a single chip, i.e. the modules in fig. 1 are all integrated on a single chip, or may be partially integrated on a single chip.
To describe the MCU processing system in the embodiment of the present invention in more detail, specific instructions and execution processes of the MCU processing system in the embodiment of the present invention are further described below as an example.
In an embodiment of the present invention, the data in the data memory may be read out in a direct addressing manner, and after the data in the data memory and the data in the register are calculated, the result is stored in the data memory. For example, the following instructions may be executed:
ADD 0x80，R0 (1)
the register R0 can be added to the data in the memory cell 0x80 by the instruction (1), and the calculation result is stored to the memory cell with the address of 0x 80.
In the process of executing the instruction (1), the instruction register decodes the instruction (1), the decoding result obtained by decoding comprises the address of the storage unit, the address selector selects the storage unit with the address of 0x80 according to the decoding result of the instruction register, and the stored data is transmitted to the ALU arithmetic unit through the data bus and the data selector. The ALU operation unit obtains the data stored in the register R0 according to the instruction of the decoding result of the instruction register, and adds the data stored in the register R0 to the data in the storage unit 0x80 to obtain an operation result.
Based on the decoded result of instruction (1), the ALU arithmetic unit may write the arithmetic result to a memory location of address 0x80 in the data memory through the data bus, and during the writing, the address selector selects the memory location of address 0x 80. If the calculation process of the instruction (1) is implemented based on the existing MCU processing system, multiple instructions need to be passed, for example:
MOV R1，#0x80 (2)
LD R2，[R1] (3)
ADD R2，R0 (4)
ST[R1]，R2 (5)
wherein: by instruction (2), the contents of register R1 are assigned to address 0x80 of the memory cell; in the instruction (3), the data in the register R1 is addressed as the address of the memory cell, and the data in the memory cell with the address of 0x80 is assigned to the register R2; in the instruction (4), the data in the register R0 and the data in the register R2 are added, and the operation result is stored to the register R2; in instruction (5), the operation result held in the register R2 is written back to the memory cell with address 0x 80.
As can be seen from comparison, the operation which can be realized by the MCU processing system in the embodiment of the invention only needs 1 instruction can be completed by 4 instructions in the existing MCU processing system, so that the efficiency of the MCU processing system in the embodiment of the invention is higher.
In another embodiment of the present invention, the data in the data memory can be read out in a direct addressing manner, the data in the data memory and the data in the register are calculated, and the result is stored to the register. For example, the following instructions may be executed:
ADD R0，0x80 (6)
the data in the memory cell with the address 0x80 can be added to the data in the register R0 by the instruction (6), and the operation result is stored to R0.
During the execution of the instruction (6), the instruction register decodes the instruction (6), and the address selector selects a storage unit with the address of 0x80 in the data memory based on the decoded result; the data selector communicates the ALU operation unit and the data bus based on control of the instruction register, so that the ALU operation unit acquires data in the memory location having an address of 0x80 via the data bus and the data selector. Based on the decoded result of the instruction register, the ALU operation unit fetches the data in the register R0, and sums the data in the storage unit with address 0x80 with the data in R0, storing the result to the register R0.
If the instruction (6) is implemented in the existing MCU processing system, 3 instructions are needed to complete, for example:
MOV R1，#0x80
LD R2，[R1]
ADD R0，R2
the meaning of each of the three instructions can be referred to as instructions (2) to (4), and is not described herein again.
The MCU processing system in the embodiment of the present invention may also support other processing instructions for directly addressing the data memory, for example: SUB 0x80, R1; SUB R1, 0x80, etc., are not listed here.
The MCU processing system in the embodiment of the present invention may also be compatible with the instruction of the existing MCU processing system, such as the operation on the immediate and data in the register, the operation on the data in the register, the data loading based on the indirect addressing of the register, etc., including but not limited to: ADD R0, #0x 01; ADD R0, R1; LD R2, [ R1], and the like.
In the embodiment of the invention, the MCU processing system comprises a data memory, an ALU arithmetic unit, a data selector and an address selector. The address selector is connected to the data memory, the data memory is connected to the data selector through a data bus, and the data selector is connected with the input end of the ALU arithmetic unit. Therefore, the address selector can directly select the data memory, and the data in the data memory can directly reach the ALU arithmetic unit through the data bus and the data selector, so that the ALU arithmetic unit can indirectly acquire the data in the data memory without a register set, and the MCU processing system can improve the efficiency of operating the data in the data memory.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (5)
1. An MCU processing system, comprising: the device comprises a data memory, an ALU arithmetic unit, a data selector, an address selector and a register set;
the address selector is connected to the data memory, and the data memory is connected to the data selector through a data bus; the data selector is connected with the input end of the ALU arithmetic unit;
the data memory comprises a plurality of memory cells, and the address selector is suitable for selecting the memory cells in the data memory based on the decoding result of the direct addressing instruction; the ALU arithmetic unit is suitable for writing an arithmetic result into the memory cell selected by the address selector through the data bus;
an instruction register connected to the address selector and the data selector, respectively;
the register group is respectively connected to the address selector and the ALU operation unit, is suitable for providing data to the ALU operation unit and/or storing operation results from the ALU operation unit, and provides addresses to the address selector; the register banks include a plurality of main register banks and a plurality of auxiliary register banks, the main register banks supporting all operations involving the register banks such that addresses of the register banks occupy a smaller number of bits in an instruction system; the auxiliary register set is related to partial operation of the register set, and the auxiliary register set is complementary to the main register set, so that the resources occupied by the register set in an instruction system are reduced while the system performance is ensured;
the MCU processing system is suitable for a simplified instruction set.
2. The MCU processing system according to claim 1, wherein the data selector is adapted to read data of the selected memory location through the data bus and provide the data of the memory location to the ALU arithmetic unit based on the direct addressing instruction decoding result.
3. The MCU processing system of claim 1, wherein an output of the ALU arithmetic unit is connected to the data memory via the data bus.
4. The MCU processing system according to claim 1, wherein the address selector is adapted to obtain an address from the register set based on an indirect addressing instruction decoding result to select a memory location in the data memory to which the address points according to the address.
5. MCU processing system according to any of claims 1 to 4, characterized in that the data memory is an SRAM.
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| WO2020172988A1 (en) * | 2019-02-28 | 2020-09-03 | Huawei Technologies Co., Ltd. | Shader alu outlet control |
| CN110609705B (en) * | 2019-09-20 | 2021-05-11 | 深圳市航顺芯片技术研发有限公司 | Method for improving MCU bus efficiency, intelligent terminal, storage medium and chip |
| CN115244521A (en) * | 2020-05-06 | 2022-10-25 | 阿里巴巴集团控股有限公司 | Hierarchical method and system for storing data |
| CN111743755A (en) * | 2020-07-05 | 2020-10-09 | 上海宏勃生物科技发展有限公司 | System capable of detecting bath entering and bath exiting of patient |
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| US4276595A (en) * | 1978-06-30 | 1981-06-30 | International Business Machines Corporation | Microinstruction storage units employing partial address generators |
| US4491910A (en) * | 1982-02-22 | 1985-01-01 | Texas Instruments Incorporated | Microcomputer having data shift within memory |
| JPH05509425A (en) * | 1990-05-18 | 1993-12-22 | スター・セミコンダクター・コーポレーション | Programmable signal processor architecture |
| US5611075A (en) * | 1994-10-04 | 1997-03-11 | Analog Devices, Inc. | Bus architecture for digital signal processor allowing time multiplexed access to memory banks |
| US6996702B2 (en) * | 2001-07-31 | 2006-02-07 | Wis Technologies, Inc. | Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention |
| CN100538623C (en) * | 2006-12-08 | 2009-09-09 | 无锡华润矽科微电子有限公司 | A kind of 8 8-digit microcontrollers |
| US8055886B2 (en) * | 2007-07-12 | 2011-11-08 | Texas Instruments Incorporated | Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction |
| CN102262611B (en) * | 2010-05-25 | 2014-05-14 | 无锡华润矽科微电子有限公司 | 16-site RISC (Reduced Instruction-Set Computer) CUP (Central Processing Unit) system structure |
| CN102298352B (en) * | 2010-06-25 | 2012-11-28 | 中国科学院沈阳自动化研究所 | Specific processor system structure for high-performance programmable controller and implementation method of dedicated processor system structure |
| CN102184092A (en) * | 2011-05-04 | 2011-09-14 | 西安电子科技大学 | Special instruction set processor based on pipeline structure |
| CN103018753B (en) * | 2012-08-09 | 2014-11-05 | 江苏科技大学 | GPS (Global Position System) signal digital correlator |
| CN203745826U (en) * | 2013-12-31 | 2014-07-30 | 苏州市职业大学 | Multifunctional signal generator |
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Address after: 201203 zone a, floor 5, No. 201, Keyuan Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai Patentee after: Shanghai Xinwang Microelectronics Technology Co.,Ltd. Address before: 201203 zone a, floor 5, No. 201, Keyuan Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai Patentee before: SHANGHAI CHIPON MICRO ELECTRONIC TECHNOLOGY CO.,LTD. |
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